| stats.txt (11201:b1bd4afb6b16) | stats.txt (11245:1c5102c0a7a9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.906049 # Number of seconds simulated 4sim_ticks 1906048606500 # Number of ticks simulated 5final_tick 1906048606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.906049 # Number of seconds simulated 4sim_ticks 1906048606500 # Number of ticks simulated 5final_tick 1906048606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 269376 # Simulator instruction rate (inst/s) 8host_op_rate 269376 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9144869235 # Simulator tick rate (ticks/s) 10host_mem_usage 376080 # Number of bytes of host memory used 11host_seconds 208.43 # Real time elapsed on the host | 7host_inst_rate 268534 # Simulator instruction rate (inst/s) 8host_op_rate 268534 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9116285517 # Simulator tick rate (ticks/s) 10host_mem_usage 332204 # Number of bytes of host memory used 11host_seconds 209.08 # Real time elapsed on the host |
| 12sim_insts 56145568 # Number of instructions simulated 13sim_ops 56145568 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 1044672 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25904384 # Number of bytes read from this memory --- 125 unchanged lines hidden (view full) --- 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1565 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1858 # What write queue length does an incoming req see | 12sim_insts 56145568 # Number of instructions simulated 13sim_ops 56145568 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 1044672 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25904384 # Number of bytes read from this memory --- 125 unchanged lines hidden (view full) --- 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1565 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1858 # What write queue length does an incoming req see |
| 153system.physmem.wrQLenPdf::17 5601 # What write queue length does an incoming req see | 153system.physmem.wrQLenPdf::17 5600 # What write queue length does an incoming req see |
| 154system.physmem.wrQLenPdf::18 5604 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 6269 # What write queue length does an incoming req see | 154system.physmem.wrQLenPdf::18 5604 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 6269 # What write queue length does an incoming req see |
| 156system.physmem.wrQLenPdf::20 6564 # What write queue length does an incoming req see | 156system.physmem.wrQLenPdf::20 6565 # What write queue length does an incoming req see |
| 157system.physmem.wrQLenPdf::21 5995 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 6437 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 7880 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 8284 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 9349 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8331 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8705 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 7504 # What write queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 192system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see | 157system.physmem.wrQLenPdf::21 5995 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 6437 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 7880 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 8284 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 9349 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8331 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8705 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 7504 # What write queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 192system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see |
| 200system.physmem.bytesPerActivate::samples 64393 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 519.603311 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 318.318586 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 407.156918 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 14830 23.03% 23.03% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 11097 17.23% 40.26% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4950 7.69% 47.95% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3246 5.04% 52.99% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2531 3.93% 56.92% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1970 3.06% 59.98% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 4174 6.48% 66.46% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1358 2.11% 68.57% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 20237 31.43% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 64393 # Bytes accessed per row activation | 200system.physmem.bytesPerActivate::samples 64400 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 519.546832 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 318.268868 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 407.153797 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 14837 23.04% 23.04% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 11098 17.23% 40.27% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4944 7.68% 47.95% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3257 5.06% 53.01% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2526 3.92% 56.93% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1968 3.06% 59.98% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 4176 6.48% 66.47% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1357 2.11% 68.58% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 20237 31.42% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 64400 # Bytes accessed per row activation |
| 214system.physmem.rdPerTurnAround::samples 5302 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 76.317050 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2899.726540 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5299 99.94% 99.94% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::total 5302 # Reads before turning the bus around for writes --- 33 unchanged lines hidden (view full) --- 255system.physmem.wrPerTurnAround::168-171 2 0.04% 99.72% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::176-179 3 0.06% 99.77% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::180-183 8 0.15% 99.92% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::204-207 1 0.02% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::total 5302 # Writes before turning the bus around for reads | 214system.physmem.rdPerTurnAround::samples 5302 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 76.317050 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2899.726540 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5299 99.94% 99.94% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::total 5302 # Reads before turning the bus around for writes --- 33 unchanged lines hidden (view full) --- 255system.physmem.wrPerTurnAround::168-171 2 0.04% 99.72% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::176-179 3 0.06% 99.77% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::180-183 8 0.15% 99.92% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::204-207 1 0.02% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::total 5302 # Writes before turning the bus around for reads |
| 263system.physmem.totQLat 2636864500 # Total ticks spent queuing 264system.physmem.totMemAccLat 10223958250 # Total ticks spent from burst creation until serviced by the DRAM | 263system.physmem.totQLat 2637486000 # Total ticks spent queuing 264system.physmem.totMemAccLat 10224579750 # Total ticks spent from burst creation until serviced by the DRAM |
| 265system.physmem.totBusLat 2023225000 # Total ticks spent in databus transfers | 265system.physmem.totBusLat 2023225000 # Total ticks spent in databus transfers |
| 266system.physmem.avgQLat 6516.49 # Average queueing delay per DRAM burst | 266system.physmem.avgQLat 6518.02 # Average queueing delay per DRAM burst |
| 267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 268system.physmem.avgMemAccLat 25266.49 # Average memory access latency per DRAM burst | 268system.physmem.avgMemAccLat 25268.02 # Average memory access latency per DRAM burst |
| 269system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s 270system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s 271system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s 272system.physmem.avgWrBWSys 3.97 # Average system write bandwidth in MiByte/s 273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 274system.physmem.busUtil 0.14 # Data bus utilization in percentage 275system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 276system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 277system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 278system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing | 269system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s 270system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s 271system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s 272system.physmem.avgWrBWSys 3.97 # Average system write bandwidth in MiByte/s 273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 274system.physmem.busUtil 0.14 # Data bus utilization in percentage 275system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 276system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 277system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 278system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing |
| 279system.physmem.readRowHits 362818 # Number of row buffer hits during reads 280system.physmem.writeRowHits 95583 # Number of row buffer hits during writes | 279system.physmem.readRowHits 362820 # Number of row buffer hits during reads 280system.physmem.writeRowHits 95574 # Number of row buffer hits during writes |
| 281system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads 282system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes 283system.physmem.avgGap 3644923.65 # Average gap between requests 284system.physmem.pageHitRate 87.68 # Row buffer hit rate, read and write combined | 281system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads 282system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes 283system.physmem.avgGap 3644923.65 # Average gap between requests 284system.physmem.pageHitRate 87.68 # Row buffer hit rate, read and write combined |
| 285system.physmem_0.actEnergy 237542760 # Energy for activate commands per rank (pJ) 286system.physmem_0.preEnergy 129611625 # Energy for precharge commands per rank (pJ) | 285system.physmem_0.actEnergy 237573000 # Energy for activate commands per rank (pJ) 286system.physmem_0.preEnergy 129628125 # Energy for precharge commands per rank (pJ) |
| 287system.physmem_0.readEnergy 1576816800 # Energy for read commands per rank (pJ) 288system.physmem_0.writeEnergy 380077920 # Energy for write commands per rank (pJ) 289system.physmem_0.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) | 287system.physmem_0.readEnergy 1576816800 # Energy for read commands per rank (pJ) 288system.physmem_0.writeEnergy 380077920 # Energy for write commands per rank (pJ) 289system.physmem_0.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) |
| 290system.physmem_0.actBackEnergy 67952834145 # Energy for active background per rank (pJ) 291system.physmem_0.preBackEnergy 1084018111500 # Energy for precharge background per rank (pJ) 292system.physmem_0.totalEnergy 1278788448510 # Total energy per rank (pJ) 293system.physmem_0.averagePower 670.912661 # Core power per rank (mW) 294system.physmem_0.memoryStateTime::IDLE 1803102997000 # Time in different power states | 290system.physmem_0.actBackEnergy 67955758245 # Energy for active background per rank (pJ) 291system.physmem_0.preBackEnergy 1084015546500 # Energy for precharge background per rank (pJ) 292system.physmem_0.totalEnergy 1278788854350 # Total energy per rank (pJ) 293system.physmem_0.averagePower 670.912874 # Core power per rank (mW) 294system.physmem_0.memoryStateTime::IDLE 1803098707000 # Time in different power states |
| 295system.physmem_0.memoryStateTime::REF 63646960000 # Time in different power states 296system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 295system.physmem_0.memoryStateTime::REF 63646960000 # Time in different power states 296system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 297system.physmem_0.memoryStateTime::ACT 39293158000 # Time in different power states | 297system.physmem_0.memoryStateTime::ACT 39297448000 # Time in different power states |
| 298system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 298system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 299system.physmem_1.actEnergy 249268320 # Energy for activate commands per rank (pJ) 300system.physmem_1.preEnergy 136009500 # Energy for precharge commands per rank (pJ) | 299system.physmem_1.actEnergy 249291000 # Energy for activate commands per rank (pJ) 300system.physmem_1.preEnergy 136021875 # Energy for precharge commands per rank (pJ) |
| 301system.physmem_1.readEnergy 1579414200 # Energy for read commands per rank (pJ) 302system.physmem_1.writeEnergy 385527600 # Energy for write commands per rank (pJ) 303system.physmem_1.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) | 301system.physmem_1.readEnergy 1579414200 # Energy for read commands per rank (pJ) 302system.physmem_1.writeEnergy 385527600 # Energy for write commands per rank (pJ) 303system.physmem_1.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) |
| 304system.physmem_1.actBackEnergy 68401366290 # Energy for active background per rank (pJ) 305system.physmem_1.preBackEnergy 1083624670500 # Energy for precharge background per rank (pJ) 306system.physmem_1.totalEnergy 1278869710170 # Total energy per rank (pJ) 307system.physmem_1.averagePower 670.955290 # Core power per rank (mW) 308system.physmem_1.memoryStateTime::IDLE 1802449451000 # Time in different power states | 304system.physmem_1.actBackEnergy 68412640320 # Energy for active background per rank (pJ) 305system.physmem_1.preBackEnergy 1083614781000 # Energy for precharge background per rank (pJ) 306system.physmem_1.totalEnergy 1278871129755 # Total energy per rank (pJ) 307system.physmem_1.averagePower 670.956034 # Core power per rank (mW) 308system.physmem_1.memoryStateTime::IDLE 1802432810250 # Time in different power states |
| 309system.physmem_1.memoryStateTime::REF 63646960000 # Time in different power states 310system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 309system.physmem_1.memoryStateTime::REF 63646960000 # Time in different power states 310system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 311system.physmem_1.memoryStateTime::ACT 39946717750 # Time in different power states | 311system.physmem_1.memoryStateTime::ACT 39963358500 # Time in different power states |
| 312system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 313system.cpu.branchPred.lookups 15009028 # Number of BP lookups 314system.cpu.branchPred.condPredicted 13018563 # Number of conditional branches predicted 315system.cpu.branchPred.condIncorrect 370758 # Number of conditional branches incorrect 316system.cpu.branchPred.BTBLookups 9666577 # Number of BTB lookups 317system.cpu.branchPred.BTBHits 5199223 # Number of BTB hits 318system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 319system.cpu.branchPred.BTBHitPct 53.785564 # BTB Hit Percentage --- 50 unchanged lines hidden (view full) --- 370system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl 371system.cpu.kern.ipl_count::31 105906 57.95% 100.00% # number of times we switched to this ipl 372system.cpu.kern.ipl_count::total 182748 # number of times we switched to this ipl 373system.cpu.kern.ipl_good::0 73438 49.32% 49.32% # number of times we switched to this ipl from a different ipl 374system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl 375system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl 376system.cpu.kern.ipl_good::31 73439 49.32% 100.00% # number of times we switched to this ipl from a different ipl 377system.cpu.kern.ipl_good::total 148914 # number of times we switched to this ipl from a different ipl | 312system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 313system.cpu.branchPred.lookups 15009028 # Number of BP lookups 314system.cpu.branchPred.condPredicted 13018563 # Number of conditional branches predicted 315system.cpu.branchPred.condIncorrect 370758 # Number of conditional branches incorrect 316system.cpu.branchPred.BTBLookups 9666577 # Number of BTB lookups 317system.cpu.branchPred.BTBHits 5199223 # Number of BTB hits 318system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 319system.cpu.branchPred.BTBHitPct 53.785564 # BTB Hit Percentage --- 50 unchanged lines hidden (view full) --- 370system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl 371system.cpu.kern.ipl_count::31 105906 57.95% 100.00% # number of times we switched to this ipl 372system.cpu.kern.ipl_count::total 182748 # number of times we switched to this ipl 373system.cpu.kern.ipl_good::0 73438 49.32% 49.32% # number of times we switched to this ipl from a different ipl 374system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl 375system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl 376system.cpu.kern.ipl_good::31 73439 49.32% 100.00% # number of times we switched to this ipl from a different ipl 377system.cpu.kern.ipl_good::total 148914 # number of times we switched to this ipl from a different ipl |
| 378system.cpu.kern.ipl_ticks::0 1837271257000 96.39% 96.39% # number of cycles we spent at this ipl | 378system.cpu.kern.ipl_ticks::0 1837271633000 96.39% 96.39% # number of cycles we spent at this ipl |
| 379system.cpu.kern.ipl_ticks::21 83690500 0.00% 96.40% # number of cycles we spent at this ipl 380system.cpu.kern.ipl_ticks::22 707098000 0.04% 96.43% # number of cycles we spent at this ipl | 379system.cpu.kern.ipl_ticks::21 83690500 0.00% 96.40% # number of cycles we spent at this ipl 380system.cpu.kern.ipl_ticks::22 707098000 0.04% 96.43% # number of cycles we spent at this ipl |
| 381system.cpu.kern.ipl_ticks::31 67985555000 3.57% 100.00% # number of cycles we spent at this ipl | 381system.cpu.kern.ipl_ticks::31 67985179000 3.57% 100.00% # number of cycles we spent at this ipl |
| 382system.cpu.kern.ipl_ticks::total 1906047600500 # number of cycles we spent at this ipl 383system.cpu.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl 384system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 385system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 386system.cpu.kern.ipl_used::31 0.693436 # fraction of swpipl calls that actually changed the ipl 387system.cpu.kern.ipl_used::total 0.814860 # fraction of swpipl calls that actually changed the ipl 388system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 389system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed --- 52 unchanged lines hidden (view full) --- 442system.cpu.kern.mode_switch_good::kernel 0.324370 # fraction of useful protection mode switches 443system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 444system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches 445system.cpu.kern.mode_switch_good::total 0.392706 # fraction of useful protection mode switches 446system.cpu.kern.mode_ticks::kernel 38721238500 2.03% 2.03% # number of ticks spent at the given mode 447system.cpu.kern.mode_ticks::user 4530290000 0.24% 2.27% # number of ticks spent at the given mode 448system.cpu.kern.mode_ticks::idle 1862796062000 97.73% 100.00% # number of ticks spent at the given mode 449system.cpu.kern.swap_context 4175 # number of times the context was actually changed | 382system.cpu.kern.ipl_ticks::total 1906047600500 # number of cycles we spent at this ipl 383system.cpu.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl 384system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 385system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 386system.cpu.kern.ipl_used::31 0.693436 # fraction of swpipl calls that actually changed the ipl 387system.cpu.kern.ipl_used::total 0.814860 # fraction of swpipl calls that actually changed the ipl 388system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 389system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed --- 52 unchanged lines hidden (view full) --- 442system.cpu.kern.mode_switch_good::kernel 0.324370 # fraction of useful protection mode switches 443system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 444system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches 445system.cpu.kern.mode_switch_good::total 0.392706 # fraction of useful protection mode switches 446system.cpu.kern.mode_ticks::kernel 38721238500 2.03% 2.03% # number of ticks spent at the given mode 447system.cpu.kern.mode_ticks::user 4530290000 0.24% 2.27% # number of ticks spent at the given mode 448system.cpu.kern.mode_ticks::idle 1862796062000 97.73% 100.00% # number of ticks spent at the given mode 449system.cpu.kern.swap_context 4175 # number of times the context was actually changed |
| 450system.cpu.tickCycles 84511190 # Number of cycles that the object actually ticked 451system.cpu.idleCycles 137195507 # Total number of cycles that the object has spent stopped | 450system.cpu.tickCycles 84511215 # Number of cycles that the object actually ticked 451system.cpu.idleCycles 137195482 # Total number of cycles that the object has spent stopped |
| 452system.cpu.dcache.tags.replacements 1395430 # number of replacements 453system.cpu.dcache.tags.tagsinuse 511.976766 # Cycle average of tags in use 454system.cpu.dcache.tags.total_refs 13774781 # Total number of references to valid blocks. 455system.cpu.dcache.tags.sampled_refs 1395942 # Sample count of references to valid blocks. 456system.cpu.dcache.tags.avg_refs 9.867732 # Average number of references to valid blocks. 457system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit. 458system.cpu.dcache.tags.occ_blocks::cpu.data 511.976766 # Average occupied blocks per requestor 459system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy --- 22 unchanged lines hidden (view full) --- 482system.cpu.dcache.WriteReq_misses::cpu.data 575205 # number of WriteReq misses 483system.cpu.dcache.WriteReq_misses::total 575205 # number of WriteReq misses 484system.cpu.dcache.LoadLockedReq_misses::cpu.data 17224 # number of LoadLockedReq misses 485system.cpu.dcache.LoadLockedReq_misses::total 17224 # number of LoadLockedReq misses 486system.cpu.dcache.demand_misses::cpu.data 1776836 # number of demand (read+write) misses 487system.cpu.dcache.demand_misses::total 1776836 # number of demand (read+write) misses 488system.cpu.dcache.overall_misses::cpu.data 1776836 # number of overall misses 489system.cpu.dcache.overall_misses::total 1776836 # number of overall misses | 452system.cpu.dcache.tags.replacements 1395430 # number of replacements 453system.cpu.dcache.tags.tagsinuse 511.976766 # Cycle average of tags in use 454system.cpu.dcache.tags.total_refs 13774781 # Total number of references to valid blocks. 455system.cpu.dcache.tags.sampled_refs 1395942 # Sample count of references to valid blocks. 456system.cpu.dcache.tags.avg_refs 9.867732 # Average number of references to valid blocks. 457system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit. 458system.cpu.dcache.tags.occ_blocks::cpu.data 511.976766 # Average occupied blocks per requestor 459system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy --- 22 unchanged lines hidden (view full) --- 482system.cpu.dcache.WriteReq_misses::cpu.data 575205 # number of WriteReq misses 483system.cpu.dcache.WriteReq_misses::total 575205 # number of WriteReq misses 484system.cpu.dcache.LoadLockedReq_misses::cpu.data 17224 # number of LoadLockedReq misses 485system.cpu.dcache.LoadLockedReq_misses::total 17224 # number of LoadLockedReq misses 486system.cpu.dcache.demand_misses::cpu.data 1776836 # number of demand (read+write) misses 487system.cpu.dcache.demand_misses::total 1776836 # number of demand (read+write) misses 488system.cpu.dcache.overall_misses::cpu.data 1776836 # number of overall misses 489system.cpu.dcache.overall_misses::total 1776836 # number of overall misses |
| 490system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974936500 # number of ReadReq miss cycles 491system.cpu.dcache.ReadReq_miss_latency::total 46974936500 # number of ReadReq miss cycles 492system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956179000 # number of WriteReq miss cycles 493system.cpu.dcache.WriteReq_miss_latency::total 33956179000 # number of WriteReq miss cycles | 490system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974912500 # number of ReadReq miss cycles 491system.cpu.dcache.ReadReq_miss_latency::total 46974912500 # number of ReadReq miss cycles 492system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956321000 # number of WriteReq miss cycles 493system.cpu.dcache.WriteReq_miss_latency::total 33956321000 # number of WriteReq miss cycles |
| 494system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234952500 # number of LoadLockedReq miss cycles 495system.cpu.dcache.LoadLockedReq_miss_latency::total 234952500 # number of LoadLockedReq miss cycles | 494system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234952500 # number of LoadLockedReq miss cycles 495system.cpu.dcache.LoadLockedReq_miss_latency::total 234952500 # number of LoadLockedReq miss cycles |
| 496system.cpu.dcache.demand_miss_latency::cpu.data 80931115500 # number of demand (read+write) miss cycles 497system.cpu.dcache.demand_miss_latency::total 80931115500 # number of demand (read+write) miss cycles 498system.cpu.dcache.overall_miss_latency::cpu.data 80931115500 # number of overall miss cycles 499system.cpu.dcache.overall_miss_latency::total 80931115500 # number of overall miss cycles | 496system.cpu.dcache.demand_miss_latency::cpu.data 80931233500 # number of demand (read+write) miss cycles 497system.cpu.dcache.demand_miss_latency::total 80931233500 # number of demand (read+write) miss cycles 498system.cpu.dcache.overall_miss_latency::cpu.data 80931233500 # number of overall miss cycles 499system.cpu.dcache.overall_miss_latency::total 80931233500 # number of overall miss cycles |
| 500system.cpu.dcache.ReadReq_accesses::cpu.data 9017676 # number of ReadReq accesses(hits+misses) 501system.cpu.dcache.ReadReq_accesses::total 9017676 # number of ReadReq accesses(hits+misses) 502system.cpu.dcache.WriteReq_accesses::cpu.data 6152051 # number of WriteReq accesses(hits+misses) 503system.cpu.dcache.WriteReq_accesses::total 6152051 # number of WriteReq accesses(hits+misses) 504system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200051 # number of LoadLockedReq accesses(hits+misses) 505system.cpu.dcache.LoadLockedReq_accesses::total 200051 # number of LoadLockedReq accesses(hits+misses) 506system.cpu.dcache.StoreCondReq_accesses::cpu.data 199029 # number of StoreCondReq accesses(hits+misses) 507system.cpu.dcache.StoreCondReq_accesses::total 199029 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 514system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093498 # miss rate for WriteReq accesses 515system.cpu.dcache.WriteReq_miss_rate::total 0.093498 # miss rate for WriteReq accesses 516system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086098 # miss rate for LoadLockedReq accesses 517system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086098 # miss rate for LoadLockedReq accesses 518system.cpu.dcache.demand_miss_rate::cpu.data 0.117130 # miss rate for demand accesses 519system.cpu.dcache.demand_miss_rate::total 0.117130 # miss rate for demand accesses 520system.cpu.dcache.overall_miss_rate::cpu.data 0.117130 # miss rate for overall accesses 521system.cpu.dcache.overall_miss_rate::total 0.117130 # miss rate for overall accesses | 500system.cpu.dcache.ReadReq_accesses::cpu.data 9017676 # number of ReadReq accesses(hits+misses) 501system.cpu.dcache.ReadReq_accesses::total 9017676 # number of ReadReq accesses(hits+misses) 502system.cpu.dcache.WriteReq_accesses::cpu.data 6152051 # number of WriteReq accesses(hits+misses) 503system.cpu.dcache.WriteReq_accesses::total 6152051 # number of WriteReq accesses(hits+misses) 504system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200051 # number of LoadLockedReq accesses(hits+misses) 505system.cpu.dcache.LoadLockedReq_accesses::total 200051 # number of LoadLockedReq accesses(hits+misses) 506system.cpu.dcache.StoreCondReq_accesses::cpu.data 199029 # number of StoreCondReq accesses(hits+misses) 507system.cpu.dcache.StoreCondReq_accesses::total 199029 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 514system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093498 # miss rate for WriteReq accesses 515system.cpu.dcache.WriteReq_miss_rate::total 0.093498 # miss rate for WriteReq accesses 516system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086098 # miss rate for LoadLockedReq accesses 517system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086098 # miss rate for LoadLockedReq accesses 518system.cpu.dcache.demand_miss_rate::cpu.data 0.117130 # miss rate for demand accesses 519system.cpu.dcache.demand_miss_rate::total 0.117130 # miss rate for demand accesses 520system.cpu.dcache.overall_miss_rate::cpu.data 0.117130 # miss rate for overall accesses 521system.cpu.dcache.overall_miss_rate::total 0.117130 # miss rate for overall accesses |
| 522system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.646994 # average ReadReq miss latency 523system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.646994 # average ReadReq miss latency 524system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.177737 # average WriteReq miss latency 525system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.177737 # average WriteReq miss latency | 522system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.627021 # average ReadReq miss latency 523system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.627021 # average ReadReq miss latency 524system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.424605 # average WriteReq miss latency 525system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.424605 # average WriteReq miss latency |
| 526system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13640.995123 # average LoadLockedReq miss latency 527system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13640.995123 # average LoadLockedReq miss latency | 526system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13640.995123 # average LoadLockedReq miss latency 527system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13640.995123 # average LoadLockedReq miss latency |
| 528system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency 529system.cpu.dcache.demand_avg_miss_latency::total 45547.881459 # average overall miss latency 530system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency 531system.cpu.dcache.overall_avg_miss_latency::total 45547.881459 # average overall miss latency | 528system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency 529system.cpu.dcache.demand_avg_miss_latency::total 45547.947869 # average overall miss latency 530system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency 531system.cpu.dcache.overall_avg_miss_latency::total 45547.947869 # average overall miss latency |
| 532system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 533system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 534system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 535system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 536system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 537system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 538system.cpu.dcache.fast_writes 0 # number of fast writes performed 539system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 20 unchanged lines hidden (view full) --- 560system.cpu.dcache.overall_mshr_misses::cpu.data 1378760 # number of overall MSHR misses 561system.cpu.dcache.overall_mshr_misses::total 1378760 # number of overall MSHR misses 562system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable 563system.cpu.dcache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable 564system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable 565system.cpu.dcache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable 566system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses 567system.cpu.dcache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses | 532system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 533system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 534system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 535system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 536system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 537system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 538system.cpu.dcache.fast_writes 0 # number of fast writes performed 539system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 20 unchanged lines hidden (view full) --- 560system.cpu.dcache.overall_mshr_misses::cpu.data 1378760 # number of overall MSHR misses 561system.cpu.dcache.overall_mshr_misses::total 1378760 # number of overall MSHR misses 562system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable 563system.cpu.dcache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable 564system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable 565system.cpu.dcache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable 566system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses 567system.cpu.dcache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses |
| 568system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817588500 # number of ReadReq MSHR miss cycles 569system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817588500 # number of ReadReq MSHR miss cycles 570system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272399000 # number of WriteReq MSHR miss cycles 571system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272399000 # number of WriteReq MSHR miss cycles | 568system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817391500 # number of ReadReq MSHR miss cycles 569system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817391500 # number of ReadReq MSHR miss cycles 570system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272477000 # number of WriteReq MSHR miss cycles 571system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272477000 # number of WriteReq MSHR miss cycles |
| 572system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 217466000 # number of LoadLockedReq MSHR miss cycles 573system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217466000 # number of LoadLockedReq MSHR miss cycles | 572system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 217466000 # number of LoadLockedReq MSHR miss cycles 573system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217466000 # number of LoadLockedReq MSHR miss cycles |
| 574system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089987500 # number of demand (read+write) MSHR miss cycles 575system.cpu.dcache.demand_mshr_miss_latency::total 61089987500 # number of demand (read+write) MSHR miss cycles 576system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089987500 # number of overall MSHR miss cycles 577system.cpu.dcache.overall_mshr_miss_latency::total 61089987500 # number of overall MSHR miss cycles 578system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1530266500 # number of ReadReq MSHR uncacheable cycles 579system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1530266500 # number of ReadReq MSHR uncacheable cycles | 574system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089868500 # number of demand (read+write) MSHR miss cycles 575system.cpu.dcache.demand_mshr_miss_latency::total 61089868500 # number of demand (read+write) MSHR miss cycles 576system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089868500 # number of overall MSHR miss cycles 577system.cpu.dcache.overall_mshr_miss_latency::total 61089868500 # number of overall MSHR miss cycles 578system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529366500 # number of ReadReq MSHR uncacheable cycles 579system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529366500 # number of ReadReq MSHR uncacheable cycles |
| 580system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2162508500 # number of WriteReq MSHR uncacheable cycles 581system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2162508500 # number of WriteReq MSHR uncacheable cycles | 580system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2162508500 # number of WriteReq MSHR uncacheable cycles 581system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2162508500 # number of WriteReq MSHR uncacheable cycles |
| 582system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3692775000 # number of overall MSHR uncacheable cycles 583system.cpu.dcache.overall_mshr_uncacheable_latency::total 3692775000 # number of overall MSHR uncacheable cycles | 582system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3691875000 # number of overall MSHR uncacheable cycles 583system.cpu.dcache.overall_mshr_uncacheable_latency::total 3691875000 # number of overall MSHR uncacheable cycles |
| 584system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119139 # mshr miss rate for ReadReq accesses 585system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119139 # mshr miss rate for ReadReq accesses 586system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049480 # mshr miss rate for WriteReq accesses 587system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049480 # mshr miss rate for WriteReq accesses 588system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086083 # mshr miss rate for LoadLockedReq accesses 589system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086083 # mshr miss rate for LoadLockedReq accesses 590system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090889 # mshr miss rate for demand accesses 591system.cpu.dcache.demand_mshr_miss_rate::total 0.090889 # mshr miss rate for demand accesses 592system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090889 # mshr miss rate for overall accesses 593system.cpu.dcache.overall_mshr_miss_rate::total 0.090889 # mshr miss rate for overall accesses | 584system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119139 # mshr miss rate for ReadReq accesses 585system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119139 # mshr miss rate for ReadReq accesses 586system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049480 # mshr miss rate for WriteReq accesses 587system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049480 # mshr miss rate for WriteReq accesses 588system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086083 # mshr miss rate for LoadLockedReq accesses 589system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086083 # mshr miss rate for LoadLockedReq accesses 590system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090889 # mshr miss rate for demand accesses 591system.cpu.dcache.demand_mshr_miss_rate::total 0.090889 # mshr miss rate for demand accesses 592system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090889 # mshr miss rate for overall accesses 593system.cpu.dcache.overall_mshr_miss_rate::total 0.090889 # mshr miss rate for overall accesses |
| 594system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40785.018453 # average ReadReq mshr miss latency 595system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40785.018453 # average ReadReq mshr miss latency 596system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.508845 # average WriteReq mshr miss latency 597system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.508845 # average WriteReq mshr miss latency | 594system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40784.835087 # average ReadReq mshr miss latency 595system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40784.835087 # average ReadReq mshr miss latency 596system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.765083 # average WriteReq mshr miss latency 597system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.765083 # average WriteReq mshr miss latency |
| 598system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12627.954242 # average LoadLockedReq mshr miss latency 599system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12627.954242 # average LoadLockedReq mshr miss latency | 598system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12627.954242 # average LoadLockedReq mshr miss latency 599system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12627.954242 # average LoadLockedReq mshr miss latency |
| 600system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.919797 # average overall mshr miss latency 601system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.919797 # average overall mshr miss latency 602system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.919797 # average overall mshr miss latency 603system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.919797 # average overall mshr miss latency 604system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220690.294202 # average ReadReq mshr uncacheable latency 605system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220690.294202 # average ReadReq mshr uncacheable latency | 600system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency 601system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency 602system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency 603system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency 604system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.498990 # average ReadReq mshr uncacheable latency 605system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.498990 # average ReadReq mshr uncacheable latency |
| 606system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224699.553200 # average WriteReq mshr uncacheable latency 607system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224699.553200 # average WriteReq mshr uncacheable latency | 606system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224699.553200 # average WriteReq mshr uncacheable latency 607system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224699.553200 # average WriteReq mshr uncacheable latency |
| 608system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223020.594275 # average overall mshr uncacheable latency 609system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223020.594275 # average overall mshr uncacheable latency | 608system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222966.239884 # average overall mshr uncacheable latency 609system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222966.239884 # average overall mshr uncacheable latency |
| 610system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 611system.cpu.icache.tags.replacements 1460396 # number of replacements 612system.cpu.icache.tags.tagsinuse 508.105648 # Cycle average of tags in use | 610system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 611system.cpu.icache.tags.replacements 1460396 # number of replacements 612system.cpu.icache.tags.tagsinuse 508.105648 # Cycle average of tags in use |
| 613system.cpu.icache.tags.total_refs 18947784 # Total number of references to valid blocks. | 613system.cpu.icache.tags.total_refs 18947783 # Total number of references to valid blocks. |
| 614system.cpu.icache.tags.sampled_refs 1460907 # Sample count of references to valid blocks. | 614system.cpu.icache.tags.sampled_refs 1460907 # Sample count of references to valid blocks. |
| 615system.cpu.icache.tags.avg_refs 12.969877 # Average number of references to valid blocks. | 615system.cpu.icache.tags.avg_refs 12.969876 # Average number of references to valid blocks. |
| 616system.cpu.icache.tags.warmup_cycle 50119711500 # Cycle when the warmup percentage was hit. 617system.cpu.icache.tags.occ_blocks::cpu.inst 508.105648 # Average occupied blocks per requestor 618system.cpu.icache.tags.occ_percent::cpu.inst 0.992394 # Average percentage of cache occupancy 619system.cpu.icache.tags.occ_percent::total 0.992394 # Average percentage of cache occupancy 620system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 621system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 622system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 623system.cpu.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id 624system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 616system.cpu.icache.tags.warmup_cycle 50119711500 # Cycle when the warmup percentage was hit. 617system.cpu.icache.tags.occ_blocks::cpu.inst 508.105648 # Average occupied blocks per requestor 618system.cpu.icache.tags.occ_percent::cpu.inst 0.992394 # Average percentage of cache occupancy 619system.cpu.icache.tags.occ_percent::total 0.992394 # Average percentage of cache occupancy 620system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 621system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 622system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 623system.cpu.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id 624system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 625system.cpu.icache.tags.tag_accesses 21869953 # Number of tag accesses 626system.cpu.icache.tags.data_accesses 21869953 # Number of data accesses 627system.cpu.icache.ReadReq_hits::cpu.inst 18947787 # number of ReadReq hits 628system.cpu.icache.ReadReq_hits::total 18947787 # number of ReadReq hits 629system.cpu.icache.demand_hits::cpu.inst 18947787 # number of demand (read+write) hits 630system.cpu.icache.demand_hits::total 18947787 # number of demand (read+write) hits 631system.cpu.icache.overall_hits::cpu.inst 18947787 # number of overall hits 632system.cpu.icache.overall_hits::total 18947787 # number of overall hits | 625system.cpu.icache.tags.tag_accesses 21869952 # Number of tag accesses 626system.cpu.icache.tags.data_accesses 21869952 # Number of data accesses 627system.cpu.icache.ReadReq_hits::cpu.inst 18947786 # number of ReadReq hits 628system.cpu.icache.ReadReq_hits::total 18947786 # number of ReadReq hits 629system.cpu.icache.demand_hits::cpu.inst 18947786 # number of demand (read+write) hits 630system.cpu.icache.demand_hits::total 18947786 # number of demand (read+write) hits 631system.cpu.icache.overall_hits::cpu.inst 18947786 # number of overall hits 632system.cpu.icache.overall_hits::total 18947786 # number of overall hits |
| 633system.cpu.icache.ReadReq_misses::cpu.inst 1461083 # number of ReadReq misses 634system.cpu.icache.ReadReq_misses::total 1461083 # number of ReadReq misses 635system.cpu.icache.demand_misses::cpu.inst 1461083 # number of demand (read+write) misses 636system.cpu.icache.demand_misses::total 1461083 # number of demand (read+write) misses 637system.cpu.icache.overall_misses::cpu.inst 1461083 # number of overall misses 638system.cpu.icache.overall_misses::total 1461083 # number of overall misses | 633system.cpu.icache.ReadReq_misses::cpu.inst 1461083 # number of ReadReq misses 634system.cpu.icache.ReadReq_misses::total 1461083 # number of ReadReq misses 635system.cpu.icache.demand_misses::cpu.inst 1461083 # number of demand (read+write) misses 636system.cpu.icache.demand_misses::total 1461083 # number of demand (read+write) misses 637system.cpu.icache.overall_misses::cpu.inst 1461083 # number of overall misses 638system.cpu.icache.overall_misses::total 1461083 # number of overall misses |
| 639system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009217000 # number of ReadReq miss cycles 640system.cpu.icache.ReadReq_miss_latency::total 21009217000 # number of ReadReq miss cycles 641system.cpu.icache.demand_miss_latency::cpu.inst 21009217000 # number of demand (read+write) miss cycles 642system.cpu.icache.demand_miss_latency::total 21009217000 # number of demand (read+write) miss cycles 643system.cpu.icache.overall_miss_latency::cpu.inst 21009217000 # number of overall miss cycles 644system.cpu.icache.overall_miss_latency::total 21009217000 # number of overall miss cycles 645system.cpu.icache.ReadReq_accesses::cpu.inst 20408870 # number of ReadReq accesses(hits+misses) 646system.cpu.icache.ReadReq_accesses::total 20408870 # number of ReadReq accesses(hits+misses) 647system.cpu.icache.demand_accesses::cpu.inst 20408870 # number of demand (read+write) accesses 648system.cpu.icache.demand_accesses::total 20408870 # number of demand (read+write) accesses 649system.cpu.icache.overall_accesses::cpu.inst 20408870 # number of overall (read+write) accesses 650system.cpu.icache.overall_accesses::total 20408870 # number of overall (read+write) accesses | 639system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009954000 # number of ReadReq miss cycles 640system.cpu.icache.ReadReq_miss_latency::total 21009954000 # number of ReadReq miss cycles 641system.cpu.icache.demand_miss_latency::cpu.inst 21009954000 # number of demand (read+write) miss cycles 642system.cpu.icache.demand_miss_latency::total 21009954000 # number of demand (read+write) miss cycles 643system.cpu.icache.overall_miss_latency::cpu.inst 21009954000 # number of overall miss cycles 644system.cpu.icache.overall_miss_latency::total 21009954000 # number of overall miss cycles 645system.cpu.icache.ReadReq_accesses::cpu.inst 20408869 # number of ReadReq accesses(hits+misses) 646system.cpu.icache.ReadReq_accesses::total 20408869 # number of ReadReq accesses(hits+misses) 647system.cpu.icache.demand_accesses::cpu.inst 20408869 # number of demand (read+write) accesses 648system.cpu.icache.demand_accesses::total 20408869 # number of demand (read+write) accesses 649system.cpu.icache.overall_accesses::cpu.inst 20408869 # number of overall (read+write) accesses 650system.cpu.icache.overall_accesses::total 20408869 # number of overall (read+write) accesses |
| 651system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071591 # miss rate for ReadReq accesses 652system.cpu.icache.ReadReq_miss_rate::total 0.071591 # miss rate for ReadReq accesses 653system.cpu.icache.demand_miss_rate::cpu.inst 0.071591 # miss rate for demand accesses 654system.cpu.icache.demand_miss_rate::total 0.071591 # miss rate for demand accesses 655system.cpu.icache.overall_miss_rate::cpu.inst 0.071591 # miss rate for overall accesses 656system.cpu.icache.overall_miss_rate::total 0.071591 # miss rate for overall accesses | 651system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071591 # miss rate for ReadReq accesses 652system.cpu.icache.ReadReq_miss_rate::total 0.071591 # miss rate for ReadReq accesses 653system.cpu.icache.demand_miss_rate::cpu.inst 0.071591 # miss rate for demand accesses 654system.cpu.icache.demand_miss_rate::total 0.071591 # miss rate for demand accesses 655system.cpu.icache.overall_miss_rate::cpu.inst 0.071591 # miss rate for overall accesses 656system.cpu.icache.overall_miss_rate::total 0.071591 # miss rate for overall accesses |
| 657system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.208436 # average ReadReq miss latency 658system.cpu.icache.ReadReq_avg_miss_latency::total 14379.208436 # average ReadReq miss latency 659system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.208436 # average overall miss latency 660system.cpu.icache.demand_avg_miss_latency::total 14379.208436 # average overall miss latency 661system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.208436 # average overall miss latency 662system.cpu.icache.overall_avg_miss_latency::total 14379.208436 # average overall miss latency | 657system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.712857 # average ReadReq miss latency 658system.cpu.icache.ReadReq_avg_miss_latency::total 14379.712857 # average ReadReq miss latency 659system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency 660system.cpu.icache.demand_avg_miss_latency::total 14379.712857 # average overall miss latency 661system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency 662system.cpu.icache.overall_avg_miss_latency::total 14379.712857 # average overall miss latency |
| 663system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 664system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 665system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 666system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 667system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 668system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 669system.cpu.icache.fast_writes 0 # number of fast writes performed 670system.cpu.icache.cache_copies 0 # number of cache copies performed 671system.cpu.icache.writebacks::writebacks 1460396 # number of writebacks 672system.cpu.icache.writebacks::total 1460396 # number of writebacks 673system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1461083 # number of ReadReq MSHR misses 674system.cpu.icache.ReadReq_mshr_misses::total 1461083 # number of ReadReq MSHR misses 675system.cpu.icache.demand_mshr_misses::cpu.inst 1461083 # number of demand (read+write) MSHR misses 676system.cpu.icache.demand_mshr_misses::total 1461083 # number of demand (read+write) MSHR misses 677system.cpu.icache.overall_mshr_misses::cpu.inst 1461083 # number of overall MSHR misses 678system.cpu.icache.overall_mshr_misses::total 1461083 # number of overall MSHR misses | 663system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 664system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 665system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 666system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 667system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 668system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 669system.cpu.icache.fast_writes 0 # number of fast writes performed 670system.cpu.icache.cache_copies 0 # number of cache copies performed 671system.cpu.icache.writebacks::writebacks 1460396 # number of writebacks 672system.cpu.icache.writebacks::total 1460396 # number of writebacks 673system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1461083 # number of ReadReq MSHR misses 674system.cpu.icache.ReadReq_mshr_misses::total 1461083 # number of ReadReq MSHR misses 675system.cpu.icache.demand_mshr_misses::cpu.inst 1461083 # number of demand (read+write) MSHR misses 676system.cpu.icache.demand_mshr_misses::total 1461083 # number of demand (read+write) MSHR misses 677system.cpu.icache.overall_mshr_misses::cpu.inst 1461083 # number of overall MSHR misses 678system.cpu.icache.overall_mshr_misses::total 1461083 # number of overall MSHR misses |
| 679system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548134000 # number of ReadReq MSHR miss cycles 680system.cpu.icache.ReadReq_mshr_miss_latency::total 19548134000 # number of ReadReq MSHR miss cycles 681system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548134000 # number of demand (read+write) MSHR miss cycles 682system.cpu.icache.demand_mshr_miss_latency::total 19548134000 # number of demand (read+write) MSHR miss cycles 683system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548134000 # number of overall MSHR miss cycles 684system.cpu.icache.overall_mshr_miss_latency::total 19548134000 # number of overall MSHR miss cycles | 679system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548871000 # number of ReadReq MSHR miss cycles 680system.cpu.icache.ReadReq_mshr_miss_latency::total 19548871000 # number of ReadReq MSHR miss cycles 681system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548871000 # number of demand (read+write) MSHR miss cycles 682system.cpu.icache.demand_mshr_miss_latency::total 19548871000 # number of demand (read+write) MSHR miss cycles 683system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548871000 # number of overall MSHR miss cycles 684system.cpu.icache.overall_mshr_miss_latency::total 19548871000 # number of overall MSHR miss cycles |
| 685system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for ReadReq accesses 686system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071591 # mshr miss rate for ReadReq accesses 687system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for demand accesses 688system.cpu.icache.demand_mshr_miss_rate::total 0.071591 # mshr miss rate for demand accesses 689system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for overall accesses 690system.cpu.icache.overall_mshr_miss_rate::total 0.071591 # mshr miss rate for overall accesses | 685system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for ReadReq accesses 686system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071591 # mshr miss rate for ReadReq accesses 687system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for demand accesses 688system.cpu.icache.demand_mshr_miss_rate::total 0.071591 # mshr miss rate for demand accesses 689system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for overall accesses 690system.cpu.icache.overall_mshr_miss_rate::total 0.071591 # mshr miss rate for overall accesses |
| 691system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.208436 # average ReadReq mshr miss latency 692system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.208436 # average ReadReq mshr miss latency 693system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.208436 # average overall mshr miss latency 694system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.208436 # average overall mshr miss latency 695system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.208436 # average overall mshr miss latency 696system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.208436 # average overall mshr miss latency | 691system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.712857 # average ReadReq mshr miss latency 692system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.712857 # average ReadReq mshr miss latency 693system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency 694system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency 695system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency 696system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency |
| 697system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 698system.cpu.l2cache.tags.replacements 339568 # number of replacements | 697system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 698system.cpu.l2cache.tags.replacements 339568 # number of replacements |
| 699system.cpu.l2cache.tags.tagsinuse 65260.797469 # Cycle average of tags in use | 699system.cpu.l2cache.tags.tagsinuse 65260.797416 # Cycle average of tags in use |
| 700system.cpu.l2cache.tags.total_refs 4999517 # Total number of references to valid blocks. 701system.cpu.l2cache.tags.sampled_refs 404730 # Sample count of references to valid blocks. 702system.cpu.l2cache.tags.avg_refs 12.352722 # Average number of references to valid blocks. 703system.cpu.l2cache.tags.warmup_cycle 9687465000 # Cycle when the warmup percentage was hit. | 700system.cpu.l2cache.tags.total_refs 4999517 # Total number of references to valid blocks. 701system.cpu.l2cache.tags.sampled_refs 404730 # Sample count of references to valid blocks. 702system.cpu.l2cache.tags.avg_refs 12.352722 # Average number of references to valid blocks. 703system.cpu.l2cache.tags.warmup_cycle 9687465000 # Cycle when the warmup percentage was hit. |
| 704system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251550 # Average occupied blocks per requestor 705system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395782 # Average occupied blocks per requestor 706system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150137 # Average occupied blocks per requestor | 704system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251440 # Average occupied blocks per requestor 705system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395876 # Average occupied blocks per requestor 706system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150100 # Average occupied blocks per requestor |
| 707system.cpu.l2cache.tags.occ_percent::writebacks 0.824680 # Average percentage of cache occupancy 708system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087347 # Average percentage of cache occupancy 709system.cpu.l2cache.tags.occ_percent::cpu.data 0.083773 # Average percentage of cache occupancy 710system.cpu.l2cache.tags.occ_percent::total 0.995801 # Average percentage of cache occupancy 711system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 712system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 713system.cpu.l2cache.tags.age_task_id_blocks_1024::1 883 # Occupied blocks per task id 714system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5611 # Occupied blocks per task id --- 31 unchanged lines hidden (view full) --- 746system.cpu.l2cache.demand_misses::cpu.inst 16324 # number of demand (read+write) misses 747system.cpu.l2cache.demand_misses::cpu.data 388866 # number of demand (read+write) misses 748system.cpu.l2cache.demand_misses::total 405190 # number of demand (read+write) misses 749system.cpu.l2cache.overall_misses::cpu.inst 16324 # number of overall misses 750system.cpu.l2cache.overall_misses::cpu.data 388866 # number of overall misses 751system.cpu.l2cache.overall_misses::total 405190 # number of overall misses 752system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 404000 # number of UpgradeReq miss cycles 753system.cpu.l2cache.UpgradeReq_miss_latency::total 404000 # number of UpgradeReq miss cycles | 707system.cpu.l2cache.tags.occ_percent::writebacks 0.824680 # Average percentage of cache occupancy 708system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087347 # Average percentage of cache occupancy 709system.cpu.l2cache.tags.occ_percent::cpu.data 0.083773 # Average percentage of cache occupancy 710system.cpu.l2cache.tags.occ_percent::total 0.995801 # Average percentage of cache occupancy 711system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 712system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 713system.cpu.l2cache.tags.age_task_id_blocks_1024::1 883 # Occupied blocks per task id 714system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5611 # Occupied blocks per task id --- 31 unchanged lines hidden (view full) --- 746system.cpu.l2cache.demand_misses::cpu.inst 16324 # number of demand (read+write) misses 747system.cpu.l2cache.demand_misses::cpu.data 388866 # number of demand (read+write) misses 748system.cpu.l2cache.demand_misses::total 405190 # number of demand (read+write) misses 749system.cpu.l2cache.overall_misses::cpu.inst 16324 # number of overall misses 750system.cpu.l2cache.overall_misses::cpu.data 388866 # number of overall misses 751system.cpu.l2cache.overall_misses::total 405190 # number of overall misses 752system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 404000 # number of UpgradeReq miss cycles 753system.cpu.l2cache.UpgradeReq_miss_latency::total 404000 # number of UpgradeReq miss cycles |
| 754system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837528000 # number of ReadExReq miss cycles 755system.cpu.l2cache.ReadExReq_miss_latency::total 14837528000 # number of ReadExReq miss cycles 756system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2141943000 # number of ReadCleanReq miss cycles 757system.cpu.l2cache.ReadCleanReq_miss_latency::total 2141943000 # number of ReadCleanReq miss cycles 758system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680651000 # number of ReadSharedReq miss cycles 759system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680651000 # number of ReadSharedReq miss cycles 760system.cpu.l2cache.demand_miss_latency::cpu.inst 2141943000 # number of demand (read+write) miss cycles 761system.cpu.l2cache.demand_miss_latency::cpu.data 48518179000 # number of demand (read+write) miss cycles 762system.cpu.l2cache.demand_miss_latency::total 50660122000 # number of demand (read+write) miss cycles 763system.cpu.l2cache.overall_miss_latency::cpu.inst 2141943000 # number of overall miss cycles 764system.cpu.l2cache.overall_miss_latency::cpu.data 48518179000 # number of overall miss cycles 765system.cpu.l2cache.overall_miss_latency::total 50660122000 # number of overall miss cycles | 754system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837606000 # number of ReadExReq miss cycles 755system.cpu.l2cache.ReadExReq_miss_latency::total 14837606000 # number of ReadExReq miss cycles 756system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2142680000 # number of ReadCleanReq miss cycles 757system.cpu.l2cache.ReadCleanReq_miss_latency::total 2142680000 # number of ReadCleanReq miss cycles 758system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680454000 # number of ReadSharedReq miss cycles 759system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680454000 # number of ReadSharedReq miss cycles 760system.cpu.l2cache.demand_miss_latency::cpu.inst 2142680000 # number of demand (read+write) miss cycles 761system.cpu.l2cache.demand_miss_latency::cpu.data 48518060000 # number of demand (read+write) miss cycles 762system.cpu.l2cache.demand_miss_latency::total 50660740000 # number of demand (read+write) miss cycles 763system.cpu.l2cache.overall_miss_latency::cpu.inst 2142680000 # number of overall miss cycles 764system.cpu.l2cache.overall_miss_latency::cpu.data 48518060000 # number of overall miss cycles 765system.cpu.l2cache.overall_miss_latency::total 50660740000 # number of overall miss cycles |
| 766system.cpu.l2cache.WritebackDirty_accesses::writebacks 838232 # number of WritebackDirty accesses(hits+misses) 767system.cpu.l2cache.WritebackDirty_accesses::total 838232 # number of WritebackDirty accesses(hits+misses) 768system.cpu.l2cache.WritebackClean_accesses::writebacks 1459802 # number of WritebackClean accesses(hits+misses) 769system.cpu.l2cache.WritebackClean_accesses::total 1459802 # number of WritebackClean accesses(hits+misses) 770system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses) 771system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) 772system.cpu.l2cache.ReadExReq_accesses::cpu.data 304414 # number of ReadExReq accesses(hits+misses) 773system.cpu.l2cache.ReadExReq_accesses::total 304414 # number of ReadExReq accesses(hits+misses) --- 18 unchanged lines hidden (view full) --- 792system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011173 # miss rate for demand accesses 793system.cpu.l2cache.demand_miss_rate::cpu.data 0.278565 # miss rate for demand accesses 794system.cpu.l2cache.demand_miss_rate::total 0.141825 # miss rate for demand accesses 795system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011173 # miss rate for overall accesses 796system.cpu.l2cache.overall_miss_rate::cpu.data 0.278565 # miss rate for overall accesses 797system.cpu.l2cache.overall_miss_rate::total 0.141825 # miss rate for overall accesses 798system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22444.444444 # average UpgradeReq miss latency 799system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22444.444444 # average UpgradeReq miss latency | 766system.cpu.l2cache.WritebackDirty_accesses::writebacks 838232 # number of WritebackDirty accesses(hits+misses) 767system.cpu.l2cache.WritebackDirty_accesses::total 838232 # number of WritebackDirty accesses(hits+misses) 768system.cpu.l2cache.WritebackClean_accesses::writebacks 1459802 # number of WritebackClean accesses(hits+misses) 769system.cpu.l2cache.WritebackClean_accesses::total 1459802 # number of WritebackClean accesses(hits+misses) 770system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses) 771system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) 772system.cpu.l2cache.ReadExReq_accesses::cpu.data 304414 # number of ReadExReq accesses(hits+misses) 773system.cpu.l2cache.ReadExReq_accesses::total 304414 # number of ReadExReq accesses(hits+misses) --- 18 unchanged lines hidden (view full) --- 792system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011173 # miss rate for demand accesses 793system.cpu.l2cache.demand_miss_rate::cpu.data 0.278565 # miss rate for demand accesses 794system.cpu.l2cache.demand_miss_rate::total 0.141825 # miss rate for demand accesses 795system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011173 # miss rate for overall accesses 796system.cpu.l2cache.overall_miss_rate::cpu.data 0.278565 # miss rate for overall accesses 797system.cpu.l2cache.overall_miss_rate::total 0.141825 # miss rate for overall accesses 798system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22444.444444 # average UpgradeReq miss latency 799system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22444.444444 # average UpgradeReq miss latency |
| 800system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.169443 # average ReadExReq miss latency 801system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.169443 # average ReadExReq miss latency 802system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131214.346974 # average ReadCleanReq miss latency 803system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131214.346974 # average ReadCleanReq miss latency 804system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.759286 # average ReadSharedReq miss latency 805system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.759286 # average ReadSharedReq miss latency 806system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency 807system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency 808system.cpu.l2cache.demand_avg_miss_latency::total 125028.065846 # average overall miss latency 809system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency 810system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency 811system.cpu.l2cache.overall_avg_miss_latency::total 125028.065846 # average overall miss latency | 800system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.838058 # average ReadExReq miss latency 801system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.838058 # average ReadExReq miss latency 802system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131259.495222 # average ReadCleanReq miss latency 803system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131259.495222 # average ReadCleanReq miss latency 804system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.035572 # average ReadSharedReq miss latency 805system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.035572 # average ReadSharedReq miss latency 806system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency 807system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency 808system.cpu.l2cache.demand_avg_miss_latency::total 125029.591056 # average overall miss latency 809system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency 810system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency 811system.cpu.l2cache.overall_avg_miss_latency::total 125029.591056 # average overall miss latency |
| 812system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 813system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 814system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 815system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 816system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 817system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 818system.cpu.l2cache.fast_writes 0 # number of fast writes performed 819system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 836system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable 837system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable 838system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable 839system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable 840system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses 841system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses 842system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1285500 # number of UpgradeReq MSHR miss cycles 843system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1285500 # number of UpgradeReq MSHR miss cycles | 812system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 813system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 814system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 815system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 816system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 817system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 818system.cpu.l2cache.fast_writes 0 # number of fast writes performed 819system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 836system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable 837system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable 838system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable 839system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable 840system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses 841system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses 842system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1285500 # number of UpgradeReq MSHR miss cycles 843system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1285500 # number of UpgradeReq MSHR miss cycles |
| 844system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13670938000 # number of ReadExReq MSHR miss cycles 845system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13670938000 # number of ReadExReq MSHR miss cycles 846system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1978703000 # number of ReadCleanReq MSHR miss cycles 847system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1978703000 # number of ReadCleanReq MSHR miss cycles 848system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960659500 # number of ReadSharedReq MSHR miss cycles 849system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960659500 # number of ReadSharedReq MSHR miss cycles 850system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1978703000 # number of demand (read+write) MSHR miss cycles 851system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631597500 # number of demand (read+write) MSHR miss cycles 852system.cpu.l2cache.demand_mshr_miss_latency::total 46610300500 # number of demand (read+write) MSHR miss cycles 853system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1978703000 # number of overall MSHR miss cycles 854system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631597500 # number of overall MSHR miss cycles 855system.cpu.l2cache.overall_mshr_miss_latency::total 46610300500 # number of overall MSHR miss cycles 856system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1443571000 # number of ReadReq MSHR uncacheable cycles 857system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1443571000 # number of ReadReq MSHR uncacheable cycles | 844system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13671016000 # number of ReadExReq MSHR miss cycles 845system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13671016000 # number of ReadExReq MSHR miss cycles 846system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1979440000 # number of ReadCleanReq MSHR miss cycles 847system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1979440000 # number of ReadCleanReq MSHR miss cycles 848system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960462500 # number of ReadSharedReq MSHR miss cycles 849system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960462500 # number of ReadSharedReq MSHR miss cycles 850system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1979440000 # number of demand (read+write) MSHR miss cycles 851system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631478500 # number of demand (read+write) MSHR miss cycles 852system.cpu.l2cache.demand_mshr_miss_latency::total 46610918500 # number of demand (read+write) MSHR miss cycles 853system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1979440000 # number of overall MSHR miss cycles 854system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631478500 # number of overall MSHR miss cycles 855system.cpu.l2cache.overall_mshr_miss_latency::total 46610918500 # number of overall MSHR miss cycles 856system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442671000 # number of ReadReq MSHR uncacheable cycles 857system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442671000 # number of ReadReq MSHR uncacheable cycles |
| 858system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051831500 # number of WriteReq MSHR uncacheable cycles 859system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051831500 # number of WriteReq MSHR uncacheable cycles | 858system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051831500 # number of WriteReq MSHR uncacheable cycles 859system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051831500 # number of WriteReq MSHR uncacheable cycles |
| 860system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3495402500 # number of overall MSHR uncacheable cycles 861system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3495402500 # number of overall MSHR uncacheable cycles | 860system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3494502500 # number of overall MSHR uncacheable cycles 861system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494502500 # number of overall MSHR uncacheable cycles |
| 862system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses 863system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses 864system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383225 # mshr miss rate for ReadExReq accesses 865system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383225 # mshr miss rate for ReadExReq accesses 866system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for ReadCleanReq accesses 867system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011173 # mshr miss rate for ReadCleanReq accesses 868system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249378 # mshr miss rate for ReadSharedReq accesses 869system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249378 # mshr miss rate for ReadSharedReq accesses 870system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for demand accesses 871system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for demand accesses 872system.cpu.l2cache.demand_mshr_miss_rate::total 0.141825 # mshr miss rate for demand accesses 873system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for overall accesses 874system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for overall accesses 875system.cpu.l2cache.overall_mshr_miss_rate::total 0.141825 # mshr miss rate for overall accesses 876system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71416.666667 # average UpgradeReq mshr miss latency 877system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71416.666667 # average UpgradeReq mshr miss latency | 862system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses 863system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses 864system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383225 # mshr miss rate for ReadExReq accesses 865system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383225 # mshr miss rate for ReadExReq accesses 866system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for ReadCleanReq accesses 867system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011173 # mshr miss rate for ReadCleanReq accesses 868system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249378 # mshr miss rate for ReadSharedReq accesses 869system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249378 # mshr miss rate for ReadSharedReq accesses 870system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for demand accesses 871system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for demand accesses 872system.cpu.l2cache.demand_mshr_miss_rate::total 0.141825 # mshr miss rate for demand accesses 873system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for overall accesses 874system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for overall accesses 875system.cpu.l2cache.overall_mshr_miss_rate::total 0.141825 # mshr miss rate for overall accesses 876system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71416.666667 # average UpgradeReq mshr miss latency 877system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71416.666667 # average UpgradeReq mshr miss latency |
| 878system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.169443 # average ReadExReq mshr miss latency 879system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.169443 # average ReadExReq mshr miss latency 880system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121214.346974 # average ReadCleanReq mshr miss latency 881system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121214.346974 # average ReadCleanReq mshr miss latency 882system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113739.395019 # average ReadSharedReq mshr miss latency 883system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113739.395019 # average ReadSharedReq mshr miss latency 884system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency 885system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency 886system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency 887system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency 888system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency 890system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208187.337756 # average ReadReq mshr uncacheable latency 891system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208187.337756 # average ReadReq mshr uncacheable latency | 878system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.838058 # average ReadExReq mshr miss latency 879system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.838058 # average ReadExReq mshr miss latency 880system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121259.495222 # average ReadCleanReq mshr miss latency 881system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121259.495222 # average ReadCleanReq mshr miss latency 882system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113738.671305 # average ReadSharedReq mshr miss latency 883system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113738.671305 # average ReadSharedReq mshr miss latency 884system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency 885system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency 886system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency 887system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency 888system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency 890system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.542544 # average ReadReq mshr uncacheable latency 891system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.542544 # average ReadReq mshr uncacheable latency |
| 892system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213199.449293 # average WriteReq mshr uncacheable latency 893system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213199.449293 # average WriteReq mshr uncacheable latency | 892system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213199.449293 # average WriteReq mshr uncacheable latency 893system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213199.449293 # average WriteReq mshr uncacheable latency |
| 894system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211100.525426 # average overall mshr uncacheable latency 895system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211100.525426 # average overall mshr uncacheable latency | 894system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211046.171035 # average overall mshr uncacheable latency 895system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211046.171035 # average overall mshr uncacheable latency |
| 896system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 897system.cpu.toL2Bus.snoop_filter.tot_requests 5712890 # Total number of requests made to the snoop filter. 898system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856017 # Number of requests hitting in the snoop filter with a single holder of the requested data. 899system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 900system.cpu.toL2Bus.snoop_filter.tot_snoops 1248 # Total number of snoops made to the snoop filter. 901system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 902system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 903system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution --- 49 unchanged lines hidden (view full) --- 953system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 954system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 955system.disk2.dma_write_txs 1 # Number of DMA write transactions. 956system.iobus.trans_dist::ReadReq 7107 # Transaction distribution 957system.iobus.trans_dist::ReadResp 7107 # Transaction distribution 958system.iobus.trans_dist::WriteReq 51176 # Transaction distribution 959system.iobus.trans_dist::WriteResp 51176 # Transaction distribution 960system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5110 # Packet count per connected master and slave (bytes) | 896system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 897system.cpu.toL2Bus.snoop_filter.tot_requests 5712890 # Total number of requests made to the snoop filter. 898system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856017 # Number of requests hitting in the snoop filter with a single holder of the requested data. 899system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 900system.cpu.toL2Bus.snoop_filter.tot_snoops 1248 # Total number of snoops made to the snoop filter. 901system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 902system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 903system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution --- 49 unchanged lines hidden (view full) --- 953system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 954system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 955system.disk2.dma_write_txs 1 # Number of DMA write transactions. 956system.iobus.trans_dist::ReadReq 7107 # Transaction distribution 957system.iobus.trans_dist::ReadResp 7107 # Transaction distribution 958system.iobus.trans_dist::WriteReq 51176 # Transaction distribution 959system.iobus.trans_dist::WriteResp 51176 # Transaction distribution 960system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5110 # Packet count per connected master and slave (bytes) |
| 961system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) | 961system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) |
| 962system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 963system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 964system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 965system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 966system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 967system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) | 962system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 963system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 964system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 965system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 966system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 967system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) |
| 968system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) | |
| 969system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) | 968system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) |
| 970system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 971system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | |
| 972system.iobus.pkt_count_system.bridge.master::total 33116 # Packet count per connected master and slave (bytes) 973system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 974system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 975system.iobus.pkt_count::total 116566 # Packet count per connected master and slave (bytes) 976system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20440 # Cumulative packet size per connected master and slave (bytes) | 969system.iobus.pkt_count_system.bridge.master::total 33116 # Packet count per connected master and slave (bytes) 970system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 971system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 972system.iobus.pkt_count::total 116566 # Packet count per connected master and slave (bytes) 973system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20440 # Cumulative packet size per connected master and slave (bytes) |
| 977system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) | 974system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) |
| 978system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 979system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 980system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 981system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 982system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 983system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) | 975system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 976system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 977system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 978system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 979system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 980system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) |
| 984system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) | |
| 985system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) | 981system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) |
| 986system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 987system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | |
| 988system.iobus.pkt_size_system.bridge.master::total 44381 # Cumulative packet size per connected master and slave (bytes) 989system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 990system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 991system.iobus.pkt_size::total 2705989 # Cumulative packet size per connected master and slave (bytes) 992system.iobus.reqLayer0.occupancy 5423500 # Layer occupancy (ticks) 993system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 982system.iobus.pkt_size_system.bridge.master::total 44381 # Cumulative packet size per connected master and slave (bytes) 983system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 984system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 985system.iobus.pkt_size::total 2705989 # Cumulative packet size per connected master and slave (bytes) 986system.iobus.reqLayer0.occupancy 5423500 # Layer occupancy (ticks) 987system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 994system.iobus.reqLayer1.occupancy 386000 # Layer occupancy (ticks) | 988system.iobus.reqLayer1.occupancy 784500 # Layer occupancy (ticks) |
| 995system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 996system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 997system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 998system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 999system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1000system.iobus.reqLayer22.occupancy 186500 # Layer occupancy (ticks) 1001system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1002system.iobus.reqLayer23.occupancy 14813500 # Layer occupancy (ticks) 1003system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1004system.iobus.reqLayer24.occupancy 2308500 # Layer occupancy (ticks) 1005system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1006system.iobus.reqLayer25.occupancy 5938000 # Layer occupancy (ticks) 1007system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) | 989system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 990system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 991system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 992system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 993system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 994system.iobus.reqLayer22.occupancy 186500 # Layer occupancy (ticks) 995system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 996system.iobus.reqLayer23.occupancy 14813500 # Layer occupancy (ticks) 997system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 998system.iobus.reqLayer24.occupancy 2308500 # Layer occupancy (ticks) 999system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1000system.iobus.reqLayer25.occupancy 5938000 # Layer occupancy (ticks) 1001system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) |
| 1008system.iobus.reqLayer26.occupancy 224500 # Layer occupancy (ticks) | 1002system.iobus.reqLayer26.occupancy 98500 # Layer occupancy (ticks) |
| 1009system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1003system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1010system.iobus.reqLayer27.occupancy 98500 # Layer occupancy (ticks) | 1004system.iobus.reqLayer27.occupancy 215092991 # Layer occupancy (ticks) |
| 1011system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) | 1005system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) |
| 1012system.iobus.reqLayer28.occupancy 142500 # Layer occupancy (ticks) 1013system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1014system.iobus.reqLayer29.occupancy 215092991 # Layer occupancy (ticks) 1015system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1016system.iobus.reqLayer30.occupancy 31500 # Layer occupancy (ticks) 1017system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | |
| 1018system.iobus.respLayer0.occupancy 23492000 # Layer occupancy (ticks) 1019system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1020system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1021system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1022system.iocache.tags.replacements 41685 # number of replacements 1023system.iocache.tags.tagsinuse 1.290814 # Cycle average of tags in use 1024system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1025system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. --- 130 unchanged lines hidden (view full) --- 1156system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1157system.membus.snoop_fanout::total 843925 # Request fanout histogram 1158system.membus.reqLayer0.occupancy 29573500 # Layer occupancy (ticks) 1159system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1160system.membus.reqLayer1.occupancy 1319381154 # Layer occupancy (ticks) 1161system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1162system.membus.reqLayer2.occupancy 22500 # Layer occupancy (ticks) 1163system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1006system.iobus.respLayer0.occupancy 23492000 # Layer occupancy (ticks) 1007system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1008system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1009system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1010system.iocache.tags.replacements 41685 # number of replacements 1011system.iocache.tags.tagsinuse 1.290814 # Cycle average of tags in use 1012system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1013system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. --- 130 unchanged lines hidden (view full) --- 1144system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1145system.membus.snoop_fanout::total 843925 # Request fanout histogram 1146system.membus.reqLayer0.occupancy 29573500 # Layer occupancy (ticks) 1147system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1148system.membus.reqLayer1.occupancy 1319381154 # Layer occupancy (ticks) 1149system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1150system.membus.reqLayer2.occupancy 22500 # Layer occupancy (ticks) 1151system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1164system.membus.respLayer1.occupancy 2160247074 # Layer occupancy (ticks) | 1152system.membus.respLayer1.occupancy 2160244574 # Layer occupancy (ticks) |
| 1165system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1166system.membus.respLayer2.occupancy 69858432 # Layer occupancy (ticks) 1167system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1168system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1169system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1170system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1171system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1172system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 28 unchanged lines hidden --- | 1153system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1154system.membus.respLayer2.occupancy 69858432 # Layer occupancy (ticks) 1155system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1156system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1157system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1158system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1159system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1160system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 28 unchanged lines hidden --- |