| stats.txt (10892:bd37e25fb3b7) | stats.txt (11103:38f6188421e0) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.886196 # Number of seconds simulated 4sim_ticks 1886195993000 # Number of ticks simulated 5final_tick 1886195993000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.887168 # Number of seconds simulated 4sim_ticks 1887168480000 # Number of ticks simulated 5final_tick 1887168480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 256659 # Simulator instruction rate (inst/s) 8host_op_rate 256659 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8626071053 # Simulator tick rate (ticks/s) 10host_mem_usage 374008 # Number of bytes of host memory used 11host_seconds 218.66 # Real time elapsed on the host 12sim_insts 56121694 # Number of instructions simulated 13sim_ops 56121694 # Number of ops (including micro ops) simulated | 7host_inst_rate 181674 # Simulator instruction rate (inst/s) 8host_op_rate 181674 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6108559174 # Simulator tick rate (ticks/s) 10host_mem_usage 367844 # Number of bytes of host memory used 11host_seconds 308.94 # Real time elapsed on the host 12sim_insts 56125948 # Number of instructions simulated 13sim_ops 56125948 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 1049728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24850240 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 1049920 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24850048 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25900928 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25900928 # Number of bytes read from this memory |
| 20system.physmem.bytes_inst_read::cpu.inst 1049728 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1049728 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7553600 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7553600 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 16402 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388285 # Number of read requests responded to by this memory | 20system.physmem.bytes_inst_read::cpu.inst 1049920 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1049920 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7553472 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7553472 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 16405 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388282 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 404702 # Number of read requests responded to by this memory | 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 404702 # Number of read requests responded to by this memory |
| 28system.physmem.num_writes::writebacks 118025 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 118025 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 556532 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13174792 # Total read bandwidth from this memory (bytes/s) | 28system.physmem.num_writes::writebacks 118023 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 118023 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 556347 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13167901 # Total read bandwidth from this memory (bytes/s) |
| 32system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) | 32system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) |
| 33system.physmem.bw_read::total 13731833 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 556532 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 556532 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4004674 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4004674 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4004674 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 556532 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13174792 # Total bandwidth to/from this memory (bytes/s) | 33system.physmem.bw_read::total 13724757 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 556347 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 556347 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4002542 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4002542 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4002542 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 556347 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13167901 # Total bandwidth to/from this memory (bytes/s) |
| 41system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) | 41system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) |
| 42system.physmem.bw_total::total 17736507 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.bw_total::total 17727299 # Total bandwidth to/from this memory (bytes/s) |
| 43system.physmem.readReqs 404702 # Number of read requests accepted | 43system.physmem.readReqs 404702 # Number of read requests accepted |
| 44system.physmem.writeReqs 118025 # Number of write requests accepted | 44system.physmem.writeReqs 118023 # Number of write requests accepted |
| 45system.physmem.readBursts 404702 # Number of DRAM read bursts, including those serviced by the write queue | 45system.physmem.readBursts 404702 # Number of DRAM read bursts, including those serviced by the write queue |
| 46system.physmem.writeBursts 118025 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25894272 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7551808 # Total number of bytes written to DRAM | 46system.physmem.writeBursts 118023 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25893824 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7551936 # Total number of bytes written to DRAM |
| 50system.physmem.bytesReadSys 25900928 # Total read bytes from the system interface side | 50system.physmem.bytesReadSys 25900928 # Total read bytes from the system interface side |
| 51system.physmem.bytesWrittenSys 7553600 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue | 51system.physmem.bytesWrittenSys 7553472 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue |
| 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 54system.physmem.neitherReadNorWriteReqs 41706 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25487 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25728 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25822 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25769 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25085 # Per bank write bursts 60system.physmem.perBankRdBursts::5 25016 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24650 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24524 # Per bank write bursts | 54system.physmem.neitherReadNorWriteReqs 41707 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25482 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25721 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25818 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25768 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25084 # Per bank write bursts 60system.physmem.perBankRdBursts::5 25019 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24651 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24525 # Per bank write bursts |
| 63system.physmem.perBankRdBursts::8 25293 # Per bank write bursts | 63system.physmem.perBankRdBursts::8 25293 # Per bank write bursts |
| 64system.physmem.perBankRdBursts::9 25190 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25398 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24986 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24522 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25563 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25828 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25737 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7820 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7688 # Per bank write bursts 73system.physmem.perBankWrBursts::2 8067 # Per bank write bursts | 64system.physmem.perBankRdBursts::9 25189 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25397 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24988 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24521 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25565 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25830 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25740 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7815 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7682 # Per bank write bursts 73system.physmem.perBankWrBursts::2 8062 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::3 7737 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7196 # Per bank write bursts | 74system.physmem.perBankWrBursts::3 7737 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7196 # Per bank write bursts |
| 76system.physmem.perBankWrBursts::5 7011 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6646 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6392 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7401 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6804 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7278 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6972 # Per bank write bursts | 76system.physmem.perBankWrBursts::5 7012 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6647 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6398 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7404 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6806 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7277 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6969 # Per bank write bursts |
| 83system.physmem.perBankWrBursts::12 7052 # Per bank write bursts | 83system.physmem.perBankWrBursts::12 7052 # Per bank write bursts |
| 84system.physmem.perBankWrBursts::13 8008 # Per bank write bursts 85system.physmem.perBankWrBursts::14 7983 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7942 # Per bank write bursts | 84system.physmem.perBankWrBursts::13 8011 # Per bank write bursts 85system.physmem.perBankWrBursts::14 7982 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7949 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 88system.physmem.numWrRetry 17 # Number of times write queue was full causing retry 89system.physmem.totGap 1886187226500 # Total gap between requests | 88system.physmem.numWrRetry 29 # Number of times write queue was full causing retry 89system.physmem.totGap 1887159671500 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 404702 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 404702 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 118025 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 402327 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 118023 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 402323 # What read queue length does an incoming req see |
| 105system.physmem.rdQLenPdf::1 2193 # What read queue length does an incoming req see | 105system.physmem.rdQLenPdf::1 2193 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see | 106system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see |
| 107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 1481 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1905 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 6090 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 6347 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 6056 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 6388 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 7084 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 7338 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 9716 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 8808 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 7466 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8358 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 6772 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 6976 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 5877 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5494 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 133 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 111 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 119 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 117 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 91 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 177 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 111 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 96 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 193 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 101 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 112 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 133 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 82 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 56 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 63594 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 525.931377 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 320.890659 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 414.200803 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 14460 22.74% 22.74% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10997 17.29% 40.03% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4933 7.76% 47.79% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3625 5.70% 53.49% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2479 3.90% 57.39% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1827 2.87% 60.26% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1418 2.23% 62.49% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1367 2.15% 64.64% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 22488 35.36% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 63594 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5295 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 76.408121 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2902.928186 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5292 99.94% 99.94% # Reads before turning the bus around for writes | 151system.physmem.wrQLenPdf::15 1508 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1846 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 6025 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 5962 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 6254 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 7072 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 7254 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 9744 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 8775 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 7502 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8222 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 6817 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6604 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 7036 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 5493 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5524 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 194 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 125 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 181 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 183 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 169 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 185 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 184 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 185 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 145 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 139 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 143 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 131 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 120 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 158 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 87 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 94 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 63563 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 526.182842 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 320.768050 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 414.563237 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 14483 22.79% 22.79% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10991 17.29% 40.08% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4893 7.70% 47.77% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3583 5.64% 53.41% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2419 3.81% 57.22% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1815 2.86% 60.07% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1455 2.29% 62.36% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1407 2.21% 64.58% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 22517 35.42% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 63563 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5279 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 76.639515 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2907.321691 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5276 99.94% 99.94% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::total 5295 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5295 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 22.284608 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 18.797942 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 22.673735 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-23 4676 88.31% 88.31% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::24-31 227 4.29% 92.60% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::32-39 77 1.45% 94.05% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-47 16 0.30% 94.35% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::48-55 14 0.26% 94.62% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::56-63 6 0.11% 94.73% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::64-71 7 0.13% 94.86% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::72-79 9 0.17% 95.03% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::80-87 7 0.13% 95.17% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::88-95 34 0.64% 95.81% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::96-103 171 3.23% 99.04% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::104-111 10 0.19% 99.23% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::120-127 1 0.02% 99.26% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::128-135 5 0.09% 99.36% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::136-143 3 0.06% 99.41% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::152-159 1 0.02% 99.43% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::168-175 2 0.04% 99.47% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::176-183 4 0.08% 99.55% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::184-191 4 0.08% 99.62% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::192-199 8 0.15% 99.77% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::216-223 2 0.04% 99.83% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::total 5295 # Writes before turning the bus around for reads 253system.physmem.totQLat 2213284250 # Total ticks spent queuing 254system.physmem.totMemAccLat 9799496750 # Total ticks spent from burst creation until serviced by the DRAM 255system.physmem.totBusLat 2022990000 # Total ticks spent in databus transfers 256system.physmem.avgQLat 5470.33 # Average queueing delay per DRAM burst | 221system.physmem.rdPerTurnAround::total 5279 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5279 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 22.352529 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 18.833418 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 22.552708 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-23 4665 88.37% 88.37% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::24-31 223 4.22% 92.59% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::32-39 69 1.31% 93.90% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-47 13 0.25% 94.15% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::48-55 7 0.13% 94.28% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::56-63 8 0.15% 94.43% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::64-71 10 0.19% 94.62% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::72-79 11 0.21% 94.83% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::80-87 9 0.17% 95.00% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::88-95 33 0.63% 95.62% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::96-103 187 3.54% 99.17% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::104-111 5 0.09% 99.26% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::112-119 2 0.04% 99.30% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::120-127 2 0.04% 99.34% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::128-135 7 0.13% 99.47% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::152-159 1 0.02% 99.51% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::160-167 3 0.06% 99.56% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::168-175 3 0.06% 99.62% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::176-183 6 0.11% 99.73% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::216-223 1 0.02% 99.79% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::224-231 9 0.17% 99.96% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::total 5279 # Writes before turning the bus around for reads 252system.physmem.totQLat 2194493000 # Total ticks spent queuing 253system.physmem.totMemAccLat 9780574250 # Total ticks spent from burst creation until serviced by the DRAM 254system.physmem.totBusLat 2022955000 # Total ticks spent in databus transfers 255system.physmem.avgQLat 5423.98 # Average queueing delay per DRAM burst |
| 257system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 256system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 258system.physmem.avgMemAccLat 24220.33 # Average memory access latency per DRAM burst 259system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s | 257system.physmem.avgMemAccLat 24173.98 # Average memory access latency per DRAM burst 258system.physmem.avgRdBW 13.72 # Average DRAM read bandwidth in MiByte/s |
| 260system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s | 259system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s |
| 261system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s | 260system.physmem.avgRdBWSys 13.72 # Average system read bandwidth in MiByte/s |
| 262system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s 263system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 264system.physmem.busUtil 0.14 # Data bus utilization in percentage 265system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 266system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 267system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 261system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s 262system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 263system.physmem.busUtil 0.14 # Data bus utilization in percentage 264system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 265system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 266system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 268system.physmem.avgWrQLen 24.19 # Average write queue length when enqueuing 269system.physmem.readRowHits 363516 # Number of row buffer hits during reads 270system.physmem.writeRowHits 95485 # Number of row buffer hits during writes 271system.physmem.readRowHitRate 89.85 # Row buffer hit rate for reads 272system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes 273system.physmem.avgGap 3608360.06 # Average gap between requests | 267system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing 268system.physmem.readRowHits 363582 # Number of row buffer hits during reads 269system.physmem.writeRowHits 95445 # Number of row buffer hits during writes 270system.physmem.readRowHitRate 89.86 # Row buffer hit rate for reads 271system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes 272system.physmem.avgGap 3610234.20 # Average gap between requests |
| 274system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined | 273system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined |
| 275system.physmem_0.actEnergy 233845920 # Energy for activate commands per rank (pJ) 276system.physmem_0.preEnergy 127594500 # Energy for precharge commands per rank (pJ) 277system.physmem_0.readEnergy 1576231800 # Energy for read commands per rank (pJ) 278system.physmem_0.writeEnergy 379449360 # Energy for write commands per rank (pJ) 279system.physmem_0.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ) 280system.physmem_0.actBackEnergy 60326866845 # Energy for active background per rank (pJ) 281system.physmem_0.preBackEnergy 1078799265750 # Energy for precharge background per rank (pJ) 282system.physmem_0.totalEnergy 1264640388495 # Total energy per rank (pJ) 283system.physmem_0.averagePower 670.471373 # Core power per rank (mW) 284system.physmem_0.memoryStateTime::IDLE 1794467110750 # Time in different power states 285system.physmem_0.memoryStateTime::REF 62984220000 # Time in different power states | 274system.physmem_0.actEnergy 233596440 # Energy for activate commands per rank (pJ) 275system.physmem_0.preEnergy 127458375 # Energy for precharge commands per rank (pJ) 276system.physmem_0.readEnergy 1576130400 # Energy for read commands per rank (pJ) 277system.physmem_0.writeEnergy 379397520 # Energy for write commands per rank (pJ) 278system.physmem_0.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ) 279system.physmem_0.actBackEnergy 60352481790 # Energy for active background per rank (pJ) 280system.physmem_0.preBackEnergy 1079356093500 # Energy for precharge background per rank (pJ) 281system.physmem_0.totalEnergy 1265285353785 # Total energy per rank (pJ) 282system.physmem_0.averagePower 670.470116 # Core power per rank (mW) 283system.physmem_0.memoryStateTime::IDLE 1795392967750 # Time in different power states 284system.physmem_0.memoryStateTime::REF 63016460000 # Time in different power states |
| 286system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 285system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 287system.physmem_0.memoryStateTime::ACT 28744633000 # Time in different power states | 286system.physmem_0.memoryStateTime::ACT 28752031000 # Time in different power states |
| 288system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 287system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 289system.physmem_1.actEnergy 246924720 # Energy for activate commands per rank (pJ) 290system.physmem_1.preEnergy 134730750 # Energy for precharge commands per rank (pJ) 291system.physmem_1.readEnergy 1579632600 # Energy for read commands per rank (pJ) 292system.physmem_1.writeEnergy 385171200 # Energy for write commands per rank (pJ) 293system.physmem_1.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ) 294system.physmem_1.actBackEnergy 61494025635 # Energy for active background per rank (pJ) 295system.physmem_1.preBackEnergy 1077775442250 # Energy for precharge background per rank (pJ) 296system.physmem_1.totalEnergy 1264813061475 # Total energy per rank (pJ) 297system.physmem_1.averagePower 670.562919 # Core power per rank (mW) 298system.physmem_1.memoryStateTime::IDLE 1792762379750 # Time in different power states 299system.physmem_1.memoryStateTime::REF 62984220000 # Time in different power states | 288system.physmem_1.actEnergy 246939840 # Energy for activate commands per rank (pJ) 289system.physmem_1.preEnergy 134739000 # Energy for precharge commands per rank (pJ) 290system.physmem_1.readEnergy 1579679400 # Energy for read commands per rank (pJ) 291system.physmem_1.writeEnergy 385236000 # Energy for write commands per rank (pJ) 292system.physmem_1.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ) 293system.physmem_1.actBackEnergy 61300664820 # Energy for active background per rank (pJ) 294system.physmem_1.preBackEnergy 1078524362250 # Energy for precharge background per rank (pJ) 295system.physmem_1.totalEnergy 1265431817070 # Total energy per rank (pJ) 296system.physmem_1.averagePower 670.547722 # Core power per rank (mW) 297system.physmem_1.memoryStateTime::IDLE 1794008459000 # Time in different power states 298system.physmem_1.memoryStateTime::REF 63016460000 # Time in different power states |
| 300system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 299system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 301system.physmem_1.memoryStateTime::ACT 30449364000 # Time in different power states | 300system.physmem_1.memoryStateTime::ACT 30136553500 # Time in different power states |
| 302system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 301system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 303system.cpu.branchPred.lookups 15004879 # Number of BP lookups 304system.cpu.branchPred.condPredicted 13013312 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 375549 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 10036322 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 5207234 # Number of BTB hits | 302system.cpu.branchPred.lookups 14997890 # Number of BP lookups 303system.cpu.branchPred.condPredicted 13009268 # Number of conditional branches predicted 304system.cpu.branchPred.condIncorrect 370594 # Number of conditional branches incorrect 305system.cpu.branchPred.BTBLookups 9393435 # Number of BTB lookups 306system.cpu.branchPred.BTBHits 5198350 # Number of BTB hits |
| 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 307system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 309system.cpu.branchPred.BTBHitPct 51.883887 # BTB Hit Percentage 310system.cpu.branchPred.usedRAS 808293 # Number of times the RAS was used to get a target. 311system.cpu.branchPred.RASInCorrect 31321 # Number of incorrect RAS predictions. | 308system.cpu.branchPred.BTBHitPct 55.340246 # BTB Hit Percentage 309system.cpu.branchPred.usedRAS 807960 # Number of times the RAS was used to get a target. 310system.cpu.branchPred.RASInCorrect 32049 # Number of incorrect RAS predictions. |
| 312system.cpu_clk_domain.clock 500 # Clock period in ticks 313system.cpu.dtb.fetch_hits 0 # ITB hits 314system.cpu.dtb.fetch_misses 0 # ITB misses 315system.cpu.dtb.fetch_acv 0 # ITB acv 316system.cpu.dtb.fetch_accesses 0 # ITB accesses | 311system.cpu_clk_domain.clock 500 # Clock period in ticks 312system.cpu.dtb.fetch_hits 0 # ITB hits 313system.cpu.dtb.fetch_misses 0 # ITB misses 314system.cpu.dtb.fetch_acv 0 # ITB acv 315system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 317system.cpu.dtb.read_hits 9242647 # DTB read hits 318system.cpu.dtb.read_misses 17811 # DTB read misses | 316system.cpu.dtb.read_hits 9241004 # DTB read hits 317system.cpu.dtb.read_misses 17472 # DTB read misses |
| 319system.cpu.dtb.read_acv 211 # DTB read access violations | 318system.cpu.dtb.read_acv 211 # DTB read access violations |
| 320system.cpu.dtb.read_accesses 766734 # DTB read accesses 321system.cpu.dtb.write_hits 6385782 # DTB write hits 322system.cpu.dtb.write_misses 2309 # DTB write misses | 319system.cpu.dtb.read_accesses 766036 # DTB read accesses 320system.cpu.dtb.write_hits 6386411 # DTB write hits 321system.cpu.dtb.write_misses 2301 # DTB write misses |
| 323system.cpu.dtb.write_acv 160 # DTB write access violations | 322system.cpu.dtb.write_acv 160 # DTB write access violations |
| 324system.cpu.dtb.write_accesses 298407 # DTB write accesses 325system.cpu.dtb.data_hits 15628429 # DTB hits 326system.cpu.dtb.data_misses 20120 # DTB misses | 323system.cpu.dtb.write_accesses 298419 # DTB write accesses 324system.cpu.dtb.data_hits 15627415 # DTB hits 325system.cpu.dtb.data_misses 19773 # DTB misses |
| 327system.cpu.dtb.data_acv 371 # DTB access violations | 326system.cpu.dtb.data_acv 371 # DTB access violations |
| 328system.cpu.dtb.data_accesses 1065141 # DTB accesses 329system.cpu.itb.fetch_hits 4016387 # ITB hits 330system.cpu.itb.fetch_misses 6834 # ITB misses 331system.cpu.itb.fetch_acv 689 # ITB acv 332system.cpu.itb.fetch_accesses 4023221 # ITB accesses | 327system.cpu.dtb.data_accesses 1064455 # DTB accesses 328system.cpu.itb.fetch_hits 4013195 # ITB hits 329system.cpu.itb.fetch_misses 6857 # ITB misses 330system.cpu.itb.fetch_acv 677 # ITB acv 331system.cpu.itb.fetch_accesses 4020052 # ITB accesses |
| 333system.cpu.itb.read_hits 0 # DTB read hits 334system.cpu.itb.read_misses 0 # DTB read misses 335system.cpu.itb.read_acv 0 # DTB read access violations 336system.cpu.itb.read_accesses 0 # DTB read accesses 337system.cpu.itb.write_hits 0 # DTB write hits 338system.cpu.itb.write_misses 0 # DTB write misses 339system.cpu.itb.write_acv 0 # DTB write access violations 340system.cpu.itb.write_accesses 0 # DTB write accesses 341system.cpu.itb.data_hits 0 # DTB hits 342system.cpu.itb.data_misses 0 # DTB misses 343system.cpu.itb.data_acv 0 # DTB access violations 344system.cpu.itb.data_accesses 0 # DTB accesses | 332system.cpu.itb.read_hits 0 # DTB read hits 333system.cpu.itb.read_misses 0 # DTB read misses 334system.cpu.itb.read_acv 0 # DTB read access violations 335system.cpu.itb.read_accesses 0 # DTB read accesses 336system.cpu.itb.write_hits 0 # DTB write hits 337system.cpu.itb.write_misses 0 # DTB write misses 338system.cpu.itb.write_acv 0 # DTB write access violations 339system.cpu.itb.write_accesses 0 # DTB write accesses 340system.cpu.itb.data_hits 0 # DTB hits 341system.cpu.itb.data_misses 0 # DTB misses 342system.cpu.itb.data_acv 0 # DTB access violations 343system.cpu.itb.data_accesses 0 # DTB accesses |
| 345system.cpu.numCycles 180216793 # number of cpu cycles simulated | 344system.cpu.numCycles 182043546 # number of cpu cycles simulated |
| 346system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 347system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 345system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 346system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 348system.cpu.committedInsts 56121694 # Number of instructions committed 349system.cpu.committedOps 56121694 # Number of ops (including micro ops) committed 350system.cpu.discardedOps 2519198 # Number of ops (including micro ops) which were discarded before commit 351system.cpu.numFetchSuspends 5577 # Number of times Execute suspended instruction fetching 352system.cpu.quiesceCycles 3592175193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 353system.cpu.cpi 3.211179 # CPI: cycles per instruction 354system.cpu.ipc 0.311412 # IPC: instructions per cycle | 347system.cpu.committedInsts 56125948 # Number of instructions committed 348system.cpu.committedOps 56125948 # Number of ops (including micro ops) committed 349system.cpu.discardedOps 2502558 # Number of ops (including micro ops) which were discarded before commit 350system.cpu.numFetchSuspends 5565 # Number of times Execute suspended instruction fetching 351system.cpu.quiesceCycles 3594204473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 352system.cpu.cpi 3.243483 # CPI: cycles per instruction 353system.cpu.ipc 0.308311 # IPC: instructions per cycle |
| 355system.cpu.kern.inst.arm 0 # number of arm instructions executed | 354system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 356system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed 357system.cpu.kern.inst.hwrei 211471 # number of hwrei instructions executed 358system.cpu.kern.ipl_count::0 74788 40.94% 40.94% # number of times we switched to this ipl 359system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl 360system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl 361system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl 362system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl 363system.cpu.kern.ipl_good::0 73421 49.32% 49.32% # number of times we switched to this ipl from a different ipl 364system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl 365system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl 366system.cpu.kern.ipl_good::31 73422 49.32% 100.00% # number of times we switched to this ipl from a different ipl 367system.cpu.kern.ipl_good::total 148877 # number of times we switched to this ipl from a different ipl 368system.cpu.kern.ipl_ticks::0 1833775262000 97.22% 97.22% # number of cycles we spent at this ipl 369system.cpu.kern.ipl_ticks::21 81341000 0.00% 97.23% # number of cycles we spent at this ipl 370system.cpu.kern.ipl_ticks::22 679703500 0.04% 97.26% # number of cycles we spent at this ipl 371system.cpu.kern.ipl_ticks::31 51658703500 2.74% 100.00% # number of cycles we spent at this ipl 372system.cpu.kern.ipl_ticks::total 1886195010000 # number of cycles we spent at this ipl 373system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl | 355system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed 356system.cpu.kern.inst.hwrei 211461 # number of hwrei instructions executed 357system.cpu.kern.ipl_count::0 74782 40.94% 40.94% # number of times we switched to this ipl 358system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl 359system.cpu.kern.ipl_count::22 1902 1.04% 42.05% # number of times we switched to this ipl 360system.cpu.kern.ipl_count::31 105860 57.95% 100.00% # number of times we switched to this ipl 361system.cpu.kern.ipl_count::total 182675 # number of times we switched to this ipl 362system.cpu.kern.ipl_good::0 73415 49.32% 49.32% # number of times we switched to this ipl from a different ipl 363system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 364system.cpu.kern.ipl_good::22 1902 1.28% 50.68% # number of times we switched to this ipl from a different ipl 365system.cpu.kern.ipl_good::31 73415 49.32% 100.00% # number of times we switched to this ipl from a different ipl 366system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl 367system.cpu.kern.ipl_ticks::0 1834747397000 97.22% 97.22% # number of cycles we spent at this ipl 368system.cpu.kern.ipl_ticks::21 80828500 0.00% 97.23% # number of cycles we spent at this ipl 369system.cpu.kern.ipl_ticks::22 680298500 0.04% 97.26% # number of cycles we spent at this ipl 370system.cpu.kern.ipl_ticks::31 51658959000 2.74% 100.00% # number of cycles we spent at this ipl 371system.cpu.kern.ipl_ticks::total 1887167483000 # number of cycles we spent at this ipl 372system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl |
| 374system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 375system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 373system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 374system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 376system.cpu.kern.ipl_used::31 0.693550 # fraction of swpipl calls that actually changed the ipl 377system.cpu.kern.ipl_used::total 0.814934 # fraction of swpipl calls that actually changed the ipl | 375system.cpu.kern.ipl_used::31 0.693510 # fraction of swpipl calls that actually changed the ipl 376system.cpu.kern.ipl_used::total 0.814906 # fraction of swpipl calls that actually changed the ipl |
| 378system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 379system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 380system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 381system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 382system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 383system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 384system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 385system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 408system.cpu.kern.syscall::total 326 # number of syscalls executed 409system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 410system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 411system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 412system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 413system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed 414system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 415system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 377system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 378system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 379system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 380system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 381system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 382system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 383system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 384system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 407system.cpu.kern.syscall::total 326 # number of syscalls executed 408system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 409system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 410system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 411system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 412system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed 413system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 414system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 416system.cpu.kern.callpal::swpipl 175525 91.23% 93.43% # number of callpals executed 417system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed | 415system.cpu.kern.callpal::swpipl 175514 91.22% 93.43% # number of callpals executed 416system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed |
| 418system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 419system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 420system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 421system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 422system.cpu.kern.callpal::rti 5127 2.66% 99.64% # number of callpals executed 423system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 424system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 417system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 418system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 419system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 420system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 421system.cpu.kern.callpal::rti 5127 2.66% 99.64% # number of callpals executed 422system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 423system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 425system.cpu.kern.callpal::total 192408 # number of callpals executed | 424system.cpu.kern.callpal::total 192398 # number of callpals executed |
| 426system.cpu.kern.mode_switch::kernel 5868 # number of protection mode switches 427system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 428system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 429system.cpu.kern.mode_good::kernel 1907 430system.cpu.kern.mode_good::user 1739 431system.cpu.kern.mode_good::idle 168 432system.cpu.kern.mode_switch_good::kernel 0.324983 # fraction of useful protection mode switches 433system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 434system.cpu.kern.mode_switch_good::idle 0.080114 # fraction of useful protection mode switches 435system.cpu.kern.mode_switch_good::total 0.393034 # fraction of useful protection mode switches | 425system.cpu.kern.mode_switch::kernel 5868 # number of protection mode switches 426system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 427system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 428system.cpu.kern.mode_good::kernel 1907 429system.cpu.kern.mode_good::user 1739 430system.cpu.kern.mode_good::idle 168 431system.cpu.kern.mode_switch_good::kernel 0.324983 # fraction of useful protection mode switches 432system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 433system.cpu.kern.mode_switch_good::idle 0.080114 # fraction of useful protection mode switches 434system.cpu.kern.mode_switch_good::total 0.393034 # fraction of useful protection mode switches |
| 436system.cpu.kern.mode_ticks::kernel 36513483500 1.94% 1.94% # number of ticks spent at the given mode 437system.cpu.kern.mode_ticks::user 4123557000 0.22% 2.15% # number of ticks spent at the given mode 438system.cpu.kern.mode_ticks::idle 1845557959500 97.85% 100.00% # number of ticks spent at the given mode | 435system.cpu.kern.mode_ticks::kernel 36501486500 1.93% 1.93% # number of ticks spent at the given mode 436system.cpu.kern.mode_ticks::user 4115911000 0.22% 2.15% # number of ticks spent at the given mode 437system.cpu.kern.mode_ticks::idle 1846550075500 97.85% 100.00% # number of ticks spent at the given mode |
| 439system.cpu.kern.swap_context 4173 # number of times the context was actually changed | 438system.cpu.kern.swap_context 4173 # number of times the context was actually changed |
| 440system.cpu.tickCycles 84408299 # Number of cycles that the object actually ticked 441system.cpu.idleCycles 95808494 # Total number of cycles that the object has spent stopped 442system.cpu.dcache.tags.replacements 1395428 # number of replacements 443system.cpu.dcache.tags.tagsinuse 511.981685 # Cycle average of tags in use 444system.cpu.dcache.tags.total_refs 13773051 # Total number of references to valid blocks. 445system.cpu.dcache.tags.sampled_refs 1395940 # Sample count of references to valid blocks. 446system.cpu.dcache.tags.avg_refs 9.866506 # Average number of references to valid blocks. | 439system.cpu.tickCycles 86269078 # Number of cycles that the object actually ticked 440system.cpu.idleCycles 95774468 # Total number of cycles that the object has spent stopped 441system.cpu.dcache.tags.replacements 1395484 # number of replacements 442system.cpu.dcache.tags.tagsinuse 511.981722 # Cycle average of tags in use 443system.cpu.dcache.tags.total_refs 13771544 # Total number of references to valid blocks. 444system.cpu.dcache.tags.sampled_refs 1395996 # Sample count of references to valid blocks. 445system.cpu.dcache.tags.avg_refs 9.865031 # Average number of references to valid blocks. |
| 447system.cpu.dcache.tags.warmup_cycle 90850500 # Cycle when the warmup percentage was hit. | 446system.cpu.dcache.tags.warmup_cycle 90850500 # Cycle when the warmup percentage was hit. |
| 448system.cpu.dcache.tags.occ_blocks::cpu.data 511.981685 # Average occupied blocks per requestor | 447system.cpu.dcache.tags.occ_blocks::cpu.data 511.981722 # Average occupied blocks per requestor |
| 449system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy 450system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy 451system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 452system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id | 448system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy 449system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy 450system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 451system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id |
| 453system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id 454system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id | 452system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id 453system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id |
| 455system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 454system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 456system.cpu.dcache.tags.tag_accesses 63660654 # Number of tag accesses 457system.cpu.dcache.tags.data_accesses 63660654 # Number of data accesses 458system.cpu.dcache.ReadReq_hits::cpu.data 7815445 # number of ReadReq hits 459system.cpu.dcache.ReadReq_hits::total 7815445 # number of ReadReq hits 460system.cpu.dcache.WriteReq_hits::cpu.data 5575784 # number of WriteReq hits 461system.cpu.dcache.WriteReq_hits::total 5575784 # number of WriteReq hits 462system.cpu.dcache.LoadLockedReq_hits::cpu.data 182800 # number of LoadLockedReq hits 463system.cpu.dcache.LoadLockedReq_hits::total 182800 # number of LoadLockedReq hits 464system.cpu.dcache.StoreCondReq_hits::cpu.data 198989 # number of StoreCondReq hits 465system.cpu.dcache.StoreCondReq_hits::total 198989 # number of StoreCondReq hits 466system.cpu.dcache.demand_hits::cpu.data 13391229 # number of demand (read+write) hits 467system.cpu.dcache.demand_hits::total 13391229 # number of demand (read+write) hits 468system.cpu.dcache.overall_hits::cpu.data 13391229 # number of overall hits 469system.cpu.dcache.overall_hits::total 13391229 # number of overall hits 470system.cpu.dcache.ReadReq_misses::cpu.data 1201797 # number of ReadReq misses 471system.cpu.dcache.ReadReq_misses::total 1201797 # number of ReadReq misses 472system.cpu.dcache.WriteReq_misses::cpu.data 574153 # number of WriteReq misses 473system.cpu.dcache.WriteReq_misses::total 574153 # number of WriteReq misses 474system.cpu.dcache.LoadLockedReq_misses::cpu.data 17210 # number of LoadLockedReq misses 475system.cpu.dcache.LoadLockedReq_misses::total 17210 # number of LoadLockedReq misses 476system.cpu.dcache.demand_misses::cpu.data 1775950 # number of demand (read+write) misses 477system.cpu.dcache.demand_misses::total 1775950 # number of demand (read+write) misses 478system.cpu.dcache.overall_misses::cpu.data 1775950 # number of overall misses 479system.cpu.dcache.overall_misses::total 1775950 # number of overall misses 480system.cpu.dcache.ReadReq_miss_latency::cpu.data 32866409500 # number of ReadReq miss cycles 481system.cpu.dcache.ReadReq_miss_latency::total 32866409500 # number of ReadReq miss cycles 482system.cpu.dcache.WriteReq_miss_latency::cpu.data 22318082000 # number of WriteReq miss cycles 483system.cpu.dcache.WriteReq_miss_latency::total 22318082000 # number of WriteReq miss cycles 484system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230873000 # number of LoadLockedReq miss cycles 485system.cpu.dcache.LoadLockedReq_miss_latency::total 230873000 # number of LoadLockedReq miss cycles 486system.cpu.dcache.demand_miss_latency::cpu.data 55184491500 # number of demand (read+write) miss cycles 487system.cpu.dcache.demand_miss_latency::total 55184491500 # number of demand (read+write) miss cycles 488system.cpu.dcache.overall_miss_latency::cpu.data 55184491500 # number of overall miss cycles 489system.cpu.dcache.overall_miss_latency::total 55184491500 # number of overall miss cycles 490system.cpu.dcache.ReadReq_accesses::cpu.data 9017242 # number of ReadReq accesses(hits+misses) 491system.cpu.dcache.ReadReq_accesses::total 9017242 # number of ReadReq accesses(hits+misses) 492system.cpu.dcache.WriteReq_accesses::cpu.data 6149937 # number of WriteReq accesses(hits+misses) 493system.cpu.dcache.WriteReq_accesses::total 6149937 # number of WriteReq accesses(hits+misses) 494system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200010 # number of LoadLockedReq accesses(hits+misses) 495system.cpu.dcache.LoadLockedReq_accesses::total 200010 # number of LoadLockedReq accesses(hits+misses) 496system.cpu.dcache.StoreCondReq_accesses::cpu.data 198989 # number of StoreCondReq accesses(hits+misses) 497system.cpu.dcache.StoreCondReq_accesses::total 198989 # number of StoreCondReq accesses(hits+misses) 498system.cpu.dcache.demand_accesses::cpu.data 15167179 # number of demand (read+write) accesses 499system.cpu.dcache.demand_accesses::total 15167179 # number of demand (read+write) accesses 500system.cpu.dcache.overall_accesses::cpu.data 15167179 # number of overall (read+write) accesses 501system.cpu.dcache.overall_accesses::total 15167179 # number of overall (read+write) accesses 502system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133278 # miss rate for ReadReq accesses 503system.cpu.dcache.ReadReq_miss_rate::total 0.133278 # miss rate for ReadReq accesses 504system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093359 # miss rate for WriteReq accesses 505system.cpu.dcache.WriteReq_miss_rate::total 0.093359 # miss rate for WriteReq accesses 506system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086046 # miss rate for LoadLockedReq accesses 507system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086046 # miss rate for LoadLockedReq accesses 508system.cpu.dcache.demand_miss_rate::cpu.data 0.117092 # miss rate for demand accesses 509system.cpu.dcache.demand_miss_rate::total 0.117092 # miss rate for demand accesses 510system.cpu.dcache.overall_miss_rate::cpu.data 0.117092 # miss rate for overall accesses 511system.cpu.dcache.overall_miss_rate::total 0.117092 # miss rate for overall accesses 512system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27347.721371 # average ReadReq miss latency 513system.cpu.dcache.ReadReq_avg_miss_latency::total 27347.721371 # average ReadReq miss latency 514system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38871.314789 # average WriteReq miss latency 515system.cpu.dcache.WriteReq_avg_miss_latency::total 38871.314789 # average WriteReq miss latency 516system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13415.049390 # average LoadLockedReq miss latency 517system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13415.049390 # average LoadLockedReq miss latency 518system.cpu.dcache.demand_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency 519system.cpu.dcache.demand_avg_miss_latency::total 31073.223627 # average overall miss latency 520system.cpu.dcache.overall_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency 521system.cpu.dcache.overall_avg_miss_latency::total 31073.223627 # average overall miss latency | 455system.cpu.dcache.tags.tag_accesses 63656757 # Number of tag accesses 456system.cpu.dcache.tags.data_accesses 63656757 # Number of data accesses 457system.cpu.dcache.ReadReq_hits::cpu.data 7813939 # number of ReadReq hits 458system.cpu.dcache.ReadReq_hits::total 7813939 # number of ReadReq hits 459system.cpu.dcache.WriteReq_hits::cpu.data 5575873 # number of WriteReq hits 460system.cpu.dcache.WriteReq_hits::total 5575873 # number of WriteReq hits 461system.cpu.dcache.LoadLockedReq_hits::cpu.data 182717 # number of LoadLockedReq hits 462system.cpu.dcache.LoadLockedReq_hits::total 182717 # number of LoadLockedReq hits 463system.cpu.dcache.StoreCondReq_hits::cpu.data 198981 # number of StoreCondReq hits 464system.cpu.dcache.StoreCondReq_hits::total 198981 # number of StoreCondReq hits 465system.cpu.dcache.demand_hits::cpu.data 13389812 # number of demand (read+write) hits 466system.cpu.dcache.demand_hits::total 13389812 # number of demand (read+write) hits 467system.cpu.dcache.overall_hits::cpu.data 13389812 # number of overall hits 468system.cpu.dcache.overall_hits::total 13389812 # number of overall hits 469system.cpu.dcache.ReadReq_misses::cpu.data 1201834 # number of ReadReq misses 470system.cpu.dcache.ReadReq_misses::total 1201834 # number of ReadReq misses 471system.cpu.dcache.WriteReq_misses::cpu.data 574561 # number of WriteReq misses 472system.cpu.dcache.WriteReq_misses::total 574561 # number of WriteReq misses 473system.cpu.dcache.LoadLockedReq_misses::cpu.data 17285 # number of LoadLockedReq misses 474system.cpu.dcache.LoadLockedReq_misses::total 17285 # number of LoadLockedReq misses 475system.cpu.dcache.demand_misses::cpu.data 1776395 # number of demand (read+write) misses 476system.cpu.dcache.demand_misses::total 1776395 # number of demand (read+write) misses 477system.cpu.dcache.overall_misses::cpu.data 1776395 # number of overall misses 478system.cpu.dcache.overall_misses::total 1776395 # number of overall misses 479system.cpu.dcache.ReadReq_miss_latency::cpu.data 32870602000 # number of ReadReq miss cycles 480system.cpu.dcache.ReadReq_miss_latency::total 32870602000 # number of ReadReq miss cycles 481system.cpu.dcache.WriteReq_miss_latency::cpu.data 22298477500 # number of WriteReq miss cycles 482system.cpu.dcache.WriteReq_miss_latency::total 22298477500 # number of WriteReq miss cycles 483system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232185000 # number of LoadLockedReq miss cycles 484system.cpu.dcache.LoadLockedReq_miss_latency::total 232185000 # number of LoadLockedReq miss cycles 485system.cpu.dcache.demand_miss_latency::cpu.data 55169079500 # number of demand (read+write) miss cycles 486system.cpu.dcache.demand_miss_latency::total 55169079500 # number of demand (read+write) miss cycles 487system.cpu.dcache.overall_miss_latency::cpu.data 55169079500 # number of overall miss cycles 488system.cpu.dcache.overall_miss_latency::total 55169079500 # number of overall miss cycles 489system.cpu.dcache.ReadReq_accesses::cpu.data 9015773 # number of ReadReq accesses(hits+misses) 490system.cpu.dcache.ReadReq_accesses::total 9015773 # number of ReadReq accesses(hits+misses) 491system.cpu.dcache.WriteReq_accesses::cpu.data 6150434 # number of WriteReq accesses(hits+misses) 492system.cpu.dcache.WriteReq_accesses::total 6150434 # number of WriteReq accesses(hits+misses) 493system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200002 # number of LoadLockedReq accesses(hits+misses) 494system.cpu.dcache.LoadLockedReq_accesses::total 200002 # number of LoadLockedReq accesses(hits+misses) 495system.cpu.dcache.StoreCondReq_accesses::cpu.data 198981 # number of StoreCondReq accesses(hits+misses) 496system.cpu.dcache.StoreCondReq_accesses::total 198981 # number of StoreCondReq accesses(hits+misses) 497system.cpu.dcache.demand_accesses::cpu.data 15166207 # number of demand (read+write) accesses 498system.cpu.dcache.demand_accesses::total 15166207 # number of demand (read+write) accesses 499system.cpu.dcache.overall_accesses::cpu.data 15166207 # number of overall (read+write) accesses 500system.cpu.dcache.overall_accesses::total 15166207 # number of overall (read+write) accesses 501system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133303 # miss rate for ReadReq accesses 502system.cpu.dcache.ReadReq_miss_rate::total 0.133303 # miss rate for ReadReq accesses 503system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093418 # miss rate for WriteReq accesses 504system.cpu.dcache.WriteReq_miss_rate::total 0.093418 # miss rate for WriteReq accesses 505system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086424 # miss rate for LoadLockedReq accesses 506system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086424 # miss rate for LoadLockedReq accesses 507system.cpu.dcache.demand_miss_rate::cpu.data 0.117128 # miss rate for demand accesses 508system.cpu.dcache.demand_miss_rate::total 0.117128 # miss rate for demand accesses 509system.cpu.dcache.overall_miss_rate::cpu.data 0.117128 # miss rate for overall accesses 510system.cpu.dcache.overall_miss_rate::total 0.117128 # miss rate for overall accesses 511system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27350.367854 # average ReadReq miss latency 512system.cpu.dcache.ReadReq_avg_miss_latency::total 27350.367854 # average ReadReq miss latency 513system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38809.591149 # average WriteReq miss latency 514system.cpu.dcache.WriteReq_avg_miss_latency::total 38809.591149 # average WriteReq miss latency 515system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13432.745155 # average LoadLockedReq miss latency 516system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13432.745155 # average LoadLockedReq miss latency 517system.cpu.dcache.demand_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency 518system.cpu.dcache.demand_avg_miss_latency::total 31056.763558 # average overall miss latency 519system.cpu.dcache.overall_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency 520system.cpu.dcache.overall_avg_miss_latency::total 31056.763558 # average overall miss latency |
| 522system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 523system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 524system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 525system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 526system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 527system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 528system.cpu.dcache.fast_writes 0 # number of fast writes performed 529system.cpu.dcache.cache_copies 0 # number of cache copies performed | 521system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 522system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 523system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 524system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 525system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 526system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 527system.cpu.dcache.fast_writes 0 # number of fast writes performed 528system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 530system.cpu.dcache.writebacks::writebacks 838228 # number of writebacks 531system.cpu.dcache.writebacks::total 838228 # number of writebacks 532system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127318 # number of ReadReq MSHR hits 533system.cpu.dcache.ReadReq_mshr_hits::total 127318 # number of ReadReq MSHR hits 534system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269861 # number of WriteReq MSHR hits 535system.cpu.dcache.WriteReq_mshr_hits::total 269861 # number of WriteReq MSHR hits | 529system.cpu.dcache.writebacks::writebacks 838310 # number of writebacks 530system.cpu.dcache.writebacks::total 838310 # number of writebacks 531system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127379 # number of ReadReq MSHR hits 532system.cpu.dcache.ReadReq_mshr_hits::total 127379 # number of ReadReq MSHR hits 533system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270264 # number of WriteReq MSHR hits 534system.cpu.dcache.WriteReq_mshr_hits::total 270264 # number of WriteReq MSHR hits |
| 536system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 537system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits | 535system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 536system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits |
| 538system.cpu.dcache.demand_mshr_hits::cpu.data 397179 # number of demand (read+write) MSHR hits 539system.cpu.dcache.demand_mshr_hits::total 397179 # number of demand (read+write) MSHR hits 540system.cpu.dcache.overall_mshr_hits::cpu.data 397179 # number of overall MSHR hits 541system.cpu.dcache.overall_mshr_hits::total 397179 # number of overall MSHR hits 542system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074479 # number of ReadReq MSHR misses 543system.cpu.dcache.ReadReq_mshr_misses::total 1074479 # number of ReadReq MSHR misses 544system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304292 # number of WriteReq MSHR misses 545system.cpu.dcache.WriteReq_mshr_misses::total 304292 # number of WriteReq MSHR misses 546system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17207 # number of LoadLockedReq MSHR misses 547system.cpu.dcache.LoadLockedReq_mshr_misses::total 17207 # number of LoadLockedReq MSHR misses 548system.cpu.dcache.demand_mshr_misses::cpu.data 1378771 # number of demand (read+write) MSHR misses 549system.cpu.dcache.demand_mshr_misses::total 1378771 # number of demand (read+write) MSHR misses 550system.cpu.dcache.overall_mshr_misses::cpu.data 1378771 # number of overall MSHR misses 551system.cpu.dcache.overall_mshr_misses::total 1378771 # number of overall MSHR misses 552system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable 553system.cpu.dcache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable 554system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable 555system.cpu.dcache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable 556system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses 557system.cpu.dcache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses 558system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29864669500 # number of ReadReq MSHR miss cycles 559system.cpu.dcache.ReadReq_mshr_miss_latency::total 29864669500 # number of ReadReq MSHR miss cycles 560system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11367980000 # number of WriteReq MSHR miss cycles 561system.cpu.dcache.WriteReq_mshr_miss_latency::total 11367980000 # number of WriteReq MSHR miss cycles 562system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 213500500 # number of LoadLockedReq MSHR miss cycles 563system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 213500500 # number of LoadLockedReq MSHR miss cycles 564system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41232649500 # number of demand (read+write) MSHR miss cycles 565system.cpu.dcache.demand_mshr_miss_latency::total 41232649500 # number of demand (read+write) MSHR miss cycles 566system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41232649500 # number of overall MSHR miss cycles 567system.cpu.dcache.overall_mshr_miss_latency::total 41232649500 # number of overall MSHR miss cycles 568system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1451443000 # number of ReadReq MSHR uncacheable cycles 569system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1451443000 # number of ReadReq MSHR uncacheable cycles 570system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2042111500 # number of WriteReq MSHR uncacheable cycles 571system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2042111500 # number of WriteReq MSHR uncacheable cycles 572system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3493554500 # number of overall MSHR uncacheable cycles 573system.cpu.dcache.overall_mshr_uncacheable_latency::total 3493554500 # number of overall MSHR uncacheable cycles 574system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119158 # mshr miss rate for ReadReq accesses 575system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119158 # mshr miss rate for ReadReq accesses 576system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049479 # mshr miss rate for WriteReq accesses 577system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049479 # mshr miss rate for WriteReq accesses 578system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086031 # mshr miss rate for LoadLockedReq accesses 579system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086031 # mshr miss rate for LoadLockedReq accesses 580system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090905 # mshr miss rate for demand accesses 581system.cpu.dcache.demand_mshr_miss_rate::total 0.090905 # mshr miss rate for demand accesses 582system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090905 # mshr miss rate for overall accesses 583system.cpu.dcache.overall_mshr_miss_rate::total 0.090905 # mshr miss rate for overall accesses 584system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27794.558572 # average ReadReq mshr miss latency 585system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27794.558572 # average ReadReq mshr miss latency 586system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37358.786955 # average WriteReq mshr miss latency 587system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37358.786955 # average WriteReq mshr miss latency 588system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12407.770094 # average LoadLockedReq mshr miss latency 589system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12407.770094 # average LoadLockedReq mshr miss latency 590system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29905.364633 # average overall mshr miss latency 591system.cpu.dcache.demand_avg_mshr_miss_latency::total 29905.364633 # average overall mshr miss latency 592system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29905.364633 # average overall mshr miss latency 593system.cpu.dcache.overall_avg_mshr_miss_latency::total 29905.364633 # average overall mshr miss latency 594system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209322.613210 # average ReadReq mshr uncacheable latency 595system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209322.613210 # average ReadReq mshr uncacheable latency 596system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212255.638707 # average WriteReq mshr uncacheable latency 597system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212255.638707 # average WriteReq mshr uncacheable latency 598system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211027.151918 # average overall mshr uncacheable latency 599system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211027.151918 # average overall mshr uncacheable latency | 537system.cpu.dcache.demand_mshr_hits::cpu.data 397643 # number of demand (read+write) MSHR hits 538system.cpu.dcache.demand_mshr_hits::total 397643 # number of demand (read+write) MSHR hits 539system.cpu.dcache.overall_mshr_hits::cpu.data 397643 # number of overall MSHR hits 540system.cpu.dcache.overall_mshr_hits::total 397643 # number of overall MSHR hits 541system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074455 # number of ReadReq MSHR misses 542system.cpu.dcache.ReadReq_mshr_misses::total 1074455 # number of ReadReq MSHR misses 543system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304297 # number of WriteReq MSHR misses 544system.cpu.dcache.WriteReq_mshr_misses::total 304297 # number of WriteReq MSHR misses 545system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17282 # number of LoadLockedReq MSHR misses 546system.cpu.dcache.LoadLockedReq_mshr_misses::total 17282 # number of LoadLockedReq MSHR misses 547system.cpu.dcache.demand_mshr_misses::cpu.data 1378752 # number of demand (read+write) MSHR misses 548system.cpu.dcache.demand_mshr_misses::total 1378752 # number of demand (read+write) MSHR misses 549system.cpu.dcache.overall_mshr_misses::cpu.data 1378752 # number of overall MSHR misses 550system.cpu.dcache.overall_mshr_misses::total 1378752 # number of overall MSHR misses 551system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 552system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 553system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9620 # number of WriteReq MSHR uncacheable 554system.cpu.dcache.WriteReq_mshr_uncacheable::total 9620 # number of WriteReq MSHR uncacheable 555system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16550 # number of overall MSHR uncacheable misses 556system.cpu.dcache.overall_mshr_uncacheable_misses::total 16550 # number of overall MSHR uncacheable misses 557system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29867395000 # number of ReadReq MSHR miss cycles 558system.cpu.dcache.ReadReq_mshr_miss_latency::total 29867395000 # number of ReadReq MSHR miss cycles 559system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11355989000 # number of WriteReq MSHR miss cycles 560system.cpu.dcache.WriteReq_mshr_miss_latency::total 11355989000 # number of WriteReq MSHR miss cycles 561system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214737500 # number of LoadLockedReq MSHR miss cycles 562system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214737500 # number of LoadLockedReq MSHR miss cycles 563system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41223384000 # number of demand (read+write) MSHR miss cycles 564system.cpu.dcache.demand_mshr_miss_latency::total 41223384000 # number of demand (read+write) MSHR miss cycles 565system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41223384000 # number of overall MSHR miss cycles 566system.cpu.dcache.overall_mshr_miss_latency::total 41223384000 # number of overall MSHR miss cycles 567system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450621500 # number of ReadReq MSHR uncacheable cycles 568system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450621500 # number of ReadReq MSHR uncacheable cycles 569system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2041589000 # number of WriteReq MSHR uncacheable cycles 570system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2041589000 # number of WriteReq MSHR uncacheable cycles 571system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3492210500 # number of overall MSHR uncacheable cycles 572system.cpu.dcache.overall_mshr_uncacheable_latency::total 3492210500 # number of overall MSHR uncacheable cycles 573system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119175 # mshr miss rate for ReadReq accesses 574system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119175 # mshr miss rate for ReadReq accesses 575system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049476 # mshr miss rate for WriteReq accesses 576system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049476 # mshr miss rate for WriteReq accesses 577system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086409 # mshr miss rate for LoadLockedReq accesses 578system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086409 # mshr miss rate for LoadLockedReq accesses 579system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090909 # mshr miss rate for demand accesses 580system.cpu.dcache.demand_mshr_miss_rate::total 0.090909 # mshr miss rate for demand accesses 581system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090909 # mshr miss rate for overall accesses 582system.cpu.dcache.overall_mshr_miss_rate::total 0.090909 # mshr miss rate for overall accesses 583system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27797.716051 # average ReadReq mshr miss latency 584system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27797.716051 # average ReadReq mshr miss latency 585system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37318.767520 # average WriteReq mshr miss latency 586system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37318.767520 # average WriteReq mshr miss latency 587system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12425.500521 # average LoadLockedReq mshr miss latency 588system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12425.500521 # average LoadLockedReq mshr miss latency 589system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29899.056538 # average overall mshr miss latency 590system.cpu.dcache.demand_avg_mshr_miss_latency::total 29899.056538 # average overall mshr miss latency 591system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29899.056538 # average overall mshr miss latency 592system.cpu.dcache.overall_avg_mshr_miss_latency::total 29899.056538 # average overall mshr miss latency 593system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209324.891775 # average ReadReq mshr uncacheable latency 594system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209324.891775 # average ReadReq mshr uncacheable latency 595system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212223.388773 # average WriteReq mshr uncacheable latency 596system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212223.388773 # average WriteReq mshr uncacheable latency 597system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211009.697885 # average overall mshr uncacheable latency 598system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211009.697885 # average overall mshr uncacheable latency |
| 600system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 599system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 601system.cpu.icache.tags.replacements 1459012 # number of replacements 602system.cpu.icache.tags.tagsinuse 509.459740 # Cycle average of tags in use 603system.cpu.icache.tags.total_refs 18968780 # Total number of references to valid blocks. 604system.cpu.icache.tags.sampled_refs 1459523 # Sample count of references to valid blocks. 605system.cpu.icache.tags.avg_refs 12.996561 # Average number of references to valid blocks. 606system.cpu.icache.tags.warmup_cycle 33609211500 # Cycle when the warmup percentage was hit. 607system.cpu.icache.tags.occ_blocks::cpu.inst 509.459740 # Average occupied blocks per requestor 608system.cpu.icache.tags.occ_percent::cpu.inst 0.995039 # Average percentage of cache occupancy 609system.cpu.icache.tags.occ_percent::total 0.995039 # Average percentage of cache occupancy | 600system.cpu.icache.tags.replacements 1459068 # number of replacements 601system.cpu.icache.tags.tagsinuse 509.460685 # Cycle average of tags in use 602system.cpu.icache.tags.total_refs 18942908 # Total number of references to valid blocks. 603system.cpu.icache.tags.sampled_refs 1459579 # Sample count of references to valid blocks. 604system.cpu.icache.tags.avg_refs 12.978337 # Average number of references to valid blocks. 605system.cpu.icache.tags.warmup_cycle 33609235500 # Cycle when the warmup percentage was hit. 606system.cpu.icache.tags.occ_blocks::cpu.inst 509.460685 # Average occupied blocks per requestor 607system.cpu.icache.tags.occ_percent::cpu.inst 0.995040 # Average percentage of cache occupancy 608system.cpu.icache.tags.occ_percent::total 0.995040 # Average percentage of cache occupancy |
| 610system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 611system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id | 609system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 610system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id |
| 612system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::2 401 # Occupied blocks per task id | 611system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id |
| 614system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 613system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 615system.cpu.icache.tags.tag_accesses 21888175 # Number of tag accesses 616system.cpu.icache.tags.data_accesses 21888175 # Number of data accesses 617system.cpu.icache.ReadReq_hits::cpu.inst 18968783 # number of ReadReq hits 618system.cpu.icache.ReadReq_hits::total 18968783 # number of ReadReq hits 619system.cpu.icache.demand_hits::cpu.inst 18968783 # number of demand (read+write) hits 620system.cpu.icache.demand_hits::total 18968783 # number of demand (read+write) hits 621system.cpu.icache.overall_hits::cpu.inst 18968783 # number of overall hits 622system.cpu.icache.overall_hits::total 18968783 # number of overall hits 623system.cpu.icache.ReadReq_misses::cpu.inst 1459696 # number of ReadReq misses 624system.cpu.icache.ReadReq_misses::total 1459696 # number of ReadReq misses 625system.cpu.icache.demand_misses::cpu.inst 1459696 # number of demand (read+write) misses 626system.cpu.icache.demand_misses::total 1459696 # number of demand (read+write) misses 627system.cpu.icache.overall_misses::cpu.inst 1459696 # number of overall misses 628system.cpu.icache.overall_misses::total 1459696 # number of overall misses 629system.cpu.icache.ReadReq_miss_latency::cpu.inst 20145975000 # number of ReadReq miss cycles 630system.cpu.icache.ReadReq_miss_latency::total 20145975000 # number of ReadReq miss cycles 631system.cpu.icache.demand_miss_latency::cpu.inst 20145975000 # number of demand (read+write) miss cycles 632system.cpu.icache.demand_miss_latency::total 20145975000 # number of demand (read+write) miss cycles 633system.cpu.icache.overall_miss_latency::cpu.inst 20145975000 # number of overall miss cycles 634system.cpu.icache.overall_miss_latency::total 20145975000 # number of overall miss cycles 635system.cpu.icache.ReadReq_accesses::cpu.inst 20428479 # number of ReadReq accesses(hits+misses) 636system.cpu.icache.ReadReq_accesses::total 20428479 # number of ReadReq accesses(hits+misses) 637system.cpu.icache.demand_accesses::cpu.inst 20428479 # number of demand (read+write) accesses 638system.cpu.icache.demand_accesses::total 20428479 # number of demand (read+write) accesses 639system.cpu.icache.overall_accesses::cpu.inst 20428479 # number of overall (read+write) accesses 640system.cpu.icache.overall_accesses::total 20428479 # number of overall (read+write) accesses 641system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071454 # miss rate for ReadReq accesses 642system.cpu.icache.ReadReq_miss_rate::total 0.071454 # miss rate for ReadReq accesses 643system.cpu.icache.demand_miss_rate::cpu.inst 0.071454 # miss rate for demand accesses 644system.cpu.icache.demand_miss_rate::total 0.071454 # miss rate for demand accesses 645system.cpu.icache.overall_miss_rate::cpu.inst 0.071454 # miss rate for overall accesses 646system.cpu.icache.overall_miss_rate::total 0.071454 # miss rate for overall accesses 647system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.486748 # average ReadReq miss latency 648system.cpu.icache.ReadReq_avg_miss_latency::total 13801.486748 # average ReadReq miss latency 649system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.486748 # average overall miss latency 650system.cpu.icache.demand_avg_miss_latency::total 13801.486748 # average overall miss latency 651system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.486748 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::total 13801.486748 # average overall miss latency | 614system.cpu.icache.tags.tag_accesses 21862421 # Number of tag accesses 615system.cpu.icache.tags.data_accesses 21862421 # Number of data accesses 616system.cpu.icache.ReadReq_hits::cpu.inst 18942911 # number of ReadReq hits 617system.cpu.icache.ReadReq_hits::total 18942911 # number of ReadReq hits 618system.cpu.icache.demand_hits::cpu.inst 18942911 # number of demand (read+write) hits 619system.cpu.icache.demand_hits::total 18942911 # number of demand (read+write) hits 620system.cpu.icache.overall_hits::cpu.inst 18942911 # number of overall hits 621system.cpu.icache.overall_hits::total 18942911 # number of overall hits 622system.cpu.icache.ReadReq_misses::cpu.inst 1459755 # number of ReadReq misses 623system.cpu.icache.ReadReq_misses::total 1459755 # number of ReadReq misses 624system.cpu.icache.demand_misses::cpu.inst 1459755 # number of demand (read+write) misses 625system.cpu.icache.demand_misses::total 1459755 # number of demand (read+write) misses 626system.cpu.icache.overall_misses::cpu.inst 1459755 # number of overall misses 627system.cpu.icache.overall_misses::total 1459755 # number of overall misses 628system.cpu.icache.ReadReq_miss_latency::cpu.inst 20136698000 # number of ReadReq miss cycles 629system.cpu.icache.ReadReq_miss_latency::total 20136698000 # number of ReadReq miss cycles 630system.cpu.icache.demand_miss_latency::cpu.inst 20136698000 # number of demand (read+write) miss cycles 631system.cpu.icache.demand_miss_latency::total 20136698000 # number of demand (read+write) miss cycles 632system.cpu.icache.overall_miss_latency::cpu.inst 20136698000 # number of overall miss cycles 633system.cpu.icache.overall_miss_latency::total 20136698000 # number of overall miss cycles 634system.cpu.icache.ReadReq_accesses::cpu.inst 20402666 # number of ReadReq accesses(hits+misses) 635system.cpu.icache.ReadReq_accesses::total 20402666 # number of ReadReq accesses(hits+misses) 636system.cpu.icache.demand_accesses::cpu.inst 20402666 # number of demand (read+write) accesses 637system.cpu.icache.demand_accesses::total 20402666 # number of demand (read+write) accesses 638system.cpu.icache.overall_accesses::cpu.inst 20402666 # number of overall (read+write) accesses 639system.cpu.icache.overall_accesses::total 20402666 # number of overall (read+write) accesses 640system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071547 # miss rate for ReadReq accesses 641system.cpu.icache.ReadReq_miss_rate::total 0.071547 # miss rate for ReadReq accesses 642system.cpu.icache.demand_miss_rate::cpu.inst 0.071547 # miss rate for demand accesses 643system.cpu.icache.demand_miss_rate::total 0.071547 # miss rate for demand accesses 644system.cpu.icache.overall_miss_rate::cpu.inst 0.071547 # miss rate for overall accesses 645system.cpu.icache.overall_miss_rate::total 0.071547 # miss rate for overall accesses 646system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13794.573747 # average ReadReq miss latency 647system.cpu.icache.ReadReq_avg_miss_latency::total 13794.573747 # average ReadReq miss latency 648system.cpu.icache.demand_avg_miss_latency::cpu.inst 13794.573747 # average overall miss latency 649system.cpu.icache.demand_avg_miss_latency::total 13794.573747 # average overall miss latency 650system.cpu.icache.overall_avg_miss_latency::cpu.inst 13794.573747 # average overall miss latency 651system.cpu.icache.overall_avg_miss_latency::total 13794.573747 # average overall miss latency |
| 653system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 654system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 656system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 658system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu.icache.fast_writes 0 # number of fast writes performed 660system.cpu.icache.cache_copies 0 # number of cache copies performed | 652system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 653system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 655system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 656system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 657system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 658system.cpu.icache.fast_writes 0 # number of fast writes performed 659system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 661system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459696 # number of ReadReq MSHR misses 662system.cpu.icache.ReadReq_mshr_misses::total 1459696 # number of ReadReq MSHR misses 663system.cpu.icache.demand_mshr_misses::cpu.inst 1459696 # number of demand (read+write) MSHR misses 664system.cpu.icache.demand_mshr_misses::total 1459696 # number of demand (read+write) MSHR misses 665system.cpu.icache.overall_mshr_misses::cpu.inst 1459696 # number of overall MSHR misses 666system.cpu.icache.overall_mshr_misses::total 1459696 # number of overall MSHR misses 667system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18686279000 # number of ReadReq MSHR miss cycles 668system.cpu.icache.ReadReq_mshr_miss_latency::total 18686279000 # number of ReadReq MSHR miss cycles 669system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18686279000 # number of demand (read+write) MSHR miss cycles 670system.cpu.icache.demand_mshr_miss_latency::total 18686279000 # number of demand (read+write) MSHR miss cycles 671system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18686279000 # number of overall MSHR miss cycles 672system.cpu.icache.overall_mshr_miss_latency::total 18686279000 # number of overall MSHR miss cycles 673system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071454 # mshr miss rate for ReadReq accesses 674system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071454 # mshr miss rate for ReadReq accesses 675system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071454 # mshr miss rate for demand accesses 676system.cpu.icache.demand_mshr_miss_rate::total 0.071454 # mshr miss rate for demand accesses 677system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071454 # mshr miss rate for overall accesses 678system.cpu.icache.overall_mshr_miss_rate::total 0.071454 # mshr miss rate for overall accesses 679system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12801.486748 # average ReadReq mshr miss latency 680system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12801.486748 # average ReadReq mshr miss latency 681system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12801.486748 # average overall mshr miss latency 682system.cpu.icache.demand_avg_mshr_miss_latency::total 12801.486748 # average overall mshr miss latency 683system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12801.486748 # average overall mshr miss latency 684system.cpu.icache.overall_avg_mshr_miss_latency::total 12801.486748 # average overall mshr miss latency | 660system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459755 # number of ReadReq MSHR misses 661system.cpu.icache.ReadReq_mshr_misses::total 1459755 # number of ReadReq MSHR misses 662system.cpu.icache.demand_mshr_misses::cpu.inst 1459755 # number of demand (read+write) MSHR misses 663system.cpu.icache.demand_mshr_misses::total 1459755 # number of demand (read+write) MSHR misses 664system.cpu.icache.overall_mshr_misses::cpu.inst 1459755 # number of overall MSHR misses 665system.cpu.icache.overall_mshr_misses::total 1459755 # number of overall MSHR misses 666system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18676943000 # number of ReadReq MSHR miss cycles 667system.cpu.icache.ReadReq_mshr_miss_latency::total 18676943000 # number of ReadReq MSHR miss cycles 668system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18676943000 # number of demand (read+write) MSHR miss cycles 669system.cpu.icache.demand_mshr_miss_latency::total 18676943000 # number of demand (read+write) MSHR miss cycles 670system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18676943000 # number of overall MSHR miss cycles 671system.cpu.icache.overall_mshr_miss_latency::total 18676943000 # number of overall MSHR miss cycles 672system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071547 # mshr miss rate for ReadReq accesses 673system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071547 # mshr miss rate for ReadReq accesses 674system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071547 # mshr miss rate for demand accesses 675system.cpu.icache.demand_mshr_miss_rate::total 0.071547 # mshr miss rate for demand accesses 676system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071547 # mshr miss rate for overall accesses 677system.cpu.icache.overall_mshr_miss_rate::total 0.071547 # mshr miss rate for overall accesses 678system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12794.573747 # average ReadReq mshr miss latency 679system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12794.573747 # average ReadReq mshr miss latency 680system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12794.573747 # average overall mshr miss latency 681system.cpu.icache.demand_avg_mshr_miss_latency::total 12794.573747 # average overall mshr miss latency 682system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12794.573747 # average overall mshr miss latency 683system.cpu.icache.overall_avg_mshr_miss_latency::total 12794.573747 # average overall mshr miss latency |
| 685system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 684system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 686system.cpu.l2cache.tags.replacements 339196 # number of replacements 687system.cpu.l2cache.tags.tagsinuse 65318.328839 # Cycle average of tags in use 688system.cpu.l2cache.tags.total_refs 4996938 # Total number of references to valid blocks. 689system.cpu.l2cache.tags.sampled_refs 404358 # Sample count of references to valid blocks. 690system.cpu.l2cache.tags.avg_refs 12.357708 # Average number of references to valid blocks. | 685system.cpu.l2cache.tags.replacements 339197 # number of replacements 686system.cpu.l2cache.tags.tagsinuse 65316.861882 # Cycle average of tags in use 687system.cpu.l2cache.tags.total_refs 4997134 # Total number of references to valid blocks. 688system.cpu.l2cache.tags.sampled_refs 404357 # Sample count of references to valid blocks. 689system.cpu.l2cache.tags.avg_refs 12.358223 # Average number of references to valid blocks. |
| 691system.cpu.l2cache.tags.warmup_cycle 6286116000 # Cycle when the warmup percentage was hit. | 690system.cpu.l2cache.tags.warmup_cycle 6286116000 # Cycle when the warmup percentage was hit. |
| 692system.cpu.l2cache.tags.occ_blocks::writebacks 54387.720391 # Average occupied blocks per requestor 693system.cpu.l2cache.tags.occ_blocks::cpu.inst 5865.311953 # Average occupied blocks per requestor 694system.cpu.l2cache.tags.occ_blocks::cpu.data 5065.296495 # Average occupied blocks per requestor 695system.cpu.l2cache.tags.occ_percent::writebacks 0.829891 # Average percentage of cache occupancy 696system.cpu.l2cache.tags.occ_percent::cpu.inst 0.089498 # Average percentage of cache occupancy 697system.cpu.l2cache.tags.occ_percent::cpu.data 0.077290 # Average percentage of cache occupancy 698system.cpu.l2cache.tags.occ_percent::total 0.996679 # Average percentage of cache occupancy 699system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 700system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id | 691system.cpu.l2cache.tags.occ_blocks::writebacks 54372.711085 # Average occupied blocks per requestor 692system.cpu.l2cache.tags.occ_blocks::cpu.inst 5866.673832 # Average occupied blocks per requestor 693system.cpu.l2cache.tags.occ_blocks::cpu.data 5077.476965 # Average occupied blocks per requestor 694system.cpu.l2cache.tags.occ_percent::writebacks 0.829662 # Average percentage of cache occupancy 695system.cpu.l2cache.tags.occ_percent::cpu.inst 0.089518 # Average percentage of cache occupancy 696system.cpu.l2cache.tags.occ_percent::cpu.data 0.077476 # Average percentage of cache occupancy 697system.cpu.l2cache.tags.occ_percent::total 0.996656 # Average percentage of cache occupancy 698system.cpu.l2cache.tags.occ_task_id_blocks::1024 65160 # Occupied blocks per task id 699system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id |
| 701system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id | 700system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id |
| 702system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5169 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2809 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55538 # Occupied blocks per task id 705system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id 706system.cpu.l2cache.tags.tag_accesses 46373741 # Number of tag accesses 707system.cpu.l2cache.tags.data_accesses 46373741 # Number of data accesses 708system.cpu.l2cache.Writeback_hits::writebacks 838228 # number of Writeback hits 709system.cpu.l2cache.Writeback_hits::total 838228 # number of Writeback hits | 701system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5171 # Occupied blocks per task id 702system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2816 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55529 # Occupied blocks per task id 704system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994263 # Percentage of cache occupancy per task id 705system.cpu.l2cache.tags.tag_accesses 46375417 # Number of tag accesses 706system.cpu.l2cache.tags.data_accesses 46375417 # Number of data accesses 707system.cpu.l2cache.Writeback_hits::writebacks 838310 # number of Writeback hits 708system.cpu.l2cache.Writeback_hits::total 838310 # number of Writeback hits |
| 710system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 711system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 709system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 710system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 712system.cpu.l2cache.ReadExReq_hits::cpu.data 187768 # number of ReadExReq hits 713system.cpu.l2cache.ReadExReq_hits::total 187768 # number of ReadExReq hits 714system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1443233 # number of ReadCleanReq hits 715system.cpu.l2cache.ReadCleanReq_hits::total 1443233 # number of ReadCleanReq hits 716system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819477 # number of ReadSharedReq hits 717system.cpu.l2cache.ReadSharedReq_hits::total 819477 # number of ReadSharedReq hits 718system.cpu.l2cache.demand_hits::cpu.inst 1443233 # number of demand (read+write) hits 719system.cpu.l2cache.demand_hits::cpu.data 1007245 # number of demand (read+write) hits 720system.cpu.l2cache.demand_hits::total 2450478 # number of demand (read+write) hits 721system.cpu.l2cache.overall_hits::cpu.inst 1443233 # number of overall hits 722system.cpu.l2cache.overall_hits::cpu.data 1007245 # number of overall hits 723system.cpu.l2cache.overall_hits::total 2450478 # number of overall hits 724system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses 725system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses 726system.cpu.l2cache.ReadExReq_misses::cpu.data 116534 # number of ReadExReq misses 727system.cpu.l2cache.ReadExReq_misses::total 116534 # number of ReadExReq misses 728system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16403 # number of ReadCleanReq misses 729system.cpu.l2cache.ReadCleanReq_misses::total 16403 # number of ReadCleanReq misses 730system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272179 # number of ReadSharedReq misses 731system.cpu.l2cache.ReadSharedReq_misses::total 272179 # number of ReadSharedReq misses 732system.cpu.l2cache.demand_misses::cpu.inst 16403 # number of demand (read+write) misses 733system.cpu.l2cache.demand_misses::cpu.data 388713 # number of demand (read+write) misses | 711system.cpu.l2cache.ReadExReq_hits::cpu.data 187763 # number of ReadExReq hits 712system.cpu.l2cache.ReadExReq_hits::total 187763 # number of ReadExReq hits 713system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1443287 # number of ReadCleanReq hits 714system.cpu.l2cache.ReadCleanReq_hits::total 1443287 # number of ReadCleanReq hits 715system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819540 # number of ReadSharedReq hits 716system.cpu.l2cache.ReadSharedReq_hits::total 819540 # number of ReadSharedReq hits 717system.cpu.l2cache.demand_hits::cpu.inst 1443287 # number of demand (read+write) hits 718system.cpu.l2cache.demand_hits::cpu.data 1007303 # number of demand (read+write) hits 719system.cpu.l2cache.demand_hits::total 2450590 # number of demand (read+write) hits 720system.cpu.l2cache.overall_hits::cpu.inst 1443287 # number of overall hits 721system.cpu.l2cache.overall_hits::cpu.data 1007303 # number of overall hits 722system.cpu.l2cache.overall_hits::total 2450590 # number of overall hits 723system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses 724system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses 725system.cpu.l2cache.ReadExReq_misses::cpu.data 116544 # number of ReadExReq misses 726system.cpu.l2cache.ReadExReq_misses::total 116544 # number of ReadExReq misses 727system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16406 # number of ReadCleanReq misses 728system.cpu.l2cache.ReadCleanReq_misses::total 16406 # number of ReadCleanReq misses 729system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272166 # number of ReadSharedReq misses 730system.cpu.l2cache.ReadSharedReq_misses::total 272166 # number of ReadSharedReq misses 731system.cpu.l2cache.demand_misses::cpu.inst 16406 # number of demand (read+write) misses 732system.cpu.l2cache.demand_misses::cpu.data 388710 # number of demand (read+write) misses |
| 734system.cpu.l2cache.demand_misses::total 405116 # number of demand (read+write) misses | 733system.cpu.l2cache.demand_misses::total 405116 # number of demand (read+write) misses |
| 735system.cpu.l2cache.overall_misses::cpu.inst 16403 # number of overall misses 736system.cpu.l2cache.overall_misses::cpu.data 388713 # number of overall misses | 734system.cpu.l2cache.overall_misses::cpu.inst 16406 # number of overall misses 735system.cpu.l2cache.overall_misses::cpu.data 388710 # number of overall misses |
| 737system.cpu.l2cache.overall_misses::total 405116 # number of overall misses 738system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 253000 # number of UpgradeReq miss cycles 739system.cpu.l2cache.UpgradeReq_miss_latency::total 253000 # number of UpgradeReq miss cycles | 736system.cpu.l2cache.overall_misses::total 405116 # number of overall misses 737system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 253000 # number of UpgradeReq miss cycles 738system.cpu.l2cache.UpgradeReq_miss_latency::total 253000 # number of UpgradeReq miss cycles |
| 740system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8935872000 # number of ReadExReq miss cycles 741system.cpu.l2cache.ReadExReq_miss_latency::total 8935872000 # number of ReadExReq miss cycles 742system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1324497500 # number of ReadCleanReq miss cycles 743system.cpu.l2cache.ReadCleanReq_miss_latency::total 1324497500 # number of ReadCleanReq miss cycles 744system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19726651500 # number of ReadSharedReq miss cycles 745system.cpu.l2cache.ReadSharedReq_miss_latency::total 19726651500 # number of ReadSharedReq miss cycles 746system.cpu.l2cache.demand_miss_latency::cpu.inst 1324497500 # number of demand (read+write) miss cycles 747system.cpu.l2cache.demand_miss_latency::cpu.data 28662523500 # number of demand (read+write) miss cycles 748system.cpu.l2cache.demand_miss_latency::total 29987021000 # number of demand (read+write) miss cycles 749system.cpu.l2cache.overall_miss_latency::cpu.inst 1324497500 # number of overall miss cycles 750system.cpu.l2cache.overall_miss_latency::cpu.data 28662523500 # number of overall miss cycles 751system.cpu.l2cache.overall_miss_latency::total 29987021000 # number of overall miss cycles 752system.cpu.l2cache.Writeback_accesses::writebacks 838228 # number of Writeback accesses(hits+misses) 753system.cpu.l2cache.Writeback_accesses::total 838228 # number of Writeback accesses(hits+misses) 754system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses) 755system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses) 756system.cpu.l2cache.ReadExReq_accesses::cpu.data 304302 # number of ReadExReq accesses(hits+misses) 757system.cpu.l2cache.ReadExReq_accesses::total 304302 # number of ReadExReq accesses(hits+misses) 758system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1459636 # number of ReadCleanReq accesses(hits+misses) 759system.cpu.l2cache.ReadCleanReq_accesses::total 1459636 # number of ReadCleanReq accesses(hits+misses) 760system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091656 # number of ReadSharedReq accesses(hits+misses) 761system.cpu.l2cache.ReadSharedReq_accesses::total 1091656 # number of ReadSharedReq accesses(hits+misses) 762system.cpu.l2cache.demand_accesses::cpu.inst 1459636 # number of demand (read+write) accesses 763system.cpu.l2cache.demand_accesses::cpu.data 1395958 # number of demand (read+write) accesses 764system.cpu.l2cache.demand_accesses::total 2855594 # number of demand (read+write) accesses 765system.cpu.l2cache.overall_accesses::cpu.inst 1459636 # number of overall (read+write) accesses 766system.cpu.l2cache.overall_accesses::cpu.data 1395958 # number of overall (read+write) accesses 767system.cpu.l2cache.overall_accesses::total 2855594 # number of overall (read+write) accesses 768system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses 769system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800000 # miss rate for UpgradeReq accesses 770system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382955 # miss rate for ReadExReq accesses 771system.cpu.l2cache.ReadExReq_miss_rate::total 0.382955 # miss rate for ReadExReq accesses 772system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011238 # miss rate for ReadCleanReq accesses 773system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011238 # miss rate for ReadCleanReq accesses 774system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249327 # miss rate for ReadSharedReq accesses 775system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249327 # miss rate for ReadSharedReq accesses 776system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011238 # miss rate for demand accesses 777system.cpu.l2cache.demand_miss_rate::cpu.data 0.278456 # miss rate for demand accesses 778system.cpu.l2cache.demand_miss_rate::total 0.141868 # miss rate for demand accesses 779system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011238 # miss rate for overall accesses 780system.cpu.l2cache.overall_miss_rate::cpu.data 0.278456 # miss rate for overall accesses 781system.cpu.l2cache.overall_miss_rate::total 0.141868 # miss rate for overall accesses 782system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15812.500000 # average UpgradeReq miss latency 783system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15812.500000 # average UpgradeReq miss latency 784system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76680.385124 # average ReadExReq miss latency 785system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76680.385124 # average ReadExReq miss latency 786system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80747.271841 # average ReadCleanReq miss latency 787system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80747.271841 # average ReadCleanReq miss latency 788system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72476.757942 # average ReadSharedReq miss latency 789system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72476.757942 # average ReadSharedReq miss latency 790system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80747.271841 # average overall miss latency 791system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73736.982041 # average overall miss latency 792system.cpu.l2cache.demand_avg_miss_latency::total 74020.826134 # average overall miss latency 793system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80747.271841 # average overall miss latency 794system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73736.982041 # average overall miss latency 795system.cpu.l2cache.overall_avg_miss_latency::total 74020.826134 # average overall miss latency | 739system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8923529500 # number of ReadExReq miss cycles 740system.cpu.l2cache.ReadExReq_miss_latency::total 8923529500 # number of ReadExReq miss cycles 741system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1314713000 # number of ReadCleanReq miss cycles 742system.cpu.l2cache.ReadCleanReq_miss_latency::total 1314713000 # number of ReadCleanReq miss cycles 743system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19729862500 # number of ReadSharedReq miss cycles 744system.cpu.l2cache.ReadSharedReq_miss_latency::total 19729862500 # number of ReadSharedReq miss cycles 745system.cpu.l2cache.demand_miss_latency::cpu.inst 1314713000 # number of demand (read+write) miss cycles 746system.cpu.l2cache.demand_miss_latency::cpu.data 28653392000 # number of demand (read+write) miss cycles 747system.cpu.l2cache.demand_miss_latency::total 29968105000 # number of demand (read+write) miss cycles 748system.cpu.l2cache.overall_miss_latency::cpu.inst 1314713000 # number of overall miss cycles 749system.cpu.l2cache.overall_miss_latency::cpu.data 28653392000 # number of overall miss cycles 750system.cpu.l2cache.overall_miss_latency::total 29968105000 # number of overall miss cycles 751system.cpu.l2cache.Writeback_accesses::writebacks 838310 # number of Writeback accesses(hits+misses) 752system.cpu.l2cache.Writeback_accesses::total 838310 # number of Writeback accesses(hits+misses) 753system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) 754system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) 755system.cpu.l2cache.ReadExReq_accesses::cpu.data 304307 # number of ReadExReq accesses(hits+misses) 756system.cpu.l2cache.ReadExReq_accesses::total 304307 # number of ReadExReq accesses(hits+misses) 757system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1459693 # number of ReadCleanReq accesses(hits+misses) 758system.cpu.l2cache.ReadCleanReq_accesses::total 1459693 # number of ReadCleanReq accesses(hits+misses) 759system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091706 # number of ReadSharedReq accesses(hits+misses) 760system.cpu.l2cache.ReadSharedReq_accesses::total 1091706 # number of ReadSharedReq accesses(hits+misses) 761system.cpu.l2cache.demand_accesses::cpu.inst 1459693 # number of demand (read+write) accesses 762system.cpu.l2cache.demand_accesses::cpu.data 1396013 # number of demand (read+write) accesses 763system.cpu.l2cache.demand_accesses::total 2855706 # number of demand (read+write) accesses 764system.cpu.l2cache.overall_accesses::cpu.inst 1459693 # number of overall (read+write) accesses 765system.cpu.l2cache.overall_accesses::cpu.data 1396013 # number of overall (read+write) accesses 766system.cpu.l2cache.overall_accesses::total 2855706 # number of overall (read+write) accesses 767system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.809524 # miss rate for UpgradeReq accesses 768system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses 769system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382982 # miss rate for ReadExReq accesses 770system.cpu.l2cache.ReadExReq_miss_rate::total 0.382982 # miss rate for ReadExReq accesses 771system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011239 # miss rate for ReadCleanReq accesses 772system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011239 # miss rate for ReadCleanReq accesses 773system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249303 # miss rate for ReadSharedReq accesses 774system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249303 # miss rate for ReadSharedReq accesses 775system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011239 # miss rate for demand accesses 776system.cpu.l2cache.demand_miss_rate::cpu.data 0.278443 # miss rate for demand accesses 777system.cpu.l2cache.demand_miss_rate::total 0.141862 # miss rate for demand accesses 778system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011239 # miss rate for overall accesses 779system.cpu.l2cache.overall_miss_rate::cpu.data 0.278443 # miss rate for overall accesses 780system.cpu.l2cache.overall_miss_rate::total 0.141862 # miss rate for overall accesses 781system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14882.352941 # average UpgradeReq miss latency 782system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14882.352941 # average UpgradeReq miss latency 783system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76567.901393 # average ReadExReq miss latency 784system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76567.901393 # average ReadExReq miss latency 785system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80136.108741 # average ReadCleanReq miss latency 786system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80136.108741 # average ReadCleanReq miss latency 787system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72492.017739 # average ReadSharedReq miss latency 788system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72492.017739 # average ReadSharedReq miss latency 789system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80136.108741 # average overall miss latency 790system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73714.059324 # average overall miss latency 791system.cpu.l2cache.demand_avg_miss_latency::total 73974.133335 # average overall miss latency 792system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80136.108741 # average overall miss latency 793system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73714.059324 # average overall miss latency 794system.cpu.l2cache.overall_avg_miss_latency::total 73974.133335 # average overall miss latency |
| 796system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 797system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 798system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 799system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 800system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 801system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 802system.cpu.l2cache.fast_writes 0 # number of fast writes performed 803system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 795system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 796system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 797system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 798system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 799system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 800system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 801system.cpu.l2cache.fast_writes 0 # number of fast writes performed 802system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 804system.cpu.l2cache.writebacks::writebacks 76513 # number of writebacks 805system.cpu.l2cache.writebacks::total 76513 # number of writebacks | 803system.cpu.l2cache.writebacks::writebacks 76511 # number of writebacks 804system.cpu.l2cache.writebacks::total 76511 # number of writebacks |
| 806system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 317 # number of CleanEvict MSHR misses 807system.cpu.l2cache.CleanEvict_mshr_misses::total 317 # number of CleanEvict MSHR misses | 805system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 317 # number of CleanEvict MSHR misses 806system.cpu.l2cache.CleanEvict_mshr_misses::total 317 # number of CleanEvict MSHR misses |
| 808system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses 809system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses 810system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116534 # number of ReadExReq MSHR misses 811system.cpu.l2cache.ReadExReq_mshr_misses::total 116534 # number of ReadExReq MSHR misses 812system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16403 # number of ReadCleanReq MSHR misses 813system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16403 # number of ReadCleanReq MSHR misses 814system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272179 # number of ReadSharedReq MSHR misses 815system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272179 # number of ReadSharedReq MSHR misses 816system.cpu.l2cache.demand_mshr_misses::cpu.inst 16403 # number of demand (read+write) MSHR misses 817system.cpu.l2cache.demand_mshr_misses::cpu.data 388713 # number of demand (read+write) MSHR misses | 807system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses 808system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses 809system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116544 # number of ReadExReq MSHR misses 810system.cpu.l2cache.ReadExReq_mshr_misses::total 116544 # number of ReadExReq MSHR misses 811system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16406 # number of ReadCleanReq MSHR misses 812system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16406 # number of ReadCleanReq MSHR misses 813system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272166 # number of ReadSharedReq MSHR misses 814system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272166 # number of ReadSharedReq MSHR misses 815system.cpu.l2cache.demand_mshr_misses::cpu.inst 16406 # number of demand (read+write) MSHR misses 816system.cpu.l2cache.demand_mshr_misses::cpu.data 388710 # number of demand (read+write) MSHR misses |
| 818system.cpu.l2cache.demand_mshr_misses::total 405116 # number of demand (read+write) MSHR misses | 817system.cpu.l2cache.demand_mshr_misses::total 405116 # number of demand (read+write) MSHR misses |
| 819system.cpu.l2cache.overall_mshr_misses::cpu.inst 16403 # number of overall MSHR misses 820system.cpu.l2cache.overall_mshr_misses::cpu.data 388713 # number of overall MSHR misses | 818system.cpu.l2cache.overall_mshr_misses::cpu.inst 16406 # number of overall MSHR misses 819system.cpu.l2cache.overall_mshr_misses::cpu.data 388710 # number of overall MSHR misses |
| 821system.cpu.l2cache.overall_mshr_misses::total 405116 # number of overall MSHR misses | 820system.cpu.l2cache.overall_mshr_misses::total 405116 # number of overall MSHR misses |
| 822system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable 823system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable 824system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable 825system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable 826system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses 827system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses 828system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 431000 # number of UpgradeReq MSHR miss cycles 829system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 431000 # number of UpgradeReq MSHR miss cycles 830system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7770532000 # number of ReadExReq MSHR miss cycles 831system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7770532000 # number of ReadExReq MSHR miss cycles 832system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1160467500 # number of ReadCleanReq MSHR miss cycles 833system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1160467500 # number of ReadCleanReq MSHR miss cycles 834system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17006826000 # number of ReadSharedReq MSHR miss cycles 835system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17006826000 # number of ReadSharedReq MSHR miss cycles 836system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1160467500 # number of demand (read+write) MSHR miss cycles 837system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24777358000 # number of demand (read+write) MSHR miss cycles 838system.cpu.l2cache.demand_mshr_miss_latency::total 25937825500 # number of demand (read+write) MSHR miss cycles 839system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1160467500 # number of overall MSHR miss cycles 840system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24777358000 # number of overall MSHR miss cycles 841system.cpu.l2cache.overall_mshr_miss_latency::total 25937825500 # number of overall MSHR miss cycles 842system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364748500 # number of ReadReq MSHR uncacheable cycles 843system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364748500 # number of ReadReq MSHR uncacheable cycles 844system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1931469000 # number of WriteReq MSHR uncacheable cycles 845system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1931469000 # number of WriteReq MSHR uncacheable cycles 846system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3296217500 # number of overall MSHR uncacheable cycles 847system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3296217500 # number of overall MSHR uncacheable cycles | 821system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 822system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 823system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9620 # number of WriteReq MSHR uncacheable 824system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9620 # number of WriteReq MSHR uncacheable 825system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16550 # number of overall MSHR uncacheable misses 826system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16550 # number of overall MSHR uncacheable misses 827system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 453499 # number of UpgradeReq MSHR miss cycles 828system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 453499 # number of UpgradeReq MSHR miss cycles 829system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7758089500 # number of ReadExReq MSHR miss cycles 830system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7758089500 # number of ReadExReq MSHR miss cycles 831system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1150653000 # number of ReadCleanReq MSHR miss cycles 832system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1150653000 # number of ReadCleanReq MSHR miss cycles 833system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17010167000 # number of ReadSharedReq MSHR miss cycles 834system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17010167000 # number of ReadSharedReq MSHR miss cycles 835system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1150653000 # number of demand (read+write) MSHR miss cycles 836system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24768256500 # number of demand (read+write) MSHR miss cycles 837system.cpu.l2cache.demand_mshr_miss_latency::total 25918909500 # number of demand (read+write) MSHR miss cycles 838system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1150653000 # number of overall MSHR miss cycles 839system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24768256500 # number of overall MSHR miss cycles 840system.cpu.l2cache.overall_mshr_miss_latency::total 25918909500 # number of overall MSHR miss cycles 841system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363977000 # number of ReadReq MSHR uncacheable cycles 842system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363977000 # number of ReadReq MSHR uncacheable cycles 843system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1930958000 # number of WriteReq MSHR uncacheable cycles 844system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1930958000 # number of WriteReq MSHR uncacheable cycles 845system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3294935000 # number of overall MSHR uncacheable cycles 846system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3294935000 # number of overall MSHR uncacheable cycles |
| 848system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 849system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 847system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 848system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 850system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses 851system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses 852system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382955 # mshr miss rate for ReadExReq accesses 853system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382955 # mshr miss rate for ReadExReq accesses 854system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for ReadCleanReq accesses 855system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011238 # mshr miss rate for ReadCleanReq accesses 856system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249327 # mshr miss rate for ReadSharedReq accesses 857system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249327 # mshr miss rate for ReadSharedReq accesses 858system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for demand accesses 859system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for demand accesses 860system.cpu.l2cache.demand_mshr_miss_rate::total 0.141868 # mshr miss rate for demand accesses 861system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for overall accesses 862system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for overall accesses 863system.cpu.l2cache.overall_mshr_miss_rate::total 0.141868 # mshr miss rate for overall accesses 864system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26937.500000 # average UpgradeReq mshr miss latency 865system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26937.500000 # average UpgradeReq mshr miss latency 866system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66680.385124 # average ReadExReq mshr miss latency 867system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66680.385124 # average ReadExReq mshr miss latency 868system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70747.271841 # average ReadCleanReq mshr miss latency 869system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70747.271841 # average ReadCleanReq mshr miss latency 870system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62483.975619 # average ReadSharedReq mshr miss latency 871system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62483.975619 # average ReadSharedReq mshr miss latency 872system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency 873system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency 874system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency 875system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency 876system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency 877system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency 878system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196819.800981 # average ReadReq mshr uncacheable latency 879system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196819.800981 # average ReadReq mshr uncacheable latency 880system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200755.534768 # average WriteReq mshr uncacheable latency 881system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200755.534768 # average WriteReq mshr uncacheable latency 882system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199107.067351 # average overall mshr uncacheable latency 883system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199107.067351 # average overall mshr uncacheable latency | 849system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses 850system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses 851system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382982 # mshr miss rate for ReadExReq accesses 852system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382982 # mshr miss rate for ReadExReq accesses 853system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for ReadCleanReq accesses 854system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011239 # mshr miss rate for ReadCleanReq accesses 855system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249303 # mshr miss rate for ReadSharedReq accesses 856system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249303 # mshr miss rate for ReadSharedReq accesses 857system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for demand accesses 858system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for demand accesses 859system.cpu.l2cache.demand_mshr_miss_rate::total 0.141862 # mshr miss rate for demand accesses 860system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for overall accesses 861system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for overall accesses 862system.cpu.l2cache.overall_mshr_miss_rate::total 0.141862 # mshr miss rate for overall accesses 863system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26676.411765 # average UpgradeReq mshr miss latency 864system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26676.411765 # average UpgradeReq mshr miss latency 865system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66567.901393 # average ReadExReq mshr miss latency 866system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66567.901393 # average ReadExReq mshr miss latency 867system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70136.108741 # average ReadCleanReq mshr miss latency 868system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70136.108741 # average ReadCleanReq mshr miss latency 869system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62499.235761 # average ReadSharedReq mshr miss latency 870system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62499.235761 # average ReadSharedReq mshr miss latency 871system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency 872system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency 873system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency 874system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency 875system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency 876system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency 877system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196822.077922 # average ReadReq mshr uncacheable latency 878system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196822.077922 # average ReadReq mshr uncacheable latency 879system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200723.284823 # average WriteReq mshr uncacheable latency 880system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200723.284823 # average WriteReq mshr uncacheable latency 881system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199089.728097 # average overall mshr uncacheable latency 882system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199089.728097 # average overall mshr uncacheable latency |
| 884system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 883system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 885system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution 886system.cpu.toL2Bus.trans_dist::ReadResp 2558426 # Transaction distribution 887system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution 888system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::Writeback 956270 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::CleanEvict 2277118 # Transaction distribution 891system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution 892system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution 893system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution 894system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution 895system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459696 # Transaction distribution 896system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091829 # Transaction distribution | 884system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 885system.cpu.toL2Bus.trans_dist::ReadResp 2558531 # Transaction distribution 886system.cpu.toL2Bus.trans_dist::WriteReq 9620 # Transaction distribution 887system.cpu.toL2Bus.trans_dist::WriteResp 9620 # Transaction distribution 888system.cpu.toL2Bus.trans_dist::Writeback 956362 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::CleanEvict 2277135 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution 891system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution 892system.cpu.toL2Bus.trans_dist::ReadExReq 304307 # Transaction distribution 893system.cpu.toL2Bus.trans_dist::ReadExResp 304307 # Transaction distribution 894system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459755 # Transaction distribution 895system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091879 # Transaction distribution |
| 897system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution 898system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution | 896system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution 897system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| 899system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377747 # Packet count per connected master and slave (bytes) 900system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219297 # Packet count per connected master and slave (bytes) 901system.cpu.toL2Bus.pkt_count::total 8597044 # Packet count per connected master and slave (bytes) 902system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93416704 # Cumulative packet size per connected master and slave (bytes) 903system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041221 # Cumulative packet size per connected master and slave (bytes) 904system.cpu.toL2Bus.pkt_size::total 236457925 # Cumulative packet size per connected master and slave (bytes) 905system.cpu.toL2Bus.snoops 422839 # Total snoops (count) 906system.cpu.toL2Bus.snoop_fanout::samples 6149292 # Request fanout histogram | 898system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377903 # Packet count per connected master and slave (bytes) 899system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219455 # Packet count per connected master and slave (bytes) 900system.cpu.toL2Bus.pkt_count::total 8597358 # Packet count per connected master and slave (bytes) 901system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93420352 # Cumulative packet size per connected master and slave (bytes) 902system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143049956 # Cumulative packet size per connected master and slave (bytes) 903system.cpu.toL2Bus.pkt_size::total 236470308 # Cumulative packet size per connected master and slave (bytes) 904system.cpu.toL2Bus.snoops 422854 # Total snoops (count) 905system.cpu.toL2Bus.snoop_fanout::samples 6149527 # Request fanout histogram |
| 907system.cpu.toL2Bus.snoop_fanout::mean 1.068727 # Request fanout histogram | 906system.cpu.toL2Bus.snoop_fanout::mean 1.068727 # Request fanout histogram |
| 908system.cpu.toL2Bus.snoop_fanout::stdev 0.252990 # Request fanout histogram | 907system.cpu.toL2Bus.snoop_fanout::stdev 0.252989 # Request fanout histogram |
| 909system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 910system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 908system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 911system.cpu.toL2Bus.snoop_fanout::1 5726669 93.13% 93.13% # Request fanout histogram 912system.cpu.toL2Bus.snoop_fanout::2 422623 6.87% 100.00% # Request fanout histogram | 910system.cpu.toL2Bus.snoop_fanout::1 5726891 93.13% 93.13% # Request fanout histogram 911system.cpu.toL2Bus.snoop_fanout::2 422636 6.87% 100.00% # Request fanout histogram |
| 913system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 914system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 915system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 912system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 913system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 914system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 916system.cpu.toL2Bus.snoop_fanout::total 6149292 # Request fanout histogram 917system.cpu.toL2Bus.reqLayer0.occupancy 3706373000 # Layer occupancy (ticks) | 915system.cpu.toL2Bus.snoop_fanout::total 6149527 # Request fanout histogram 916system.cpu.toL2Bus.reqLayer0.occupancy 3706565999 # Layer occupancy (ticks) |
| 918system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 919system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 920system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 917system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 918system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 919system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 921system.cpu.toL2Bus.respLayer0.occupancy 2189771045 # Layer occupancy (ticks) | 920system.cpu.toL2Bus.respLayer0.occupancy 2189850563 # Layer occupancy (ticks) |
| 922system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 921system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 923system.cpu.toL2Bus.respLayer1.occupancy 2105677995 # Layer occupancy (ticks) | 922system.cpu.toL2Bus.respLayer1.occupancy 2105755497 # Layer occupancy (ticks) |
| 924system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 925system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 926system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 927system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 928system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 929system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 930system.disk0.dma_write_txs 395 # Number of DMA write transactions. 931system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 932system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 933system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 934system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 935system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 936system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 923system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 924system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 925system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 926system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 927system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 928system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 929system.disk0.dma_write_txs 395 # Number of DMA write transactions. 930system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 931system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 932system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 933system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 934system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 935system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 937system.iobus.trans_dist::ReadReq 7107 # Transaction distribution 938system.iobus.trans_dist::ReadResp 7107 # Transaction distribution 939system.iobus.trans_dist::WriteReq 51173 # Transaction distribution 940system.iobus.trans_dist::WriteResp 51173 # Transaction distribution 941system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5104 # Packet count per connected master and slave (bytes) | 936system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 937system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 938system.iobus.trans_dist::WriteReq 51172 # Transaction distribution 939system.iobus.trans_dist::WriteResp 51172 # Transaction distribution 940system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5096 # Packet count per connected master and slave (bytes) |
| 942system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 943system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 944system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 945system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 946system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 947system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) | 941system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 942system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 943system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 944system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 945system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 946system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) |
| 948system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) | 947system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) |
| 949system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 950system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 951system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 952system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 948system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 949system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 950system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 951system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 953system.iobus.pkt_count_system.bridge.master::total 33110 # Packet count per connected master and slave (bytes) | 952system.iobus.pkt_count_system.bridge.master::total 33100 # Packet count per connected master and slave (bytes) |
| 954system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 955system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) | 953system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 954system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) |
| 956system.iobus.pkt_count::total 116560 # Packet count per connected master and slave (bytes) 957system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20416 # Cumulative packet size per connected master and slave (bytes) | 955system.iobus.pkt_count::total 116550 # Packet count per connected master and slave (bytes) 956system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20384 # Cumulative packet size per connected master and slave (bytes) |
| 958system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 959system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 960system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 961system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 962system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 963system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) | 957system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 958system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 959system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 960system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 961system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 962system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) |
| 964system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) | 963system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) |
| 965system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 966system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 967system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 968system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 964system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 965system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 966system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 967system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 969system.iobus.pkt_size_system.bridge.master::total 44357 # Cumulative packet size per connected master and slave (bytes) | 968system.iobus.pkt_size_system.bridge.master::total 44324 # Cumulative packet size per connected master and slave (bytes) |
| 970system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 971system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) | 969system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 970system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) |
| 972system.iobus.pkt_size::total 2705965 # Cumulative packet size per connected master and slave (bytes) 973system.iobus.reqLayer0.occupancy 4712000 # Layer occupancy (ticks) | 971system.iobus.pkt_size::total 2705932 # Cumulative packet size per connected master and slave (bytes) 972system.iobus.reqLayer0.occupancy 4707000 # Layer occupancy (ticks) |
| 974system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 975system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 976system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 977system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 978system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 979system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 980system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 981system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 982system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 983system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 984system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 985system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 986system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 973system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 974system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 975system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 976system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 977system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 978system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 979system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 980system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 981system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 982system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 983system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 984system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 985system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 987system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) | 986system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) |
| 988system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 989system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 990system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 991system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 992system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 993system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 994system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 987system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 988system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 989system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 990system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 991system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 992system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 993system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 995system.iobus.reqLayer29.occupancy 216063756 # Layer occupancy (ticks) | 994system.iobus.reqLayer29.occupancy 216043265 # Layer occupancy (ticks) |
| 996system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 997system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 998system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | 995system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 996system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 997system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) |
| 999system.iobus.respLayer0.occupancy 23489000 # Layer occupancy (ticks) | 998system.iobus.respLayer0.occupancy 23480000 # Layer occupancy (ticks) |
| 1000system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1001system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1002system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1003system.iocache.tags.replacements 41685 # number of replacements | 999system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1000system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1001system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1002system.iocache.tags.replacements 41685 # number of replacements |
| 1004system.iocache.tags.tagsinuse 1.294607 # Cycle average of tags in use | 1003system.iocache.tags.tagsinuse 1.302220 # Cycle average of tags in use |
| 1005system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1006system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1007system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1004system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1005system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1006system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1008system.iocache.tags.warmup_cycle 1729988854000 # Cycle when the warmup percentage was hit. 1009system.iocache.tags.occ_blocks::tsunami.ide 1.294607 # Average occupied blocks per requestor 1010system.iocache.tags.occ_percent::tsunami.ide 0.080913 # Average percentage of cache occupancy 1011system.iocache.tags.occ_percent::total 0.080913 # Average percentage of cache occupancy | 1007system.iocache.tags.warmup_cycle 1729987199000 # Cycle when the warmup percentage was hit. 1008system.iocache.tags.occ_blocks::tsunami.ide 1.302220 # Average occupied blocks per requestor 1009system.iocache.tags.occ_percent::tsunami.ide 0.081389 # Average percentage of cache occupancy 1010system.iocache.tags.occ_percent::total 0.081389 # Average percentage of cache occupancy |
| 1012system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1013system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1014system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1015system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1016system.iocache.tags.data_accesses 375525 # Number of data accesses 1017system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1018system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1019system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1020system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1021system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1022system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1023system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1024system.iocache.overall_misses::total 173 # number of overall misses 1025system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles 1026system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles | 1011system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1012system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1013system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1014system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1015system.iocache.tags.data_accesses 375525 # Number of data accesses 1016system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1017system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1018system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1019system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1020system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1021system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1022system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1023system.iocache.overall_misses::total 173 # number of overall misses 1024system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles 1025system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles |
| 1027system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907200873 # number of WriteLineReq miss cycles 1028system.iocache.WriteLineReq_miss_latency::total 4907200873 # number of WriteLineReq miss cycles | 1026system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908791382 # number of WriteLineReq miss cycles 1027system.iocache.WriteLineReq_miss_latency::total 4908791382 # number of WriteLineReq miss cycles |
| 1029system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles 1030system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles 1031system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles 1032system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles 1033system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1034system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1035system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1036system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 1043system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1044system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1045system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1046system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1047system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1048system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1049system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency 1050system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency | 1028system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles 1029system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles 1030system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles 1031system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles 1032system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1033system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1034system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1035system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 1042system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1043system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1044system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1045system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1046system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1047system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1048system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency 1049system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency |
| 1051system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118097.826170 # average WriteLineReq miss latency 1052system.iocache.WriteLineReq_avg_miss_latency::total 118097.826170 # average WriteLineReq miss latency | 1050system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118136.103725 # average WriteLineReq miss latency 1051system.iocache.WriteLineReq_avg_miss_latency::total 118136.103725 # average WriteLineReq miss latency |
| 1053system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency 1054system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency 1055system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency 1056system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency | 1052system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency 1053system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency 1054system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency 1055system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency |
| 1057system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 1056system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked |
| 1058system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1057system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1059system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked | 1058system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked |
| 1060system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1059system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1061system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 1060system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked |
| 1062system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1063system.iocache.fast_writes 0 # number of fast writes performed 1064system.iocache.cache_copies 0 # number of cache copies performed 1065system.iocache.writebacks::writebacks 41512 # number of writebacks 1066system.iocache.writebacks::total 41512 # number of writebacks 1067system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1068system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1069system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1070system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1071system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1072system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1073system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1074system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1075system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles 1076system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles | 1061system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1062system.iocache.fast_writes 0 # number of fast writes performed 1063system.iocache.cache_copies 0 # number of cache copies performed 1064system.iocache.writebacks::writebacks 41512 # number of writebacks 1065system.iocache.writebacks::total 41512 # number of writebacks 1066system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1067system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1068system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1069system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1070system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1071system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1072system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1073system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1074system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles 1075system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles |
| 1077system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829600873 # number of WriteLineReq MSHR miss cycles 1078system.iocache.WriteLineReq_mshr_miss_latency::total 2829600873 # number of WriteLineReq MSHR miss cycles | 1076system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831191382 # number of WriteLineReq MSHR miss cycles 1077system.iocache.WriteLineReq_mshr_miss_latency::total 2831191382 # number of WriteLineReq MSHR miss cycles |
| 1079system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles 1080system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles 1081system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles 1082system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles 1083system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1084system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1085system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1086system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1087system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1088system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1089system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1090system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1091system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency 1092system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency | 1078system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles 1079system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles 1080system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles 1081system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles 1082system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1083system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1084system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1085system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1086system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1087system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1088system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1089system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1090system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency 1091system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency |
| 1093system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68097.826170 # average WriteLineReq mshr miss latency 1094system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68097.826170 # average WriteLineReq mshr miss latency | 1092system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68136.103725 # average WriteLineReq mshr miss latency 1093system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68136.103725 # average WriteLineReq mshr miss latency |
| 1095system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency 1096system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency 1097system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency 1098system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency 1099system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1094system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency 1095system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency 1096system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency 1097system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency 1098system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1100system.membus.trans_dist::ReadReq 6934 # Transaction distribution 1101system.membus.trans_dist::ReadResp 295673 # Transaction distribution 1102system.membus.trans_dist::WriteReq 9621 # Transaction distribution 1103system.membus.trans_dist::WriteResp 9621 # Transaction distribution 1104system.membus.trans_dist::Writeback 118025 # Transaction distribution 1105system.membus.trans_dist::CleanEvict 262175 # Transaction distribution 1106system.membus.trans_dist::UpgradeReq 156 # Transaction distribution 1107system.membus.trans_dist::UpgradeResp 156 # Transaction distribution 1108system.membus.trans_dist::ReadExReq 116394 # Transaction distribution 1109system.membus.trans_dist::ReadExResp 116394 # Transaction distribution 1110system.membus.trans_dist::ReadSharedReq 288755 # Transaction distribution | 1099system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1100system.membus.trans_dist::ReadResp 295659 # Transaction distribution 1101system.membus.trans_dist::WriteReq 9620 # Transaction distribution 1102system.membus.trans_dist::WriteResp 9620 # Transaction distribution 1103system.membus.trans_dist::Writeback 118023 # Transaction distribution 1104system.membus.trans_dist::CleanEvict 262178 # Transaction distribution 1105system.membus.trans_dist::UpgradeReq 157 # Transaction distribution 1106system.membus.trans_dist::UpgradeResp 157 # Transaction distribution 1107system.membus.trans_dist::ReadExReq 116404 # Transaction distribution 1108system.membus.trans_dist::ReadExResp 116404 # Transaction distribution 1109system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution |
| 1111system.membus.trans_dist::BadAddressError 16 # Transaction distribution 1112system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1113system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution | 1110system.membus.trans_dist::BadAddressError 16 # Transaction distribution 1111system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1112system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution |
| 1114system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33110 # Packet count per connected master and slave (bytes) 1115system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148632 # Packet count per connected master and slave (bytes) | 1113system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33100 # Packet count per connected master and slave (bytes) 1114system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148635 # Packet count per connected master and slave (bytes) |
| 1116system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) | 1115system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) |
| 1117system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181774 # Packet count per connected master and slave (bytes) | 1116system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181767 # Packet count per connected master and slave (bytes) |
| 1118system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) 1119system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) | 1117system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) 1118system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) |
| 1120system.membus.pkt_count::total 1306591 # Packet count per connected master and slave (bytes) 1121system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44357 # Cumulative packet size per connected master and slave (bytes) 1122system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796800 # Cumulative packet size per connected master and slave (bytes) 1123system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30841157 # Cumulative packet size per connected master and slave (bytes) | 1119system.membus.pkt_count::total 1306584 # Packet count per connected master and slave (bytes) 1120system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44324 # Cumulative packet size per connected master and slave (bytes) 1121system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796672 # Cumulative packet size per connected master and slave (bytes) 1122system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30840996 # Cumulative packet size per connected master and slave (bytes) |
| 1124system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1125system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) | 1123system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1124system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) |
| 1126system.membus.pkt_size::total 33498885 # Cumulative packet size per connected master and slave (bytes) | 1125system.membus.pkt_size::total 33498724 # Cumulative packet size per connected master and slave (bytes) |
| 1127system.membus.snoops 433 # Total snoops (count) | 1126system.membus.snoops 433 # Total snoops (count) |
| 1128system.membus.snoop_fanout::samples 843789 # Request fanout histogram | 1127system.membus.snoop_fanout::samples 843798 # Request fanout histogram |
| 1129system.membus.snoop_fanout::mean 1 # Request fanout histogram 1130system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1131system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1132system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1128system.membus.snoop_fanout::mean 1 # Request fanout histogram 1129system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1130system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1131system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1133system.membus.snoop_fanout::1 843789 100.00% 100.00% # Request fanout histogram | 1132system.membus.snoop_fanout::1 843798 100.00% 100.00% # Request fanout histogram |
| 1134system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1135system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1136system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1137system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1133system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1134system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1135system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1136system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1138system.membus.snoop_fanout::total 843789 # Request fanout histogram 1139system.membus.reqLayer0.occupancy 29576000 # Layer occupancy (ticks) | 1137system.membus.snoop_fanout::total 843798 # Request fanout histogram 1138system.membus.reqLayer0.occupancy 29290000 # Layer occupancy (ticks) |
| 1140system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1139system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1141system.membus.reqLayer1.occupancy 1318697936 # Layer occupancy (ticks) | 1140system.membus.reqLayer1.occupancy 1318757186 # Layer occupancy (ticks) |
| 1142system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1143system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) 1144system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1141system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1142system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) 1143system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1145system.membus.respLayer1.occupancy 2160007596 # Layer occupancy (ticks) | 1144system.membus.respLayer1.occupancy 2160035845 # Layer occupancy (ticks) |
| 1146system.membus.respLayer1.utilization 0.1 # Layer utilization (%) | 1145system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1147system.membus.respLayer2.occupancy 72031934 # Layer occupancy (ticks) | 1146system.membus.respLayer2.occupancy 72019946 # Layer occupancy (ticks) |
| 1148system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1149system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1150system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1151system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1152system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1153system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1154system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1155system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- | 1147system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1148system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1149system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1150system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1151system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1152system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1153system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1154system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- |