| stats.txt (10827:7f5467f2f8b8) | stats.txt (10852:5b58b4cccfd7) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.887184 # Number of seconds simulated 4sim_ticks 1887184463000 # Number of ticks simulated 5final_tick 1887184463000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.887179 # Number of seconds simulated 4sim_ticks 1887179292000 # Number of ticks simulated 5final_tick 1887179292000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 272052 # Simulator instruction rate (inst/s) 8host_op_rate 272052 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9147074399 # Simulator tick rate (ticks/s) 10host_mem_usage 373996 # Number of bytes of host memory used 11host_seconds 206.32 # Real time elapsed on the host 12sim_insts 56128524 # Number of instructions simulated 13sim_ops 56128524 # Number of ops (including micro ops) simulated | 7host_inst_rate 271909 # Simulator instruction rate (inst/s) 8host_op_rate 271909 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9140545464 # Simulator tick rate (ticks/s) 10host_mem_usage 373988 # Number of bytes of host memory used 11host_seconds 206.46 # Real time elapsed on the host 12sim_insts 56138893 # Number of instructions simulated 13sim_ops 56138893 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 1052352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 1052544 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24858944 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 25913536 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1052352 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1052352 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7558400 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7558400 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 16443 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 25912448 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7556224 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7556224 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 16446 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388421 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::total 404899 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 118100 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 118100 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 557631 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13173182 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.num_reads::total 404882 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 118066 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 118066 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 557734 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13172540 # Total read bandwidth from this memory (bytes/s) |
| 32system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) | 32system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) |
| 33system.physmem.bw_read::total 13731321 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 557631 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 557631 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4005120 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4005120 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4005120 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 557631 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13173182 # Total bandwidth to/from this memory (bytes/s) | 33system.physmem.bw_read::total 13730782 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 557734 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 557734 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4003978 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4003978 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4003978 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 557734 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13172540 # Total bandwidth to/from this memory (bytes/s) |
| 41system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) | 41system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) |
| 42system.physmem.bw_total::total 17736441 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 404899 # Number of read requests accepted 44system.physmem.writeReqs 159652 # Number of write requests accepted 45system.physmem.readBursts 404899 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 159652 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25907328 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue 49system.physmem.bytesWritten 8555840 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25913536 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10217728 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 25937 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 159 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25492 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25732 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25844 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25788 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25096 # Per bank write bursts 60system.physmem.perBankRdBursts::5 25019 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24724 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24556 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25196 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25300 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25394 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24993 # Per bank write bursts | 42system.physmem.bw_total::total 17734760 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 404882 # Number of read requests accepted 44system.physmem.writeReqs 159618 # Number of write requests accepted 45system.physmem.readBursts 404882 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 159618 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25905920 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue 49system.physmem.bytesWritten 8528320 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25912448 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10215552 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 26335 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25487 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25681 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25706 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25753 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25164 # Per bank write bursts 60system.physmem.perBankRdBursts::5 25107 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24789 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24544 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25200 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25299 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25393 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24991 # Per bank write bursts |
| 67system.physmem.perBankRdBursts::12 24525 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25570 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25834 # Per bank write bursts | 67system.physmem.perBankRdBursts::12 24525 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25570 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25834 # Per bank write bursts |
| 70system.physmem.perBankRdBursts::15 25739 # Per bank write bursts 71system.physmem.perBankWrBursts::0 8904 # Per bank write bursts 72system.physmem.perBankWrBursts::1 8550 # Per bank write bursts 73system.physmem.perBankWrBursts::2 9134 # Per bank write bursts 74system.physmem.perBankWrBursts::3 8817 # Per bank write bursts 75system.physmem.perBankWrBursts::4 8179 # Per bank write bursts 76system.physmem.perBankWrBursts::5 8016 # Per bank write bursts 77system.physmem.perBankWrBursts::6 7555 # Per bank write bursts 78system.physmem.perBankWrBursts::7 7380 # Per bank write bursts 79system.physmem.perBankWrBursts::8 8271 # Per bank write bursts 80system.physmem.perBankWrBursts::9 7751 # Per bank write bursts 81system.physmem.perBankWrBursts::10 8147 # Per bank write bursts 82system.physmem.perBankWrBursts::11 7871 # Per bank write bursts 83system.physmem.perBankWrBursts::12 8181 # Per bank write bursts 84system.physmem.perBankWrBursts::13 9046 # Per bank write bursts 85system.physmem.perBankWrBursts::14 9003 # Per bank write bursts 86system.physmem.perBankWrBursts::15 8880 # Per bank write bursts | 70system.physmem.perBankRdBursts::15 25737 # Per bank write bursts 71system.physmem.perBankWrBursts::0 8901 # Per bank write bursts 72system.physmem.perBankWrBursts::1 8465 # Per bank write bursts 73system.physmem.perBankWrBursts::2 9022 # Per bank write bursts 74system.physmem.perBankWrBursts::3 8725 # Per bank write bursts 75system.physmem.perBankWrBursts::4 8062 # Per bank write bursts 76system.physmem.perBankWrBursts::5 8096 # Per bank write bursts 77system.physmem.perBankWrBursts::6 7614 # Per bank write bursts 78system.physmem.perBankWrBursts::7 7482 # Per bank write bursts 79system.physmem.perBankWrBursts::8 8269 # Per bank write bursts 80system.physmem.perBankWrBursts::9 7671 # Per bank write bursts 81system.physmem.perBankWrBursts::10 8104 # Per bank write bursts 82system.physmem.perBankWrBursts::11 7830 # Per bank write bursts 83system.physmem.perBankWrBursts::12 8200 # Per bank write bursts 84system.physmem.perBankWrBursts::13 9100 # Per bank write bursts 85system.physmem.perBankWrBursts::14 8920 # Per bank write bursts 86system.physmem.perBankWrBursts::15 8794 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 88system.physmem.numWrRetry 48 # Number of times write queue was full causing retry 89system.physmem.totGap 1887175688500 # Total gap between requests | 88system.physmem.numWrRetry 50 # Number of times write queue was full causing retry 89system.physmem.totGap 1887170570500 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 404899 # Read request sizes (log2) | 96system.physmem.readPktSize::6 404882 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 159652 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 402512 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 2208 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 159618 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 402496 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 2204 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see |
| 107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 1116 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1878 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 5779 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 5566 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 5580 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 5702 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5645 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5477 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5437 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 5641 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 5825 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 6756 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 6161 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6363 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 7635 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6502 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6461 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5991 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 1224 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 780 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 1179 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 1384 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 1265 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 883 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1555 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 1873 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1560 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1827 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1983 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1921 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 2157 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 2541 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 2774 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 2169 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 1666 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 1329 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 1241 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 764 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 299 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 261 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 147 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 161 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 64790 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 531.921099 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 325.032687 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 415.479352 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 14695 22.68% 22.68% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10956 16.91% 39.59% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 5460 8.43% 48.02% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3096 4.78% 52.80% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2482 3.83% 56.63% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1882 2.90% 59.53% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1491 2.30% 61.83% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1429 2.21% 64.04% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 23299 35.96% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 64790 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4900 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 82.608776 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 3017.174786 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 4897 99.94% 99.94% # Reads before turning the bus around for writes | 151system.physmem.wrQLenPdf::15 1093 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1663 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 5882 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 5419 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 5741 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 5593 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5366 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5405 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5456 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 5673 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 5897 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 6995 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5801 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6757 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 7486 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6471 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6260 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5953 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 1130 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 667 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 1335 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 1371 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 1390 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 945 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1888 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 1841 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1587 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1811 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1859 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1873 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 1976 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 2613 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 2770 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 2154 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 1746 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 1261 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 1211 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 744 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 478 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 307 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 228 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 258 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 181 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 167 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 153 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 175 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 96 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 64763 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 531.696185 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 324.957517 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 415.417041 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 14664 22.64% 22.64% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 11016 17.01% 39.65% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 5432 8.39% 48.04% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3093 4.78% 52.82% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2464 3.80% 56.62% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1908 2.95% 59.57% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1486 2.29% 61.86% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1430 2.21% 64.07% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 23270 35.93% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 64763 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4906 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 82.503669 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 3015.330482 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 4903 99.94% 99.94% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::total 4900 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 4900 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 27.282653 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 18.334547 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 63.863816 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::0-31 4662 95.14% 95.14% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-63 56 1.14% 96.29% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::64-95 12 0.24% 96.53% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::96-127 6 0.12% 96.65% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::128-159 26 0.53% 97.18% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::160-191 25 0.51% 97.69% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::192-223 16 0.33% 98.02% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::224-255 3 0.06% 98.08% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::256-287 4 0.08% 98.16% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::288-319 8 0.16% 98.33% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::320-351 21 0.43% 98.76% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::352-383 20 0.41% 99.16% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::384-415 2 0.04% 99.20% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::448-479 6 0.12% 99.33% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::480-511 7 0.14% 99.47% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::512-543 9 0.18% 99.65% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::544-575 6 0.12% 99.78% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::672-703 3 0.06% 99.84% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::704-735 7 0.14% 99.98% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::1088-1119 1 0.02% 100.00% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::total 4900 # Writes before turning the bus around for reads 247system.physmem.totQLat 2145936500 # Total ticks spent queuing 248system.physmem.totMemAccLat 9735974000 # Total ticks spent from burst creation until serviced by the DRAM 249system.physmem.totBusLat 2024010000 # Total ticks spent in databus transfers 250system.physmem.avgQLat 5301.20 # Average queueing delay per DRAM burst | 221system.physmem.rdPerTurnAround::total 4906 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 4906 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 27.161639 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 18.352681 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 61.394400 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-31 4666 95.11% 95.11% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-47 49 1.00% 96.11% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::48-63 4 0.08% 96.19% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::64-79 5 0.10% 96.29% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::80-95 7 0.14% 96.43% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::96-111 1 0.02% 96.45% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::112-127 2 0.04% 96.49% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::128-143 7 0.14% 96.64% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::144-159 21 0.43% 97.06% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::160-175 22 0.45% 97.51% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::176-191 9 0.18% 97.70% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::192-207 10 0.20% 97.90% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::208-223 3 0.06% 97.96% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::224-239 2 0.04% 98.00% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::240-255 2 0.04% 98.04% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::256-271 3 0.06% 98.10% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::272-287 2 0.04% 98.15% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::288-303 2 0.04% 98.19% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::304-319 3 0.06% 98.25% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::320-335 19 0.39% 98.63% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::336-351 9 0.18% 98.82% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::352-367 5 0.10% 98.92% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::368-383 13 0.26% 99.18% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::384-399 3 0.06% 99.25% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::400-415 1 0.02% 99.27% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::432-447 1 0.02% 99.29% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::448-463 3 0.06% 99.35% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::464-479 5 0.10% 99.45% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::480-495 3 0.06% 99.51% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::496-511 8 0.16% 99.67% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::512-527 2 0.04% 99.71% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::528-543 1 0.02% 99.74% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::544-559 3 0.06% 99.80% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::560-575 1 0.02% 99.82% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::656-671 1 0.02% 99.84% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::672-687 3 0.06% 99.90% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::704-719 1 0.02% 99.92% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::816-831 1 0.02% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::total 4906 # Writes before turning the bus around for reads 266system.physmem.totQLat 2145475500 # Total ticks spent queuing 267system.physmem.totMemAccLat 9735100500 # Total ticks spent from burst creation until serviced by the DRAM 268system.physmem.totBusLat 2023900000 # Total ticks spent in databus transfers 269system.physmem.avgQLat 5300.35 # Average queueing delay per DRAM burst |
| 251system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 252system.physmem.avgMemAccLat 24051.20 # Average memory access latency per DRAM burst | 271system.physmem.avgMemAccLat 24050.35 # Average memory access latency per DRAM burst |
| 253system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s | 272system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s |
| 254system.physmem.avgWrBW 4.53 # Average achieved write bandwidth in MiByte/s | 273system.physmem.avgWrBW 4.52 # Average achieved write bandwidth in MiByte/s |
| 255system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s 256system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s 257system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 258system.physmem.busUtil 0.14 # Data bus utilization in percentage 259system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 260system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes 261system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 274system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s 275system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 0.14 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes 280system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 262system.physmem.avgWrQLen 25.13 # Average write queue length when enqueuing 263system.physmem.readRowHits 363622 # Number of row buffer hits during reads 264system.physmem.writeRowHits 110075 # Number of row buffer hits during writes 265system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads 266system.physmem.writeRowHitRate 82.32 # Row buffer hit rate for writes 267system.physmem.avgGap 3342790.44 # Average gap between requests | 281system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing 282system.physmem.readRowHits 363650 # Number of row buffer hits during reads 283system.physmem.writeRowHits 109622 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate 82.25 # Row buffer hit rate for writes 286system.physmem.avgGap 3343083.38 # Average gap between requests |
| 268system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined | 287system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined |
| 269system.physmem_0.actEnergy 238979160 # Energy for activate commands per rank (pJ) 270system.physmem_0.preEnergy 130395375 # Energy for precharge commands per rank (pJ) 271system.physmem_0.readEnergy 1577557800 # Energy for read commands per rank (pJ) 272system.physmem_0.writeEnergy 431146800 # Energy for write commands per rank (pJ) | 288system.physmem_0.actEnergy 239016960 # Energy for activate commands per rank (pJ) 289system.physmem_0.preEnergy 130416000 # Energy for precharge commands per rank (pJ) 290system.physmem_0.readEnergy 1577401800 # Energy for read commands per rank (pJ) 291system.physmem_0.writeEnergy 430058160 # Energy for write commands per rank (pJ) |
| 273system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) | 292system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) |
| 274system.physmem_0.actBackEnergy 60577818750 # Energy for active background per rank (pJ) 275system.physmem_0.preBackEnergy 1079167773000 # Energy for precharge background per rank (pJ) 276system.physmem_0.totalEnergy 1265384883765 # Total energy per rank (pJ) 277system.physmem_0.averagePower 670.517324 # Core power per rank (mW) 278system.physmem_0.memoryStateTime::IDLE 1795079851716 # Time in different power states | 293system.physmem_0.actBackEnergy 60604997490 # Energy for active background per rank (pJ) 294system.physmem_0.preBackEnergy 1079143932000 # Energy for precharge background per rank (pJ) 295system.physmem_0.totalEnergy 1265387035290 # Total energy per rank (pJ) 296system.physmem_0.averagePower 670.518464 # Core power per rank (mW) 297system.physmem_0.memoryStateTime::IDLE 1795039940480 # Time in different power states |
| 279system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states 280system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 298system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states 299system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 281system.physmem_0.memoryStateTime::ACT 29080199534 # Time in different power states | 300system.physmem_0.memoryStateTime::ACT 29120110770 # Time in different power states |
| 282system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 301system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 283system.physmem_1.actEnergy 250833240 # Energy for activate commands per rank (pJ) 284system.physmem_1.preEnergy 136863375 # Energy for precharge commands per rank (pJ) 285system.physmem_1.readEnergy 1579897800 # Energy for read commands per rank (pJ) 286system.physmem_1.writeEnergy 435132000 # Energy for write commands per rank (pJ) | 302system.physmem_1.actEnergy 250591320 # Energy for activate commands per rank (pJ) 303system.physmem_1.preEnergy 136731375 # Energy for precharge commands per rank (pJ) 304system.physmem_1.readEnergy 1579882200 # Energy for read commands per rank (pJ) 305system.physmem_1.writeEnergy 433434240 # Energy for write commands per rank (pJ) |
| 287system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) | 306system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) |
| 288system.physmem_1.actBackEnergy 61600331205 # Energy for active background per rank (pJ) 289system.physmem_1.preBackEnergy 1078270840500 # Energy for precharge background per rank (pJ) 290system.physmem_1.totalEnergy 1265535111000 # Total energy per rank (pJ) 291system.physmem_1.averagePower 670.596923 # Core power per rank (mW) 292system.physmem_1.memoryStateTime::IDLE 1793587329216 # Time in different power states | 307system.physmem_1.actBackEnergy 61665698520 # Energy for active background per rank (pJ) 308system.physmem_1.preBackEnergy 1078213500750 # Energy for precharge background per rank (pJ) 309system.physmem_1.totalEnergy 1265541051285 # Total energy per rank (pJ) 310system.physmem_1.averagePower 670.600071 # Core power per rank (mW) 311system.physmem_1.memoryStateTime::IDLE 1793490285480 # Time in different power states |
| 293system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states 294system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 312system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states 313system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 295system.physmem_1.memoryStateTime::ACT 30572735784 # Time in different power states | 314system.physmem_1.memoryStateTime::ACT 30669779520 # Time in different power states |
| 296system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 315system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 297system.cpu.branchPred.lookups 15007833 # Number of BP lookups 298system.cpu.branchPred.condPredicted 13016266 # Number of conditional branches predicted 299system.cpu.branchPred.condIncorrect 375462 # Number of conditional branches incorrect 300system.cpu.branchPred.BTBLookups 9968116 # Number of BTB lookups 301system.cpu.branchPred.BTBHits 5203851 # Number of BTB hits | 316system.cpu.branchPred.lookups 15009390 # Number of BP lookups 317system.cpu.branchPred.condPredicted 13017239 # Number of conditional branches predicted 318system.cpu.branchPred.condIncorrect 373223 # Number of conditional branches incorrect 319system.cpu.branchPred.BTBLookups 9937559 # Number of BTB lookups 320system.cpu.branchPred.BTBHits 5199343 # Number of BTB hits |
| 302system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 321system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 303system.cpu.branchPred.BTBHitPct 52.204960 # BTB Hit Percentage 304system.cpu.branchPred.usedRAS 809053 # Number of times the RAS was used to get a target. 305system.cpu.branchPred.RASInCorrect 32834 # Number of incorrect RAS predictions. | 322system.cpu.branchPred.BTBHitPct 52.320122 # BTB Hit Percentage 323system.cpu.branchPred.usedRAS 808599 # Number of times the RAS was used to get a target. 324system.cpu.branchPred.RASInCorrect 32086 # Number of incorrect RAS predictions. |
| 306system.cpu_clk_domain.clock 500 # Clock period in ticks 307system.cpu.dtb.fetch_hits 0 # ITB hits 308system.cpu.dtb.fetch_misses 0 # ITB misses 309system.cpu.dtb.fetch_acv 0 # ITB acv 310system.cpu.dtb.fetch_accesses 0 # ITB accesses | 325system.cpu_clk_domain.clock 500 # Clock period in ticks 326system.cpu.dtb.fetch_hits 0 # ITB hits 327system.cpu.dtb.fetch_misses 0 # ITB misses 328system.cpu.dtb.fetch_acv 0 # ITB acv 329system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 311system.cpu.dtb.read_hits 9242504 # DTB read hits 312system.cpu.dtb.read_misses 17824 # DTB read misses | 330system.cpu.dtb.read_hits 9244571 # DTB read hits 331system.cpu.dtb.read_misses 17796 # DTB read misses |
| 313system.cpu.dtb.read_acv 211 # DTB read access violations | 332system.cpu.dtb.read_acv 211 # DTB read access violations |
| 314system.cpu.dtb.read_accesses 766347 # DTB read accesses 315system.cpu.dtb.write_hits 6386002 # DTB write hits 316system.cpu.dtb.write_misses 2322 # DTB write misses 317system.cpu.dtb.write_acv 159 # DTB write access violations 318system.cpu.dtb.write_accesses 298454 # DTB write accesses 319system.cpu.dtb.data_hits 15628506 # DTB hits 320system.cpu.dtb.data_misses 20146 # DTB misses 321system.cpu.dtb.data_acv 370 # DTB access violations 322system.cpu.dtb.data_accesses 1064801 # DTB accesses 323system.cpu.itb.fetch_hits 4019475 # ITB hits 324system.cpu.itb.fetch_misses 6849 # ITB misses 325system.cpu.itb.fetch_acv 693 # ITB acv 326system.cpu.itb.fetch_accesses 4026324 # ITB accesses | 333system.cpu.dtb.read_accesses 766653 # DTB read accesses 334system.cpu.dtb.write_hits 6387559 # DTB write hits 335system.cpu.dtb.write_misses 2314 # DTB write misses 336system.cpu.dtb.write_acv 160 # DTB write access violations 337system.cpu.dtb.write_accesses 298430 # DTB write accesses 338system.cpu.dtb.data_hits 15632130 # DTB hits 339system.cpu.dtb.data_misses 20110 # DTB misses 340system.cpu.dtb.data_acv 371 # DTB access violations 341system.cpu.dtb.data_accesses 1065083 # DTB accesses 342system.cpu.itb.fetch_hits 4016391 # ITB hits 343system.cpu.itb.fetch_misses 6902 # ITB misses 344system.cpu.itb.fetch_acv 656 # ITB acv 345system.cpu.itb.fetch_accesses 4023293 # ITB accesses |
| 327system.cpu.itb.read_hits 0 # DTB read hits 328system.cpu.itb.read_misses 0 # DTB read misses 329system.cpu.itb.read_acv 0 # DTB read access violations 330system.cpu.itb.read_accesses 0 # DTB read accesses 331system.cpu.itb.write_hits 0 # DTB write hits 332system.cpu.itb.write_misses 0 # DTB write misses 333system.cpu.itb.write_acv 0 # DTB write access violations 334system.cpu.itb.write_accesses 0 # DTB write accesses 335system.cpu.itb.data_hits 0 # DTB hits 336system.cpu.itb.data_misses 0 # DTB misses 337system.cpu.itb.data_acv 0 # DTB access violations 338system.cpu.itb.data_accesses 0 # DTB accesses | 346system.cpu.itb.read_hits 0 # DTB read hits 347system.cpu.itb.read_misses 0 # DTB read misses 348system.cpu.itb.read_acv 0 # DTB read access violations 349system.cpu.itb.read_accesses 0 # DTB read accesses 350system.cpu.itb.write_hits 0 # DTB write hits 351system.cpu.itb.write_misses 0 # DTB write misses 352system.cpu.itb.write_acv 0 # DTB write access violations 353system.cpu.itb.write_accesses 0 # DTB write accesses 354system.cpu.itb.data_hits 0 # DTB hits 355system.cpu.itb.data_misses 0 # DTB misses 356system.cpu.itb.data_acv 0 # DTB access violations 357system.cpu.itb.data_accesses 0 # DTB accesses |
| 339system.cpu.numCycles 180833533 # number of cpu cycles simulated | 358system.cpu.numCycles 180739367 # number of cpu cycles simulated |
| 340system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 341system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 359system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 360system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 342system.cpu.committedInsts 56128524 # Number of instructions committed 343system.cpu.committedOps 56128524 # Number of ops (including micro ops) committed 344system.cpu.discardedOps 2493054 # Number of ops (including micro ops) which were discarded before commit 345system.cpu.numFetchSuspends 5493 # Number of times Execute suspended instruction fetching 346system.cpu.quiesceCycles 3593535393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 347system.cpu.cpi 3.221776 # CPI: cycles per instruction 348system.cpu.ipc 0.310388 # IPC: instructions per cycle | 361system.cpu.committedInsts 56138893 # Number of instructions committed 362system.cpu.committedOps 56138893 # Number of ops (including micro ops) committed 363system.cpu.discardedOps 2514465 # Number of ops (including micro ops) which were discarded before commit 364system.cpu.numFetchSuspends 5513 # Number of times Execute suspended instruction fetching 365system.cpu.quiesceCycles 3593619217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 366system.cpu.cpi 3.219504 # CPI: cycles per instruction 367system.cpu.ipc 0.310607 # IPC: instructions per cycle |
| 349system.cpu.kern.inst.arm 0 # number of arm instructions executed | 368system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 350system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 351system.cpu.kern.inst.hwrei 211489 # number of hwrei instructions executed 352system.cpu.kern.ipl_count::0 74799 40.94% 40.94% # number of times we switched to this ipl | 369system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed 370system.cpu.kern.inst.hwrei 211474 # number of hwrei instructions executed 371system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl |
| 353system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl 354system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl | 372system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl 373system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl |
| 355system.cpu.kern.ipl_count::31 105874 57.95% 100.00% # number of times we switched to this ipl 356system.cpu.kern.ipl_count::total 182705 # number of times we switched to this ipl 357system.cpu.kern.ipl_good::0 73432 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 374system.cpu.kern.ipl_count::31 105866 57.95% 100.00% # number of times we switched to this ipl 375system.cpu.kern.ipl_count::total 182688 # number of times we switched to this ipl 376system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 358system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 359system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl | 377system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 378system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl |
| 360system.cpu.kern.ipl_good::31 73432 49.32% 100.00% # number of times we switched to this ipl from a different ipl 361system.cpu.kern.ipl_good::total 148896 # number of times we switched to this ipl from a different ipl 362system.cpu.kern.ipl_ticks::0 1834551053500 97.21% 97.21% # number of cycles we spent at this ipl 363system.cpu.kern.ipl_ticks::21 80458000 0.00% 97.22% # number of cycles we spent at this ipl 364system.cpu.kern.ipl_ticks::22 676198500 0.04% 97.25% # number of cycles we spent at this ipl 365system.cpu.kern.ipl_ticks::31 51875765500 2.75% 100.00% # number of cycles we spent at this ipl 366system.cpu.kern.ipl_ticks::total 1887183475500 # number of cycles we spent at this ipl 367system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl | 379system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl 380system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl 381system.cpu.kern.ipl_ticks::0 1834553179500 97.21% 97.21% # number of cycles we spent at this ipl 382system.cpu.kern.ipl_ticks::21 80704500 0.00% 97.22% # number of cycles we spent at this ipl 383system.cpu.kern.ipl_ticks::22 676355500 0.04% 97.25% # number of cycles we spent at this ipl 384system.cpu.kern.ipl_ticks::31 51868058000 2.75% 100.00% # number of cycles we spent at this ipl 385system.cpu.kern.ipl_ticks::total 1887178297500 # number of cycles we spent at this ipl 386system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl |
| 368system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 369system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 387system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 388system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 370system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl 371system.cpu.kern.ipl_used::total 0.814953 # fraction of swpipl calls that actually changed the ipl | 389system.cpu.kern.ipl_used::31 0.693547 # fraction of swpipl calls that actually changed the ipl 390system.cpu.kern.ipl_used::total 0.814930 # fraction of swpipl calls that actually changed the ipl |
| 372system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 373system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 374system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 375system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 376system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 377system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 378system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 379system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 399system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 400system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 401system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 402system.cpu.kern.syscall::total 326 # number of syscalls executed 403system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 404system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 405system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 406system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 391system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 392system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 393system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 394system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 395system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 396system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 397system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 398system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 418system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 419system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 420system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 421system.cpu.kern.syscall::total 326 # number of syscalls executed 422system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 423system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 424system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 425system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 407system.cpu.kern.callpal::swpctx 4170 2.17% 2.17% # number of callpals executed | 426system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed |
| 408system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 409system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 427system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 428system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 410system.cpu.kern.callpal::swpipl 175546 91.23% 93.43% # number of callpals executed | 429system.cpu.kern.callpal::swpipl 175529 91.23% 93.43% # number of callpals executed |
| 411system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed | 430system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed |
| 412system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed | 431system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed |
| 413system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 414system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 415system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 416system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed 417system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 418system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 432system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 433system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 434system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 435system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed 436system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 437system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 419system.cpu.kern.callpal::total 192427 # number of callpals executed 420system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches | 438system.cpu.kern.callpal::total 192412 # number of callpals executed 439system.cpu.kern.mode_switch::kernel 5872 # number of protection mode switches |
| 421system.cpu.kern.mode_switch::user 1739 # number of protection mode switches | 440system.cpu.kern.mode_switch::user 1739 # number of protection mode switches |
| 422system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches 423system.cpu.kern.mode_good::kernel 1906 | 441system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches 442system.cpu.kern.mode_good::kernel 1907 |
| 424system.cpu.kern.mode_good::user 1739 | 443system.cpu.kern.mode_good::user 1739 |
| 425system.cpu.kern.mode_good::idle 167 426system.cpu.kern.mode_switch_good::kernel 0.324536 # fraction of useful protection mode switches | 444system.cpu.kern.mode_good::idle 168 445system.cpu.kern.mode_switch_good::kernel 0.324762 # fraction of useful protection mode switches |
| 427system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 446system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 428system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches 429system.cpu.kern.mode_switch_good::total 0.392949 # fraction of useful protection mode switches 430system.cpu.kern.mode_ticks::kernel 36591863000 1.94% 1.94% # number of ticks spent at the given mode 431system.cpu.kern.mode_ticks::user 4134622500 0.22% 2.16% # number of ticks spent at the given mode 432system.cpu.kern.mode_ticks::idle 1846456980000 97.84% 100.00% # number of ticks spent at the given mode 433system.cpu.kern.swap_context 4171 # number of times the context was actually changed 434system.cpu.tickCycles 84552243 # Number of cycles that the object actually ticked 435system.cpu.idleCycles 96281290 # Total number of cycles that the object has spent stopped 436system.cpu.dcache.tags.replacements 1395323 # number of replacements | 447system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches 448system.cpu.kern.mode_switch_good::total 0.393074 # fraction of useful protection mode switches 449system.cpu.kern.mode_ticks::kernel 36563872500 1.94% 1.94% # number of ticks spent at the given mode 450system.cpu.kern.mode_ticks::user 4128201000 0.22% 2.16% # number of ticks spent at the given mode 451system.cpu.kern.mode_ticks::idle 1846486214000 97.84% 100.00% # number of ticks spent at the given mode 452system.cpu.kern.swap_context 4173 # number of times the context was actually changed 453system.cpu.tickCycles 84425844 # Number of cycles that the object actually ticked 454system.cpu.idleCycles 96313523 # Total number of cycles that the object has spent stopped 455system.cpu.dcache.tags.replacements 1395605 # number of replacements |
| 437system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use | 456system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use |
| 438system.cpu.dcache.tags.total_refs 13774277 # Total number of references to valid blocks. 439system.cpu.dcache.tags.sampled_refs 1395835 # Sample count of references to valid blocks. 440system.cpu.dcache.tags.avg_refs 9.868127 # Average number of references to valid blocks. | 457system.cpu.dcache.tags.total_refs 13777018 # Total number of references to valid blocks. 458system.cpu.dcache.tags.sampled_refs 1396117 # Sample count of references to valid blocks. 459system.cpu.dcache.tags.avg_refs 9.868097 # Average number of references to valid blocks. |
| 441system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. 442system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor 443system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy 444system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy 445system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 446system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 447system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 449system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 460system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. 461system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor 462system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy 463system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy 464system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 465system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 466system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id 467system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 468system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 450system.cpu.dcache.tags.tag_accesses 63660728 # Number of tag accesses 451system.cpu.dcache.tags.data_accesses 63660728 # Number of data accesses 452system.cpu.dcache.ReadReq_hits::cpu.data 7815432 # number of ReadReq hits 453system.cpu.dcache.ReadReq_hits::total 7815432 # number of ReadReq hits 454system.cpu.dcache.WriteReq_hits::cpu.data 5576995 # number of WriteReq hits 455system.cpu.dcache.WriteReq_hits::total 5576995 # number of WriteReq hits 456system.cpu.dcache.LoadLockedReq_hits::cpu.data 182818 # number of LoadLockedReq hits 457system.cpu.dcache.LoadLockedReq_hits::total 182818 # number of LoadLockedReq hits 458system.cpu.dcache.StoreCondReq_hits::cpu.data 198995 # number of StoreCondReq hits 459system.cpu.dcache.StoreCondReq_hits::total 198995 # number of StoreCondReq hits 460system.cpu.dcache.demand_hits::cpu.data 13392427 # number of demand (read+write) hits 461system.cpu.dcache.demand_hits::total 13392427 # number of demand (read+write) hits 462system.cpu.dcache.overall_hits::cpu.data 13392427 # number of overall hits 463system.cpu.dcache.overall_hits::total 13392427 # number of overall hits 464system.cpu.dcache.ReadReq_misses::cpu.data 1201537 # number of ReadReq misses 465system.cpu.dcache.ReadReq_misses::total 1201537 # number of ReadReq misses 466system.cpu.dcache.WriteReq_misses::cpu.data 573249 # number of WriteReq misses 467system.cpu.dcache.WriteReq_misses::total 573249 # number of WriteReq misses 468system.cpu.dcache.LoadLockedReq_misses::cpu.data 17197 # number of LoadLockedReq misses 469system.cpu.dcache.LoadLockedReq_misses::total 17197 # number of LoadLockedReq misses 470system.cpu.dcache.demand_misses::cpu.data 1774786 # number of demand (read+write) misses 471system.cpu.dcache.demand_misses::total 1774786 # number of demand (read+write) misses 472system.cpu.dcache.overall_misses::cpu.data 1774786 # number of overall misses 473system.cpu.dcache.overall_misses::total 1774786 # number of overall misses 474system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999736250 # number of ReadReq miss cycles 475system.cpu.dcache.ReadReq_miss_latency::total 32999736250 # number of ReadReq miss cycles 476system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461890056 # number of WriteReq miss cycles 477system.cpu.dcache.WriteReq_miss_latency::total 22461890056 # number of WriteReq miss cycles 478system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230671750 # number of LoadLockedReq miss cycles 479system.cpu.dcache.LoadLockedReq_miss_latency::total 230671750 # number of LoadLockedReq miss cycles 480system.cpu.dcache.demand_miss_latency::cpu.data 55461626306 # number of demand (read+write) miss cycles 481system.cpu.dcache.demand_miss_latency::total 55461626306 # number of demand (read+write) miss cycles 482system.cpu.dcache.overall_miss_latency::cpu.data 55461626306 # number of overall miss cycles 483system.cpu.dcache.overall_miss_latency::total 55461626306 # number of overall miss cycles 484system.cpu.dcache.ReadReq_accesses::cpu.data 9016969 # number of ReadReq accesses(hits+misses) 485system.cpu.dcache.ReadReq_accesses::total 9016969 # number of ReadReq accesses(hits+misses) 486system.cpu.dcache.WriteReq_accesses::cpu.data 6150244 # number of WriteReq accesses(hits+misses) 487system.cpu.dcache.WriteReq_accesses::total 6150244 # number of WriteReq accesses(hits+misses) 488system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200015 # number of LoadLockedReq accesses(hits+misses) 489system.cpu.dcache.LoadLockedReq_accesses::total 200015 # number of LoadLockedReq accesses(hits+misses) 490system.cpu.dcache.StoreCondReq_accesses::cpu.data 198995 # number of StoreCondReq accesses(hits+misses) 491system.cpu.dcache.StoreCondReq_accesses::total 198995 # number of StoreCondReq accesses(hits+misses) 492system.cpu.dcache.demand_accesses::cpu.data 15167213 # number of demand (read+write) accesses 493system.cpu.dcache.demand_accesses::total 15167213 # number of demand (read+write) accesses 494system.cpu.dcache.overall_accesses::cpu.data 15167213 # number of overall (read+write) accesses 495system.cpu.dcache.overall_accesses::total 15167213 # number of overall (read+write) accesses 496system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses 497system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses 498system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093208 # miss rate for WriteReq accesses 499system.cpu.dcache.WriteReq_miss_rate::total 0.093208 # miss rate for WriteReq accesses 500system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085979 # miss rate for LoadLockedReq accesses 501system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085979 # miss rate for LoadLockedReq accesses 502system.cpu.dcache.demand_miss_rate::cpu.data 0.117015 # miss rate for demand accesses 503system.cpu.dcache.demand_miss_rate::total 0.117015 # miss rate for demand accesses 504system.cpu.dcache.overall_miss_rate::cpu.data 0.117015 # miss rate for overall accesses 505system.cpu.dcache.overall_miss_rate::total 0.117015 # miss rate for overall accesses 506system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.602630 # average ReadReq miss latency 507system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.602630 # average ReadReq miss latency 508system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39183.478830 # average WriteReq miss latency 509system.cpu.dcache.WriteReq_avg_miss_latency::total 39183.478830 # average WriteReq miss latency 510system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.487818 # average LoadLockedReq miss latency 511system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.487818 # average LoadLockedReq miss latency 512system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency 513system.cpu.dcache.demand_avg_miss_latency::total 31249.754227 # average overall miss latency 514system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency 515system.cpu.dcache.overall_avg_miss_latency::total 31249.754227 # average overall miss latency | 469system.cpu.dcache.tags.tag_accesses 63673578 # Number of tag accesses 470system.cpu.dcache.tags.data_accesses 63673578 # Number of data accesses 471system.cpu.dcache.ReadReq_hits::cpu.data 7816852 # number of ReadReq hits 472system.cpu.dcache.ReadReq_hits::total 7816852 # number of ReadReq hits 473system.cpu.dcache.WriteReq_hits::cpu.data 5578390 # number of WriteReq hits 474system.cpu.dcache.WriteReq_hits::total 5578390 # number of WriteReq hits 475system.cpu.dcache.LoadLockedReq_hits::cpu.data 182745 # number of LoadLockedReq hits 476system.cpu.dcache.LoadLockedReq_hits::total 182745 # number of LoadLockedReq hits 477system.cpu.dcache.StoreCondReq_hits::cpu.data 198996 # number of StoreCondReq hits 478system.cpu.dcache.StoreCondReq_hits::total 198996 # number of StoreCondReq hits 479system.cpu.dcache.demand_hits::cpu.data 13395242 # number of demand (read+write) hits 480system.cpu.dcache.demand_hits::total 13395242 # number of demand (read+write) hits 481system.cpu.dcache.overall_hits::cpu.data 13395242 # number of overall hits 482system.cpu.dcache.overall_hits::total 13395242 # number of overall hits 483system.cpu.dcache.ReadReq_misses::cpu.data 1201883 # number of ReadReq misses 484system.cpu.dcache.ReadReq_misses::total 1201883 # number of ReadReq misses 485system.cpu.dcache.WriteReq_misses::cpu.data 573228 # number of WriteReq misses 486system.cpu.dcache.WriteReq_misses::total 573228 # number of WriteReq misses 487system.cpu.dcache.LoadLockedReq_misses::cpu.data 17271 # number of LoadLockedReq misses 488system.cpu.dcache.LoadLockedReq_misses::total 17271 # number of LoadLockedReq misses 489system.cpu.dcache.demand_misses::cpu.data 1775111 # number of demand (read+write) misses 490system.cpu.dcache.demand_misses::total 1775111 # number of demand (read+write) misses 491system.cpu.dcache.overall_misses::cpu.data 1775111 # number of overall misses 492system.cpu.dcache.overall_misses::total 1775111 # number of overall misses 493system.cpu.dcache.ReadReq_miss_latency::cpu.data 33009196500 # number of ReadReq miss cycles 494system.cpu.dcache.ReadReq_miss_latency::total 33009196500 # number of ReadReq miss cycles 495system.cpu.dcache.WriteReq_miss_latency::cpu.data 22459728804 # number of WriteReq miss cycles 496system.cpu.dcache.WriteReq_miss_latency::total 22459728804 # number of WriteReq miss cycles 497system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231661750 # number of LoadLockedReq miss cycles 498system.cpu.dcache.LoadLockedReq_miss_latency::total 231661750 # number of LoadLockedReq miss cycles 499system.cpu.dcache.demand_miss_latency::cpu.data 55468925304 # number of demand (read+write) miss cycles 500system.cpu.dcache.demand_miss_latency::total 55468925304 # number of demand (read+write) miss cycles 501system.cpu.dcache.overall_miss_latency::cpu.data 55468925304 # number of overall miss cycles 502system.cpu.dcache.overall_miss_latency::total 55468925304 # number of overall miss cycles 503system.cpu.dcache.ReadReq_accesses::cpu.data 9018735 # number of ReadReq accesses(hits+misses) 504system.cpu.dcache.ReadReq_accesses::total 9018735 # number of ReadReq accesses(hits+misses) 505system.cpu.dcache.WriteReq_accesses::cpu.data 6151618 # number of WriteReq accesses(hits+misses) 506system.cpu.dcache.WriteReq_accesses::total 6151618 # number of WriteReq accesses(hits+misses) 507system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200016 # number of LoadLockedReq accesses(hits+misses) 508system.cpu.dcache.LoadLockedReq_accesses::total 200016 # number of LoadLockedReq accesses(hits+misses) 509system.cpu.dcache.StoreCondReq_accesses::cpu.data 198996 # number of StoreCondReq accesses(hits+misses) 510system.cpu.dcache.StoreCondReq_accesses::total 198996 # number of StoreCondReq accesses(hits+misses) 511system.cpu.dcache.demand_accesses::cpu.data 15170353 # number of demand (read+write) accesses 512system.cpu.dcache.demand_accesses::total 15170353 # number of demand (read+write) accesses 513system.cpu.dcache.overall_accesses::cpu.data 15170353 # number of overall (read+write) accesses 514system.cpu.dcache.overall_accesses::total 15170353 # number of overall (read+write) accesses 515system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133265 # miss rate for ReadReq accesses 516system.cpu.dcache.ReadReq_miss_rate::total 0.133265 # miss rate for ReadReq accesses 517system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093183 # miss rate for WriteReq accesses 518system.cpu.dcache.WriteReq_miss_rate::total 0.093183 # miss rate for WriteReq accesses 519system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086348 # miss rate for LoadLockedReq accesses 520system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086348 # miss rate for LoadLockedReq accesses 521system.cpu.dcache.demand_miss_rate::cpu.data 0.117012 # miss rate for demand accesses 522system.cpu.dcache.demand_miss_rate::total 0.117012 # miss rate for demand accesses 523system.cpu.dcache.overall_miss_rate::cpu.data 0.117012 # miss rate for overall accesses 524system.cpu.dcache.overall_miss_rate::total 0.117012 # miss rate for overall accesses 525system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.567267 # average ReadReq miss latency 526system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.567267 # average ReadReq miss latency 527system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39181.143985 # average WriteReq miss latency 528system.cpu.dcache.WriteReq_avg_miss_latency::total 39181.143985 # average WriteReq miss latency 529system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.337386 # average LoadLockedReq miss latency 530system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.337386 # average LoadLockedReq miss latency 531system.cpu.dcache.demand_avg_miss_latency::cpu.data 31248.144653 # average overall miss latency 532system.cpu.dcache.demand_avg_miss_latency::total 31248.144653 # average overall miss latency 533system.cpu.dcache.overall_avg_miss_latency::cpu.data 31248.144653 # average overall miss latency 534system.cpu.dcache.overall_avg_miss_latency::total 31248.144653 # average overall miss latency |
| 516system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 517system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 518system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 519system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 520system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 521system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 522system.cpu.dcache.fast_writes 0 # number of fast writes performed 523system.cpu.dcache.cache_copies 0 # number of cache copies performed | 535system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 536system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 537system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 538system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 539system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 540system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 541system.cpu.dcache.fast_writes 0 # number of fast writes performed 542system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 524system.cpu.dcache.writebacks::writebacks 838171 # number of writebacks 525system.cpu.dcache.writebacks::total 838171 # number of writebacks 526system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127108 # number of ReadReq MSHR hits 527system.cpu.dcache.ReadReq_mshr_hits::total 127108 # number of ReadReq MSHR hits 528system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268996 # number of WriteReq MSHR hits 529system.cpu.dcache.WriteReq_mshr_hits::total 268996 # number of WriteReq MSHR hits | 543system.cpu.dcache.writebacks::writebacks 838424 # number of writebacks 544system.cpu.dcache.writebacks::total 838424 # number of writebacks 545system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127263 # number of ReadReq MSHR hits 546system.cpu.dcache.ReadReq_mshr_hits::total 127263 # number of ReadReq MSHR hits 547system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268960 # number of WriteReq MSHR hits 548system.cpu.dcache.WriteReq_mshr_hits::total 268960 # number of WriteReq MSHR hits |
| 530system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 531system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits | 549system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 550system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits |
| 532system.cpu.dcache.demand_mshr_hits::cpu.data 396104 # number of demand (read+write) MSHR hits 533system.cpu.dcache.demand_mshr_hits::total 396104 # number of demand (read+write) MSHR hits 534system.cpu.dcache.overall_mshr_hits::cpu.data 396104 # number of overall MSHR hits 535system.cpu.dcache.overall_mshr_hits::total 396104 # number of overall MSHR hits 536system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074429 # number of ReadReq MSHR misses 537system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses 538system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304253 # number of WriteReq MSHR misses 539system.cpu.dcache.WriteReq_mshr_misses::total 304253 # number of WriteReq MSHR misses 540system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17194 # number of LoadLockedReq MSHR misses 541system.cpu.dcache.LoadLockedReq_mshr_misses::total 17194 # number of LoadLockedReq MSHR misses 542system.cpu.dcache.demand_mshr_misses::cpu.data 1378682 # number of demand (read+write) MSHR misses 543system.cpu.dcache.demand_mshr_misses::total 1378682 # number of demand (read+write) MSHR misses 544system.cpu.dcache.overall_mshr_misses::cpu.data 1378682 # number of overall MSHR misses 545system.cpu.dcache.overall_mshr_misses::total 1378682 # number of overall MSHR misses | 551system.cpu.dcache.demand_mshr_hits::cpu.data 396223 # number of demand (read+write) MSHR hits 552system.cpu.dcache.demand_mshr_hits::total 396223 # number of demand (read+write) MSHR hits 553system.cpu.dcache.overall_mshr_hits::cpu.data 396223 # number of overall MSHR hits 554system.cpu.dcache.overall_mshr_hits::total 396223 # number of overall MSHR hits 555system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074620 # number of ReadReq MSHR misses 556system.cpu.dcache.ReadReq_mshr_misses::total 1074620 # number of ReadReq MSHR misses 557system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304268 # number of WriteReq MSHR misses 558system.cpu.dcache.WriteReq_mshr_misses::total 304268 # number of WriteReq MSHR misses 559system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17268 # number of LoadLockedReq MSHR misses 560system.cpu.dcache.LoadLockedReq_mshr_misses::total 17268 # number of LoadLockedReq MSHR misses 561system.cpu.dcache.demand_mshr_misses::cpu.data 1378888 # number of demand (read+write) MSHR misses 562system.cpu.dcache.demand_mshr_misses::total 1378888 # number of demand (read+write) MSHR misses 563system.cpu.dcache.overall_mshr_misses::cpu.data 1378888 # number of overall MSHR misses 564system.cpu.dcache.overall_mshr_misses::total 1378888 # number of overall MSHR misses |
| 546system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 547system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 548system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable 549system.cpu.dcache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable 550system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses 551system.cpu.dcache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses | 565system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 566system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 567system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable 568system.cpu.dcache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable 569system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses 570system.cpu.dcache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses |
| 552system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29341393000 # number of ReadReq MSHR miss cycles 553system.cpu.dcache.ReadReq_mshr_miss_latency::total 29341393000 # number of ReadReq MSHR miss cycles 554system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11237642841 # number of WriteReq MSHR miss cycles 555system.cpu.dcache.WriteReq_mshr_miss_latency::total 11237642841 # number of WriteReq MSHR miss cycles 556system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204691750 # number of LoadLockedReq MSHR miss cycles 557system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204691750 # number of LoadLockedReq MSHR miss cycles 558system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40579035841 # number of demand (read+write) MSHR miss cycles 559system.cpu.dcache.demand_mshr_miss_latency::total 40579035841 # number of demand (read+write) MSHR miss cycles 560system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40579035841 # number of overall MSHR miss cycles 561system.cpu.dcache.overall_mshr_miss_latency::total 40579035841 # number of overall MSHR miss cycles 562system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433304500 # number of ReadReq MSHR uncacheable cycles 563system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433304500 # number of ReadReq MSHR uncacheable cycles 564system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2018260000 # number of WriteReq MSHR uncacheable cycles 565system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2018260000 # number of WriteReq MSHR uncacheable cycles 566system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3451564500 # number of overall MSHR uncacheable cycles 567system.cpu.dcache.overall_mshr_uncacheable_latency::total 3451564500 # number of overall MSHR uncacheable cycles 568system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119156 # mshr miss rate for ReadReq accesses 569system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119156 # mshr miss rate for ReadReq accesses 570system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049470 # mshr miss rate for WriteReq accesses 571system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses 572system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085964 # mshr miss rate for LoadLockedReq accesses 573system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085964 # mshr miss rate for LoadLockedReq accesses 574system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090899 # mshr miss rate for demand accesses 575system.cpu.dcache.demand_mshr_miss_rate::total 0.090899 # mshr miss rate for demand accesses 576system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090899 # mshr miss rate for overall accesses 577system.cpu.dcache.overall_mshr_miss_rate::total 0.090899 # mshr miss rate for overall accesses 578system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27308.824501 # average ReadReq mshr miss latency 579system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27308.824501 # average ReadReq mshr miss latency 580system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36935.191571 # average WriteReq mshr miss latency 581system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36935.191571 # average WriteReq mshr miss latency 582system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.835989 # average LoadLockedReq mshr miss latency 583system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.835989 # average LoadLockedReq mshr miss latency 584system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29433.209283 # average overall mshr miss latency 585system.cpu.dcache.demand_avg_mshr_miss_latency::total 29433.209283 # average overall mshr miss latency 586system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29433.209283 # average overall mshr miss latency 587system.cpu.dcache.overall_avg_mshr_miss_latency::total 29433.209283 # average overall mshr miss latency 588system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206826.046176 # average ReadReq mshr uncacheable latency 589system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206826.046176 # average ReadReq mshr uncacheable latency 590system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209820.147624 # average WriteReq mshr uncacheable latency 591system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209820.147624 # average WriteReq mshr uncacheable latency 592system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208566.348420 # average overall mshr uncacheable latency 593system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208566.348420 # average overall mshr uncacheable latency | 571system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29346931250 # number of ReadReq MSHR miss cycles 572system.cpu.dcache.ReadReq_mshr_miss_latency::total 29346931250 # number of ReadReq MSHR miss cycles 573system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11233755093 # number of WriteReq MSHR miss cycles 574system.cpu.dcache.WriteReq_mshr_miss_latency::total 11233755093 # number of WriteReq MSHR miss cycles 575system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205574750 # number of LoadLockedReq MSHR miss cycles 576system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205574750 # number of LoadLockedReq MSHR miss cycles 577system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40580686343 # number of demand (read+write) MSHR miss cycles 578system.cpu.dcache.demand_mshr_miss_latency::total 40580686343 # number of demand (read+write) MSHR miss cycles 579system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40580686343 # number of overall MSHR miss cycles 580system.cpu.dcache.overall_mshr_miss_latency::total 40580686343 # number of overall MSHR miss cycles 581system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433335500 # number of ReadReq MSHR uncacheable cycles 582system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433335500 # number of ReadReq MSHR uncacheable cycles 583system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2017328500 # number of WriteReq MSHR uncacheable cycles 584system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2017328500 # number of WriteReq MSHR uncacheable cycles 585system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3450664000 # number of overall MSHR uncacheable cycles 586system.cpu.dcache.overall_mshr_uncacheable_latency::total 3450664000 # number of overall MSHR uncacheable cycles 587system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119154 # mshr miss rate for ReadReq accesses 588system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119154 # mshr miss rate for ReadReq accesses 589system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049461 # mshr miss rate for WriteReq accesses 590system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049461 # mshr miss rate for WriteReq accesses 591system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086333 # mshr miss rate for LoadLockedReq accesses 592system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086333 # mshr miss rate for LoadLockedReq accesses 593system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090894 # mshr miss rate for demand accesses 594system.cpu.dcache.demand_mshr_miss_rate::total 0.090894 # mshr miss rate for demand accesses 595system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090894 # mshr miss rate for overall accesses 596system.cpu.dcache.overall_mshr_miss_rate::total 0.090894 # mshr miss rate for overall accesses 597system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27309.124388 # average ReadReq mshr miss latency 598system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27309.124388 # average ReadReq mshr miss latency 599system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36920.593335 # average WriteReq mshr miss latency 600system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36920.593335 # average WriteReq mshr miss latency 601system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.954251 # average LoadLockedReq mshr miss latency 602system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.954251 # average LoadLockedReq mshr miss latency 603system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29430.009067 # average overall mshr miss latency 604system.cpu.dcache.demand_avg_mshr_miss_latency::total 29430.009067 # average overall mshr miss latency 605system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29430.009067 # average overall mshr miss latency 606system.cpu.dcache.overall_avg_mshr_miss_latency::total 29430.009067 # average overall mshr miss latency 607system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206830.519481 # average ReadReq mshr uncacheable latency 608system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206830.519481 # average ReadReq mshr uncacheable latency 609system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209723.308036 # average WriteReq mshr uncacheable latency 610system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209723.308036 # average WriteReq mshr uncacheable latency 611system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208511.934256 # average overall mshr uncacheable latency 612system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208511.934256 # average overall mshr uncacheable latency |
| 594system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 613system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 595system.cpu.icache.tags.replacements 1459080 # number of replacements 596system.cpu.icache.tags.tagsinuse 509.440068 # Cycle average of tags in use 597system.cpu.icache.tags.total_refs 18968295 # Total number of references to valid blocks. 598system.cpu.icache.tags.sampled_refs 1459591 # Sample count of references to valid blocks. 599system.cpu.icache.tags.avg_refs 12.995623 # Average number of references to valid blocks. 600system.cpu.icache.tags.warmup_cycle 33851094250 # Cycle when the warmup percentage was hit. 601system.cpu.icache.tags.occ_blocks::cpu.inst 509.440068 # Average occupied blocks per requestor | 614system.cpu.icache.tags.replacements 1458527 # number of replacements 615system.cpu.icache.tags.tagsinuse 509.440030 # Cycle average of tags in use 616system.cpu.icache.tags.total_refs 18957390 # Total number of references to valid blocks. 617system.cpu.icache.tags.sampled_refs 1459038 # Sample count of references to valid blocks. 618system.cpu.icache.tags.avg_refs 12.993075 # Average number of references to valid blocks. 619system.cpu.icache.tags.warmup_cycle 33850944250 # Cycle when the warmup percentage was hit. 620system.cpu.icache.tags.occ_blocks::cpu.inst 509.440030 # Average occupied blocks per requestor |
| 602system.cpu.icache.tags.occ_percent::cpu.inst 0.995000 # Average percentage of cache occupancy 603system.cpu.icache.tags.occ_percent::total 0.995000 # Average percentage of cache occupancy 604system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 605system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id | 621system.cpu.icache.tags.occ_percent::cpu.inst 0.995000 # Average percentage of cache occupancy 622system.cpu.icache.tags.occ_percent::total 0.995000 # Average percentage of cache occupancy 623system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 624system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id |
| 606system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 607system.cpu.icache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id | 625system.cpu.icache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 626system.cpu.icache.tags.age_task_id_blocks_1024::2 401 # Occupied blocks per task id |
| 608system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 627system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 609system.cpu.icache.tags.tag_accesses 21887836 # Number of tag accesses 610system.cpu.icache.tags.data_accesses 21887836 # Number of data accesses 611system.cpu.icache.ReadReq_hits::cpu.inst 18968298 # number of ReadReq hits 612system.cpu.icache.ReadReq_hits::total 18968298 # number of ReadReq hits 613system.cpu.icache.demand_hits::cpu.inst 18968298 # number of demand (read+write) hits 614system.cpu.icache.demand_hits::total 18968298 # number of demand (read+write) hits 615system.cpu.icache.overall_hits::cpu.inst 18968298 # number of overall hits 616system.cpu.icache.overall_hits::total 18968298 # number of overall hits 617system.cpu.icache.ReadReq_misses::cpu.inst 1459769 # number of ReadReq misses 618system.cpu.icache.ReadReq_misses::total 1459769 # number of ReadReq misses 619system.cpu.icache.demand_misses::cpu.inst 1459769 # number of demand (read+write) misses 620system.cpu.icache.demand_misses::total 1459769 # number of demand (read+write) misses 621system.cpu.icache.overall_misses::cpu.inst 1459769 # number of overall misses 622system.cpu.icache.overall_misses::total 1459769 # number of overall misses 623system.cpu.icache.ReadReq_miss_latency::cpu.inst 20155075408 # number of ReadReq miss cycles 624system.cpu.icache.ReadReq_miss_latency::total 20155075408 # number of ReadReq miss cycles 625system.cpu.icache.demand_miss_latency::cpu.inst 20155075408 # number of demand (read+write) miss cycles 626system.cpu.icache.demand_miss_latency::total 20155075408 # number of demand (read+write) miss cycles 627system.cpu.icache.overall_miss_latency::cpu.inst 20155075408 # number of overall miss cycles 628system.cpu.icache.overall_miss_latency::total 20155075408 # number of overall miss cycles 629system.cpu.icache.ReadReq_accesses::cpu.inst 20428067 # number of ReadReq accesses(hits+misses) 630system.cpu.icache.ReadReq_accesses::total 20428067 # number of ReadReq accesses(hits+misses) 631system.cpu.icache.demand_accesses::cpu.inst 20428067 # number of demand (read+write) accesses 632system.cpu.icache.demand_accesses::total 20428067 # number of demand (read+write) accesses 633system.cpu.icache.overall_accesses::cpu.inst 20428067 # number of overall (read+write) accesses 634system.cpu.icache.overall_accesses::total 20428067 # number of overall (read+write) accesses 635system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071459 # miss rate for ReadReq accesses 636system.cpu.icache.ReadReq_miss_rate::total 0.071459 # miss rate for ReadReq accesses 637system.cpu.icache.demand_miss_rate::cpu.inst 0.071459 # miss rate for demand accesses 638system.cpu.icache.demand_miss_rate::total 0.071459 # miss rate for demand accesses 639system.cpu.icache.overall_miss_rate::cpu.inst 0.071459 # miss rate for overall accesses 640system.cpu.icache.overall_miss_rate::total 0.071459 # miss rate for overall accesses 641system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13807.030707 # average ReadReq miss latency 642system.cpu.icache.ReadReq_avg_miss_latency::total 13807.030707 # average ReadReq miss latency 643system.cpu.icache.demand_avg_miss_latency::cpu.inst 13807.030707 # average overall miss latency 644system.cpu.icache.demand_avg_miss_latency::total 13807.030707 # average overall miss latency 645system.cpu.icache.overall_avg_miss_latency::cpu.inst 13807.030707 # average overall miss latency 646system.cpu.icache.overall_avg_miss_latency::total 13807.030707 # average overall miss latency | 628system.cpu.icache.tags.tag_accesses 21875821 # Number of tag accesses 629system.cpu.icache.tags.data_accesses 21875821 # Number of data accesses 630system.cpu.icache.ReadReq_hits::cpu.inst 18957393 # number of ReadReq hits 631system.cpu.icache.ReadReq_hits::total 18957393 # number of ReadReq hits 632system.cpu.icache.demand_hits::cpu.inst 18957393 # number of demand (read+write) hits 633system.cpu.icache.demand_hits::total 18957393 # number of demand (read+write) hits 634system.cpu.icache.overall_hits::cpu.inst 18957393 # number of overall hits 635system.cpu.icache.overall_hits::total 18957393 # number of overall hits 636system.cpu.icache.ReadReq_misses::cpu.inst 1459214 # number of ReadReq misses 637system.cpu.icache.ReadReq_misses::total 1459214 # number of ReadReq misses 638system.cpu.icache.demand_misses::cpu.inst 1459214 # number of demand (read+write) misses 639system.cpu.icache.demand_misses::total 1459214 # number of demand (read+write) misses 640system.cpu.icache.overall_misses::cpu.inst 1459214 # number of overall misses 641system.cpu.icache.overall_misses::total 1459214 # number of overall misses 642system.cpu.icache.ReadReq_miss_latency::cpu.inst 20146503654 # number of ReadReq miss cycles 643system.cpu.icache.ReadReq_miss_latency::total 20146503654 # number of ReadReq miss cycles 644system.cpu.icache.demand_miss_latency::cpu.inst 20146503654 # number of demand (read+write) miss cycles 645system.cpu.icache.demand_miss_latency::total 20146503654 # number of demand (read+write) miss cycles 646system.cpu.icache.overall_miss_latency::cpu.inst 20146503654 # number of overall miss cycles 647system.cpu.icache.overall_miss_latency::total 20146503654 # number of overall miss cycles 648system.cpu.icache.ReadReq_accesses::cpu.inst 20416607 # number of ReadReq accesses(hits+misses) 649system.cpu.icache.ReadReq_accesses::total 20416607 # number of ReadReq accesses(hits+misses) 650system.cpu.icache.demand_accesses::cpu.inst 20416607 # number of demand (read+write) accesses 651system.cpu.icache.demand_accesses::total 20416607 # number of demand (read+write) accesses 652system.cpu.icache.overall_accesses::cpu.inst 20416607 # number of overall (read+write) accesses 653system.cpu.icache.overall_accesses::total 20416607 # number of overall (read+write) accesses 654system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071472 # miss rate for ReadReq accesses 655system.cpu.icache.ReadReq_miss_rate::total 0.071472 # miss rate for ReadReq accesses 656system.cpu.icache.demand_miss_rate::cpu.inst 0.071472 # miss rate for demand accesses 657system.cpu.icache.demand_miss_rate::total 0.071472 # miss rate for demand accesses 658system.cpu.icache.overall_miss_rate::cpu.inst 0.071472 # miss rate for overall accesses 659system.cpu.icache.overall_miss_rate::total 0.071472 # miss rate for overall accesses 660system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13806.407870 # average ReadReq miss latency 661system.cpu.icache.ReadReq_avg_miss_latency::total 13806.407870 # average ReadReq miss latency 662system.cpu.icache.demand_avg_miss_latency::cpu.inst 13806.407870 # average overall miss latency 663system.cpu.icache.demand_avg_miss_latency::total 13806.407870 # average overall miss latency 664system.cpu.icache.overall_avg_miss_latency::cpu.inst 13806.407870 # average overall miss latency 665system.cpu.icache.overall_avg_miss_latency::total 13806.407870 # average overall miss latency |
| 647system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 648system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 649system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 650system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 651system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 652system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 653system.cpu.icache.fast_writes 0 # number of fast writes performed 654system.cpu.icache.cache_copies 0 # number of cache copies performed | 666system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 667system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 668system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 669system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 670system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 671system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 672system.cpu.icache.fast_writes 0 # number of fast writes performed 673system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 655system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459769 # number of ReadReq MSHR misses 656system.cpu.icache.ReadReq_mshr_misses::total 1459769 # number of ReadReq MSHR misses 657system.cpu.icache.demand_mshr_misses::cpu.inst 1459769 # number of demand (read+write) MSHR misses 658system.cpu.icache.demand_mshr_misses::total 1459769 # number of demand (read+write) MSHR misses 659system.cpu.icache.overall_mshr_misses::cpu.inst 1459769 # number of overall MSHR misses 660system.cpu.icache.overall_mshr_misses::total 1459769 # number of overall MSHR misses 661system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17958174092 # number of ReadReq MSHR miss cycles 662system.cpu.icache.ReadReq_mshr_miss_latency::total 17958174092 # number of ReadReq MSHR miss cycles 663system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17958174092 # number of demand (read+write) MSHR miss cycles 664system.cpu.icache.demand_mshr_miss_latency::total 17958174092 # number of demand (read+write) MSHR miss cycles 665system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17958174092 # number of overall MSHR miss cycles 666system.cpu.icache.overall_mshr_miss_latency::total 17958174092 # number of overall MSHR miss cycles 667system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for ReadReq accesses 668system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071459 # mshr miss rate for ReadReq accesses 669system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for demand accesses 670system.cpu.icache.demand_mshr_miss_rate::total 0.071459 # mshr miss rate for demand accesses 671system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for overall accesses 672system.cpu.icache.overall_mshr_miss_rate::total 0.071459 # mshr miss rate for overall accesses 673system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12302.065664 # average ReadReq mshr miss latency 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12302.065664 # average ReadReq mshr miss latency 675system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12302.065664 # average overall mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::total 12302.065664 # average overall mshr miss latency 677system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12302.065664 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::total 12302.065664 # average overall mshr miss latency | 674system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459214 # number of ReadReq MSHR misses 675system.cpu.icache.ReadReq_mshr_misses::total 1459214 # number of ReadReq MSHR misses 676system.cpu.icache.demand_mshr_misses::cpu.inst 1459214 # number of demand (read+write) MSHR misses 677system.cpu.icache.demand_mshr_misses::total 1459214 # number of demand (read+write) MSHR misses 678system.cpu.icache.overall_mshr_misses::cpu.inst 1459214 # number of overall MSHR misses 679system.cpu.icache.overall_mshr_misses::total 1459214 # number of overall MSHR misses 680system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17950426346 # number of ReadReq MSHR miss cycles 681system.cpu.icache.ReadReq_mshr_miss_latency::total 17950426346 # number of ReadReq MSHR miss cycles 682system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17950426346 # number of demand (read+write) MSHR miss cycles 683system.cpu.icache.demand_mshr_miss_latency::total 17950426346 # number of demand (read+write) MSHR miss cycles 684system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17950426346 # number of overall MSHR miss cycles 685system.cpu.icache.overall_mshr_miss_latency::total 17950426346 # number of overall MSHR miss cycles 686system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071472 # mshr miss rate for ReadReq accesses 687system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071472 # mshr miss rate for ReadReq accesses 688system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071472 # mshr miss rate for demand accesses 689system.cpu.icache.demand_mshr_miss_rate::total 0.071472 # mshr miss rate for demand accesses 690system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071472 # mshr miss rate for overall accesses 691system.cpu.icache.overall_mshr_miss_rate::total 0.071472 # mshr miss rate for overall accesses 692system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12301.435119 # average ReadReq mshr miss latency 693system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12301.435119 # average ReadReq mshr miss latency 694system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12301.435119 # average overall mshr miss latency 695system.cpu.icache.demand_avg_mshr_miss_latency::total 12301.435119 # average overall mshr miss latency 696system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12301.435119 # average overall mshr miss latency 697system.cpu.icache.overall_avg_mshr_miss_latency::total 12301.435119 # average overall mshr miss latency |
| 679system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 698system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 680system.cpu.l2cache.tags.replacements 339394 # number of replacements 681system.cpu.l2cache.tags.tagsinuse 65314.689332 # Cycle average of tags in use | 699system.cpu.l2cache.tags.replacements 339383 # number of replacements 700system.cpu.l2cache.tags.tagsinuse 65314.882486 # Cycle average of tags in use |
| 682system.cpu.l2cache.tags.total_refs 2982705 # Total number of references to valid blocks. | 701system.cpu.l2cache.tags.total_refs 2982705 # Total number of references to valid blocks. |
| 683system.cpu.l2cache.tags.sampled_refs 404554 # Sample count of references to valid blocks. 684system.cpu.l2cache.tags.avg_refs 7.372823 # Average number of references to valid blocks. | 702system.cpu.l2cache.tags.sampled_refs 404543 # Sample count of references to valid blocks. 703system.cpu.l2cache.tags.avg_refs 7.373023 # Average number of references to valid blocks. |
| 685system.cpu.l2cache.tags.warmup_cycle 6335415750 # Cycle when the warmup percentage was hit. | 704system.cpu.l2cache.tags.warmup_cycle 6335415750 # Cycle when the warmup percentage was hit. |
| 686system.cpu.l2cache.tags.occ_blocks::writebacks 54416.774568 # Average occupied blocks per requestor 687system.cpu.l2cache.tags.occ_blocks::cpu.inst 5825.207067 # Average occupied blocks per requestor 688system.cpu.l2cache.tags.occ_blocks::cpu.data 5072.707697 # Average occupied blocks per requestor 689system.cpu.l2cache.tags.occ_percent::writebacks 0.830334 # Average percentage of cache occupancy 690system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088886 # Average percentage of cache occupancy 691system.cpu.l2cache.tags.occ_percent::cpu.data 0.077403 # Average percentage of cache occupancy 692system.cpu.l2cache.tags.occ_percent::total 0.996623 # Average percentage of cache occupancy | 705system.cpu.l2cache.tags.occ_blocks::writebacks 54442.497002 # Average occupied blocks per requestor 706system.cpu.l2cache.tags.occ_blocks::cpu.inst 5830.422847 # Average occupied blocks per requestor 707system.cpu.l2cache.tags.occ_blocks::cpu.data 5041.962637 # Average occupied blocks per requestor 708system.cpu.l2cache.tags.occ_percent::writebacks 0.830727 # Average percentage of cache occupancy 709system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088965 # Average percentage of cache occupancy 710system.cpu.l2cache.tags.occ_percent::cpu.data 0.076934 # Average percentage of cache occupancy 711system.cpu.l2cache.tags.occ_percent::total 0.996626 # Average percentage of cache occupancy |
| 693system.cpu.l2cache.tags.occ_task_id_blocks::1024 65160 # Occupied blocks per task id 694system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id | 712system.cpu.l2cache.tags.occ_task_id_blocks::1024 65160 # Occupied blocks per task id 713system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id |
| 695system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1413 # Occupied blocks per task id | 714system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1415 # Occupied blocks per task id |
| 696system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5172 # Occupied blocks per task id | 715system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5172 # Occupied blocks per task id |
| 697system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2816 # Occupied blocks per task id | 716system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2814 # Occupied blocks per task id |
| 698system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55531 # Occupied blocks per task id 699system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994263 # Percentage of cache occupancy per task id | 717system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55531 # Occupied blocks per task id 718system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994263 # Percentage of cache occupancy per task id |
| 700system.cpu.l2cache.tags.tag_accesses 30259068 # Number of tag accesses 701system.cpu.l2cache.tags.data_accesses 30259068 # Number of data accesses 702system.cpu.l2cache.ReadReq_hits::cpu.inst 1443260 # number of ReadReq hits 703system.cpu.l2cache.ReadReq_hits::cpu.data 819385 # number of ReadReq hits 704system.cpu.l2cache.ReadReq_hits::total 2262645 # number of ReadReq hits 705system.cpu.l2cache.Writeback_hits::writebacks 838171 # number of Writeback hits 706system.cpu.l2cache.Writeback_hits::total 838171 # number of Writeback hits | 719system.cpu.l2cache.tags.tag_accesses 30258908 # Number of tag accesses 720system.cpu.l2cache.tags.data_accesses 30258908 # Number of data accesses 721system.cpu.l2cache.ReadReq_hits::cpu.inst 1442704 # number of ReadReq hits 722system.cpu.l2cache.ReadReq_hits::cpu.data 819672 # number of ReadReq hits 723system.cpu.l2cache.ReadReq_hits::total 2262376 # number of ReadReq hits 724system.cpu.l2cache.Writeback_hits::writebacks 838424 # number of Writeback hits 725system.cpu.l2cache.Writeback_hits::total 838424 # number of Writeback hits |
| 707system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 708system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 726system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 727system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 709system.cpu.l2cache.ReadExReq_hits::cpu.data 187597 # number of ReadExReq hits 710system.cpu.l2cache.ReadExReq_hits::total 187597 # number of ReadExReq hits 711system.cpu.l2cache.demand_hits::cpu.inst 1443260 # number of demand (read+write) hits 712system.cpu.l2cache.demand_hits::cpu.data 1006982 # number of demand (read+write) hits 713system.cpu.l2cache.demand_hits::total 2450242 # number of demand (read+write) hits 714system.cpu.l2cache.overall_hits::cpu.inst 1443260 # number of overall hits 715system.cpu.l2cache.overall_hits::cpu.data 1006982 # number of overall hits 716system.cpu.l2cache.overall_hits::total 2450242 # number of overall hits 717system.cpu.l2cache.ReadReq_misses::cpu.inst 16444 # number of ReadReq misses 718system.cpu.l2cache.ReadReq_misses::cpu.data 272210 # number of ReadReq misses 719system.cpu.l2cache.ReadReq_misses::total 288654 # number of ReadReq misses 720system.cpu.l2cache.UpgradeReq_misses::cpu.data 20 # number of UpgradeReq misses 721system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses 722system.cpu.l2cache.ReadExReq_misses::cpu.data 116660 # number of ReadExReq misses 723system.cpu.l2cache.ReadExReq_misses::total 116660 # number of ReadExReq misses 724system.cpu.l2cache.demand_misses::cpu.inst 16444 # number of demand (read+write) misses 725system.cpu.l2cache.demand_misses::cpu.data 388870 # number of demand (read+write) misses 726system.cpu.l2cache.demand_misses::total 405314 # number of demand (read+write) misses 727system.cpu.l2cache.overall_misses::cpu.inst 16444 # number of overall misses 728system.cpu.l2cache.overall_misses::cpu.data 388870 # number of overall misses 729system.cpu.l2cache.overall_misses::total 405314 # number of overall misses 730system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1322904500 # number of ReadReq miss cycles 731system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19744325250 # number of ReadReq miss cycles 732system.cpu.l2cache.ReadReq_miss_latency::total 21067229750 # number of ReadReq miss cycles 733system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 253997 # 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| 813system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1116950000 # number of ReadReq MSHR miss cycles 814system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16343076250 # number of ReadReq MSHR miss cycles 815system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17460026250 # number of ReadReq MSHR miss cycles 816system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 455517 # number of UpgradeReq MSHR miss cycles 817system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 455517 # number of UpgradeReq MSHR miss cycles 818system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7501019891 # number of ReadExReq MSHR miss cycles 819system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7501019891 # number of ReadExReq MSHR miss cycles 820system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1116950000 # number of demand (read+write) MSHR miss cycles 821system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23844096141 # number of demand (read+write) MSHR miss cycles 822system.cpu.l2cache.demand_mshr_miss_latency::total 24961046141 # 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number of overall MSHR uncacheable cycles 832system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for ReadReq accesses 833system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249369 # mshr miss rate for ReadReq accesses 834system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113140 # mshr miss rate for ReadReq accesses 835system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.833333 # mshr miss rate for UpgradeReq accesses 836system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses 837system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383426 # mshr miss rate for ReadExReq accesses 838system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383426 # mshr miss rate for ReadExReq accesses 839system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for demand accesses 840system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for demand accesses 841system.cpu.l2cache.demand_mshr_miss_rate::total 0.141939 # mshr miss rate for demand accesses 842system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for overall accesses 843system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for overall accesses 844system.cpu.l2cache.overall_mshr_miss_rate::total 0.141939 # mshr miss rate for overall accesses 845system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67924.470932 # average ReadReq mshr miss latency 846system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.485912 # average ReadReq mshr miss latency 847system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.733584 # average ReadReq mshr miss latency 848system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22775.850000 # average UpgradeReq mshr miss latency 849system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22775.850000 # average UpgradeReq mshr miss latency 850system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.130387 # average ReadExReq mshr miss latency 851system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.130387 # average ReadExReq mshr miss latency 852system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency 853system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency 854system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency 855system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency 856system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency 857system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency 858system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192823.448773 # average ReadReq mshr uncacheable latency 859system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192823.448773 # average ReadReq mshr uncacheable latency 860system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196820.095644 # average WriteReq mshr uncacheable latency 861system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196820.095644 # average WriteReq mshr uncacheable latency 862system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195146.474107 # average overall mshr uncacheable latency 863system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195146.474107 # average overall mshr uncacheable latency | 832system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1115769250 # number of ReadReq MSHR miss cycles 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16346505000 # number of ReadReq MSHR miss cycles 834system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17462274250 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 421016 # number of UpgradeReq MSHR miss cycles 836system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 421016 # number of UpgradeReq MSHR miss cycles 837system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7497021141 # number of ReadExReq MSHR miss cycles 838system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7497021141 # number of ReadExReq MSHR miss cycles 839system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1115769250 # number of demand (read+write) MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23843526141 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::total 24959295391 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1115769250 # number of overall MSHR miss cycles 843system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23843526141 # number of overall MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::total 24959295391 # number of overall MSHR miss cycles 845system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336297500 # number of ReadReq MSHR uncacheable cycles 846system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336297500 # number of ReadReq MSHR uncacheable cycles 847system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892281000 # number of WriteReq MSHR uncacheable cycles 848system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892281000 # number of WriteReq MSHR uncacheable cycles 849system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3228578500 # number of overall MSHR uncacheable cycles 850system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3228578500 # number of overall MSHR uncacheable cycles 851system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for ReadReq accesses 852system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249288 # mshr miss rate for ReadReq accesses 853system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113145 # mshr miss rate for ReadReq accesses 854system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses 855system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses 856system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383411 # mshr miss rate for ReadExReq accesses 857system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383411 # mshr miss rate for ReadExReq accesses 858system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for demand accesses 859system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278519 # mshr miss rate for demand accesses 860system.cpu.l2cache.demand_mshr_miss_rate::total 0.141946 # mshr miss rate for demand accesses 861system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for overall accesses 862system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278519 # mshr miss rate for overall accesses 863system.cpu.l2cache.overall_mshr_miss_rate::total 0.141946 # mshr miss rate for overall accesses 864system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67840.290022 # average ReadReq mshr miss latency 865system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60055.935603 # average ReadReq mshr miss latency 866system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60499.503698 # average ReadReq mshr miss latency 867system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23389.777778 # average UpgradeReq mshr miss latency 868system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23389.777778 # average UpgradeReq mshr miss latency 869system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64262.751719 # average ReadExReq mshr miss latency 870system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64262.751719 # average ReadExReq mshr miss latency 871system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67840.290022 # average overall mshr miss latency 872system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61318.056168 # average overall mshr miss latency 873system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61582.729186 # average overall mshr miss latency 874system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67840.290022 # average overall mshr miss latency 875system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61318.056168 # average overall mshr miss latency 876system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61582.729186 # average overall mshr miss latency 877system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192827.922078 # average ReadReq mshr uncacheable latency 878system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192827.922078 # average ReadReq mshr uncacheable latency 879system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196723.256056 # average WriteReq mshr uncacheable latency 880system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196723.256056 # average WriteReq mshr uncacheable latency 881system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195092.059943 # average overall mshr uncacheable latency 882system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195092.059943 # average overall mshr uncacheable latency |
| 864system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 883system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 865system.cpu.toL2Bus.trans_dist::ReadReq 2558467 # Transaction distribution 866system.cpu.toL2Bus.trans_dist::ReadResp 2558434 # Transaction distribution | 884system.cpu.toL2Bus.trans_dist::ReadReq 2558177 # Transaction distribution 885system.cpu.toL2Bus.trans_dist::ReadResp 2558144 # Transaction distribution |
| 867system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution | 886system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution 887system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution |
| 869system.cpu.toL2Bus.trans_dist::Writeback 838171 # Transaction distribution 870system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41592 # Transaction distribution 871system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution 872system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution 873system.cpu.toL2Bus.trans_dist::ReadExReq 304257 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::ReadExResp 304257 # Transaction distribution | 888system.cpu.toL2Bus.trans_dist::Writeback 838424 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41594 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution 891system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution 892system.cpu.toL2Bus.trans_dist::ReadExReq 304274 # Transaction distribution 893system.cpu.toL2Bus.trans_dist::ReadExResp 304274 # Transaction distribution |
| 875system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution | 894system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution |
| 876system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2919473 # Packet count per connected master and slave (bytes) 877system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663177 # Packet count per connected master and slave (bytes) 878system.cpu.toL2Bus.pkt_count::total 6582650 # Packet count per connected master and slave (bytes) 879system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93421056 # Cumulative packet size per connected master and slave (bytes) 880system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030748 # Cumulative packet size per connected master and slave (bytes) 881system.cpu.toL2Bus.pkt_size::total 236451804 # Cumulative packet size per connected master and slave (bytes) | 895system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2918365 # Packet count per connected master and slave (bytes) 896system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663990 # Packet count per connected master and slave (bytes) 897system.cpu.toL2Bus.pkt_count::total 6582355 # Packet count per connected master and slave (bytes) 898system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93385664 # Cumulative packet size per connected master and slave (bytes) 899system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143064988 # Cumulative packet size per connected master and slave (bytes) 900system.cpu.toL2Bus.pkt_size::total 236450652 # Cumulative packet size per connected master and slave (bytes) |
| 882system.cpu.toL2Bus.snoops 41986 # Total snoops (count) | 901system.cpu.toL2Bus.snoops 41986 # Total snoops (count) |
| 883system.cpu.toL2Bus.snoop_fanout::samples 3752130 # Request fanout histogram 884system.cpu.toL2Bus.snoop_fanout::mean 1.011131 # Request fanout histogram 885system.cpu.toL2Bus.snoop_fanout::stdev 0.104915 # Request fanout histogram | 902system.cpu.toL2Bus.snoop_fanout::samples 3752110 # Request fanout histogram 903system.cpu.toL2Bus.snoop_fanout::mean 1.011132 # Request fanout histogram 904system.cpu.toL2Bus.snoop_fanout::stdev 0.104918 # Request fanout histogram |
| 886system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 887system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 905system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 906system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 888system.cpu.toL2Bus.snoop_fanout::1 3710365 98.89% 98.89% # Request fanout histogram 889system.cpu.toL2Bus.snoop_fanout::2 41765 1.11% 100.00% # Request fanout histogram | 907system.cpu.toL2Bus.snoop_fanout::1 3710343 98.89% 98.89% # Request fanout histogram 908system.cpu.toL2Bus.snoop_fanout::2 41767 1.11% 100.00% # Request fanout histogram |
| 890system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 891system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 892system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 909system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 910system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 911system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 893system.cpu.toL2Bus.snoop_fanout::total 3752130 # Request fanout histogram 894system.cpu.toL2Bus.reqLayer0.occupancy 2698163499 # Layer occupancy (ticks) | 912system.cpu.toL2Bus.snoop_fanout::total 3752110 # Request fanout histogram 913system.cpu.toL2Bus.reqLayer0.occupancy 2698405000 # Layer occupancy (ticks) |
| 895system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 896system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 897system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 914system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 915system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 916system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 898system.cpu.toL2Bus.respLayer0.occupancy 2193277408 # Layer occupancy (ticks) | 917system.cpu.toL2Bus.respLayer0.occupancy 2192449154 # Layer occupancy (ticks) |
| 899system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 918system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 900system.cpu.toL2Bus.respLayer1.occupancy 2194687409 # Layer occupancy (ticks) | 919system.cpu.toL2Bus.respLayer1.occupancy 2195119407 # Layer occupancy (ticks) |
| 901system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 902system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 903system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 904system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 905system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 906system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 907system.disk0.dma_write_txs 395 # Number of DMA write transactions. 908system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 56 unchanged lines hidden (view full) --- 965system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 966system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 967system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 968system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 969system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 970system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 971system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 972system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 920system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 921system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 922system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 923system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 924system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 925system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 926system.disk0.dma_write_txs 395 # Number of DMA write transactions. 927system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 56 unchanged lines hidden (view full) --- 984system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 985system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 986system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 987system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 988system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 989system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 990system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 991system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 973system.iobus.reqLayer29.occupancy 242092694 # Layer occupancy (ticks) | 992system.iobus.reqLayer29.occupancy 242104189 # Layer occupancy (ticks) |
| 974system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 975system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 976system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 977system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) 978system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 993system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 994system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 995system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 996system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) 997system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 979system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) | 998system.iobus.respLayer1.occupancy 42024001 # Layer occupancy (ticks) |
| 980system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 981system.iocache.tags.replacements 41685 # number of replacements | 999system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1000system.iocache.tags.replacements 41685 # number of replacements |
| 982system.iocache.tags.tagsinuse 1.302259 # Cycle average of tags in use | 1001system.iocache.tags.tagsinuse 1.302269 # Cycle average of tags in use |
| 983system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 984system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 985system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1002system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1003system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1004system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 986system.iocache.tags.warmup_cycle 1729989085000 # Cycle when the warmup percentage was hit. 987system.iocache.tags.occ_blocks::tsunami.ide 1.302259 # Average occupied blocks per requestor 988system.iocache.tags.occ_percent::tsunami.ide 0.081391 # Average percentage of cache occupancy 989system.iocache.tags.occ_percent::total 0.081391 # Average percentage of cache occupancy | 1005system.iocache.tags.warmup_cycle 1729988196000 # Cycle when the warmup percentage was hit. 1006system.iocache.tags.occ_blocks::tsunami.ide 1.302269 # Average occupied blocks per requestor 1007system.iocache.tags.occ_percent::tsunami.ide 0.081392 # Average percentage of cache occupancy 1008system.iocache.tags.occ_percent::total 0.081392 # Average percentage of cache occupancy |
| 990system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 991system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 992system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 993system.iocache.tags.tag_accesses 375525 # Number of tag accesses 994system.iocache.tags.data_accesses 375525 # Number of data accesses 995system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 996system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 997system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 998system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 999system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1000system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1001system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1002system.iocache.overall_misses::total 173 # number of overall misses 1003system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles 1004system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles | 1009system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1010system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1011system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1012system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1013system.iocache.tags.data_accesses 375525 # Number of data accesses 1014system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1015system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1016system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 1017system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 1018system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1019system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1020system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1021system.iocache.overall_misses::total 173 # number of overall misses 1022system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles 1023system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles |
| 1005system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775999311 # number of WriteInvalidateReq miss cycles 1006system.iocache.WriteInvalidateReq_miss_latency::total 8775999311 # number of WriteInvalidateReq miss cycles | 1024system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8768796805 # number of WriteInvalidateReq miss cycles 1025system.iocache.WriteInvalidateReq_miss_latency::total 8768796805 # number of WriteInvalidateReq miss cycles |
| 1007system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles 1008system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles 1009system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles 1010system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles 1011system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1012system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1013system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1014system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 1021system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1022system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1023system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1024system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1025system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1026system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1027system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency 1028system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency | 1026system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles 1027system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles 1028system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles 1029system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles 1030system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1031system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1032system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1033system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 1040system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1041system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1042system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1043system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1044system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1045system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1046system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency 1047system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency |
| 1029system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211205.220230 # average WriteInvalidateReq miss latency 1030system.iocache.WriteInvalidateReq_avg_miss_latency::total 211205.220230 # average WriteInvalidateReq miss latency | 1048system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211031.883062 # average WriteInvalidateReq miss latency 1049system.iocache.WriteInvalidateReq_avg_miss_latency::total 211031.883062 # average WriteInvalidateReq miss latency |
| 1031system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency 1032system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency 1033system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency 1034system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency | 1050system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency 1051system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency 1052system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency 1053system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency |
| 1035system.iocache.blocked_cycles::no_mshrs 73059 # number of cycles access was blocked | 1054system.iocache.blocked_cycles::no_mshrs 73108 # number of cycles access was blocked |
| 1036system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1055system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1037system.iocache.blocked::no_mshrs 10002 # number of cycles access was blocked | 1056system.iocache.blocked::no_mshrs 9982 # number of cycles access was blocked |
| 1038system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1057system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1039system.iocache.avg_blocked_cycles::no_mshrs 7.304439 # average number of cycles each access was blocked | 1058system.iocache.avg_blocked_cycles::no_mshrs 7.323983 # average number of cycles each access was blocked |
| 1040system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1041system.iocache.fast_writes 0 # number of fast writes performed 1042system.iocache.cache_copies 0 # number of cache copies performed 1043system.iocache.writebacks::writebacks 41512 # number of writebacks 1044system.iocache.writebacks::total 41512 # number of writebacks 1045system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1046system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1047system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1048system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 1049system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1050system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1051system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1052system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1053system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles 1054system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles | 1059system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1060system.iocache.fast_writes 0 # number of fast writes performed 1061system.iocache.cache_copies 0 # number of cache copies performed 1062system.iocache.writebacks::writebacks 41512 # number of writebacks 1063system.iocache.writebacks::total 41512 # number of writebacks 1064system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1065system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1066system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1067system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 1068system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1069system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1070system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1071system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1072system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles 1073system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles |
| 1055system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6615295311 # number of WriteInvalidateReq MSHR miss cycles 1056system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6615295311 # number of WriteInvalidateReq MSHR miss cycles | 1074system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6608090807 # number of WriteInvalidateReq MSHR miss cycles 1075system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6608090807 # number of WriteInvalidateReq MSHR miss cycles |
| 1057system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles 1058system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles 1059system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles 1060system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles 1061system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1062system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1063system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1064system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1065system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1066system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1067system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1068system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1069system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency 1070system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency | 1076system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles 1077system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles 1078system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles 1079system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles 1080system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1081system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1082system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1083system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1084system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1085system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1086system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1087system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1088system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency 1089system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency |
| 1071system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159205.220230 # average WriteInvalidateReq mshr miss latency 1072system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159205.220230 # average WriteInvalidateReq mshr miss latency | 1090system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159031.834978 # average WriteInvalidateReq mshr miss latency 1091system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159031.834978 # average WriteInvalidateReq mshr miss latency |
| 1073system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency 1074system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency 1075system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency 1076system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency 1077system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1092system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency 1093system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency 1094system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency 1095system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency 1096system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1078system.membus.trans_dist::ReadReq 295757 # Transaction distribution 1079system.membus.trans_dist::ReadResp 295741 # Transaction distribution | 1097system.membus.trans_dist::ReadReq 295738 # Transaction distribution 1098system.membus.trans_dist::ReadResp 295722 # Transaction distribution |
| 1080system.membus.trans_dist::WriteReq 9619 # Transaction distribution 1081system.membus.trans_dist::WriteResp 9619 # Transaction distribution | 1099system.membus.trans_dist::WriteReq 9619 # Transaction distribution 1100system.membus.trans_dist::WriteResp 9619 # Transaction distribution |
| 1082system.membus.trans_dist::Writeback 118100 # Transaction distribution | 1101system.membus.trans_dist::Writeback 118066 # Transaction distribution |
| 1083system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1084system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution | 1102system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1103system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution |
| 1085system.membus.trans_dist::UpgradeReq 161 # Transaction distribution 1086system.membus.trans_dist::UpgradeResp 161 # Transaction distribution 1087system.membus.trans_dist::ReadExReq 116519 # Transaction distribution 1088system.membus.trans_dist::ReadExResp 116519 # Transaction distribution | 1104system.membus.trans_dist::UpgradeReq 159 # Transaction distribution 1105system.membus.trans_dist::UpgradeResp 159 # Transaction distribution 1106system.membus.trans_dist::ReadExReq 116521 # Transaction distribution 1107system.membus.trans_dist::ReadExResp 116521 # Transaction distribution |
| 1089system.membus.trans_dist::BadAddressError 16 # Transaction distribution 1090system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) | 1108system.membus.trans_dist::BadAddressError 16 # Transaction distribution 1109system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) |
| 1091system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886949 # Packet count per connected master and slave (bytes) | 1110system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886877 # Packet count per connected master and slave (bytes) |
| 1092system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) | 1111system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) |
| 1093system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920079 # Packet count per connected master and slave (bytes) | 1112system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920007 # Packet count per connected master and slave (bytes) |
| 1094system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1095system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) | 1113system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1114system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) |
| 1096system.membus.pkt_count::total 1044883 # Packet count per connected master and slave (bytes) | 1115system.membus.pkt_count::total 1044811 # Packet count per connected master and slave (bytes) |
| 1097system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) | 1116system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) |
| 1098system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30814208 # Cumulative packet size per connected master and slave (bytes) 1099system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30858524 # Cumulative packet size per connected master and slave (bytes) | 1117system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30810944 # Cumulative packet size per connected master and slave (bytes) 1118system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30855260 # Cumulative packet size per connected master and slave (bytes) |
| 1100system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1101system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) | 1119system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1120system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) |
| 1102system.membus.pkt_size::total 36175580 # Cumulative packet size per connected master and slave (bytes) | 1121system.membus.pkt_size::total 36172316 # Cumulative packet size per connected master and slave (bytes) |
| 1103system.membus.snoops 433 # Total snoops (count) | 1122system.membus.snoops 433 # Total snoops (count) |
| 1104system.membus.snoop_fanout::samples 581756 # Request fanout histogram | 1123system.membus.snoop_fanout::samples 581705 # Request fanout histogram |
| 1105system.membus.snoop_fanout::mean 1 # Request fanout histogram 1106system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1107system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1108system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1124system.membus.snoop_fanout::mean 1 # Request fanout histogram 1125system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1126system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1127system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1109system.membus.snoop_fanout::1 581756 100.00% 100.00% # Request fanout histogram | 1128system.membus.snoop_fanout::1 581705 100.00% 100.00% # Request fanout histogram |
| 1110system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1111system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1112system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1113system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1129system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1130system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1131system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1132system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1114system.membus.snoop_fanout::total 581756 # Request fanout histogram 1115system.membus.reqLayer0.occupancy 30242500 # Layer occupancy (ticks) | 1133system.membus.snoop_fanout::total 581705 # Request fanout histogram 1134system.membus.reqLayer0.occupancy 29342000 # Layer occupancy (ticks) |
| 1116system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1135system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1117system.membus.reqLayer1.occupancy 1230317312 # Layer occupancy (ticks) | 1136system.membus.reqLayer1.occupancy 1229889311 # Layer occupancy (ticks) |
| 1118system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1137system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1119system.membus.reqLayer2.occupancy 21000 # Layer occupancy (ticks) | 1138system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) |
| 1120system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1139system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1121system.membus.respLayer1.occupancy 2160772841 # Layer occupancy (ticks) | 1140system.membus.respLayer1.occupancy 2160670093 # Layer occupancy (ticks) |
| 1122system.membus.respLayer1.utilization 0.1 # Layer utilization (%) | 1141system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1123system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) | 1142system.membus.respLayer2.occupancy 42495999 # Layer occupancy (ticks) |
| 1124system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1125system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1126system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1127system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1128system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1129system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1130system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1131system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- | 1143system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1144system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1145system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1146system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1147system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1148system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1149system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1150system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- |