| stats.txt (10726:8a20e2a1562d) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.887184 # Number of seconds simulated 4sim_ticks 1887184463000 # Number of ticks simulated 5final_tick 1887184463000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.887184 # Number of seconds simulated 4sim_ticks 1887184463000 # Number of ticks simulated 5final_tick 1887184463000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 275099 # Simulator instruction rate (inst/s) 8host_op_rate 275099 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9249537203 # Simulator tick rate (ticks/s) 10host_mem_usage 373576 # Number of bytes of host memory used 11host_seconds 204.03 # Real time elapsed on the host | 7host_inst_rate 272052 # Simulator instruction rate (inst/s) 8host_op_rate 272052 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9147074399 # Simulator tick rate (ticks/s) 10host_mem_usage 373996 # Number of bytes of host memory used 11host_seconds 206.32 # Real time elapsed on the host |
| 12sim_insts 56128524 # Number of instructions simulated 13sim_ops 56128524 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 1052352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25913536 # Number of bytes read from this memory --- 21 unchanged lines hidden (view full) --- 41system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17736441 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 404899 # Number of read requests accepted 44system.physmem.writeReqs 159652 # Number of write requests accepted 45system.physmem.readBursts 404899 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 159652 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25907328 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue | 12sim_insts 56128524 # Number of instructions simulated 13sim_ops 56128524 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 1052352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25913536 # Number of bytes read from this memory --- 21 unchanged lines hidden (view full) --- 41system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17736441 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 404899 # Number of read requests accepted 44system.physmem.writeReqs 159652 # Number of write requests accepted 45system.physmem.readBursts 404899 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 159652 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25907328 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue |
| 49system.physmem.bytesWritten 8556800 # Total number of bytes written to DRAM | 49system.physmem.bytesWritten 8555840 # Total number of bytes written to DRAM |
| 50system.physmem.bytesReadSys 25913536 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10217728 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue | 50system.physmem.bytesReadSys 25913536 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10217728 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue |
| 53system.physmem.mergedWrBursts 25922 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write | 53system.physmem.mergedWrBursts 25937 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 159 # Number of requests that are neither read nor write |
| 55system.physmem.perBankRdBursts::0 25492 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25732 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25844 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25788 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25096 # Per bank write bursts 60system.physmem.perBankRdBursts::5 25019 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24724 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24556 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25196 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25300 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25394 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24993 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24525 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25570 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25834 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25739 # Per bank write bursts 71system.physmem.perBankWrBursts::0 8904 # Per bank write bursts 72system.physmem.perBankWrBursts::1 8550 # Per bank write bursts | 55system.physmem.perBankRdBursts::0 25492 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25732 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25844 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25788 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25096 # Per bank write bursts 60system.physmem.perBankRdBursts::5 25019 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24724 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24556 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25196 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25300 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25394 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24993 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24525 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25570 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25834 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25739 # Per bank write bursts 71system.physmem.perBankWrBursts::0 8904 # Per bank write bursts 72system.physmem.perBankWrBursts::1 8550 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::2 9125 # Per bank write bursts 74system.physmem.perBankWrBursts::3 8822 # Per bank write bursts | 73system.physmem.perBankWrBursts::2 9134 # Per bank write bursts 74system.physmem.perBankWrBursts::3 8817 # Per bank write bursts |
| 75system.physmem.perBankWrBursts::4 8179 # Per bank write bursts 76system.physmem.perBankWrBursts::5 8016 # Per bank write bursts 77system.physmem.perBankWrBursts::6 7555 # Per bank write bursts | 75system.physmem.perBankWrBursts::4 8179 # Per bank write bursts 76system.physmem.perBankWrBursts::5 8016 # Per bank write bursts 77system.physmem.perBankWrBursts::6 7555 # Per bank write bursts |
| 78system.physmem.perBankWrBursts::7 7379 # Per bank write bursts | 78system.physmem.perBankWrBursts::7 7380 # Per bank write bursts |
| 79system.physmem.perBankWrBursts::8 8271 # Per bank write bursts 80system.physmem.perBankWrBursts::9 7751 # Per bank write bursts 81system.physmem.perBankWrBursts::10 8147 # Per bank write bursts | 79system.physmem.perBankWrBursts::8 8271 # Per bank write bursts 80system.physmem.perBankWrBursts::9 7751 # Per bank write bursts 81system.physmem.perBankWrBursts::10 8147 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::11 7873 # Per bank write bursts 83system.physmem.perBankWrBursts::12 8188 # Per bank write bursts 84system.physmem.perBankWrBursts::13 9058 # Per bank write bursts | 82system.physmem.perBankWrBursts::11 7871 # Per bank write bursts 83system.physmem.perBankWrBursts::12 8181 # Per bank write bursts 84system.physmem.perBankWrBursts::13 9046 # Per bank write bursts |
| 85system.physmem.perBankWrBursts::14 9003 # Per bank write bursts | 85system.physmem.perBankWrBursts::14 9003 # Per bank write bursts |
| 86system.physmem.perBankWrBursts::15 8879 # Per bank write bursts | 86system.physmem.perBankWrBursts::15 8880 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 88system.physmem.numWrRetry 49 # Number of times write queue was full causing retry | 88system.physmem.numWrRetry 48 # Number of times write queue was full causing retry |
| 89system.physmem.totGap 1887175688500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 404899 # Read request sizes (log2) --- 47 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1116 # What write queue length does an incoming req see | 89system.physmem.totGap 1887175688500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 404899 # Read request sizes (log2) --- 47 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1116 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::16 1823 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 5859 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 5540 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 5570 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 5709 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5633 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5486 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5467 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 5625 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 5831 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 6839 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 6092 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6407 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 7561 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6547 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6436 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5994 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 1243 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 769 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 1207 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 1362 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 1280 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 845 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1622 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 1798 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1564 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1800 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1975 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1915 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 2152 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 2564 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 2779 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 2158 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 1660 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 1251 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 773 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::16 1878 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 5779 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 5566 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 5580 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 5702 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5645 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5477 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5437 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 5641 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 5825 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 6756 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 6161 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6363 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 7635 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6502 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6461 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5991 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 1224 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 780 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 1179 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 1384 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 1265 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 883 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1555 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 1873 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1560 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1827 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1983 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1921 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 2157 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 2541 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 2774 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 2169 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 1666 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 1329 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 1241 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 764 # What write queue length does an incoming req see |
| 189system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see | 189system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see |
| 190system.physmem.wrQLenPdf::54 298 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 240 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 268 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 209 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 154 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see | 190system.physmem.wrQLenPdf::54 299 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 261 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 147 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 161 # What write queue length does an incoming req see |
| 197system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see | 197system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see |
| 198system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see | 198system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see |
| 200system.physmem.bytesPerActivate::samples 64790 # Bytes accessed per row activation | 200system.physmem.bytesPerActivate::samples 64790 # Bytes accessed per row activation |
| 201system.physmem.bytesPerActivate::mean 531.935916 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 325.040765 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 415.485108 # Bytes accessed per row activation | 201system.physmem.bytesPerActivate::mean 531.921099 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 325.032687 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 415.479352 # Bytes accessed per row activation |
| 204system.physmem.bytesPerActivate::0-127 14695 22.68% 22.68% # Bytes accessed per row activation | 204system.physmem.bytesPerActivate::0-127 14695 22.68% 22.68% # Bytes accessed per row activation |
| 205system.physmem.bytesPerActivate::128-255 10955 16.91% 39.59% # Bytes accessed per row activation | 205system.physmem.bytesPerActivate::128-255 10956 16.91% 39.59% # Bytes accessed per row activation |
| 206system.physmem.bytesPerActivate::256-383 5460 8.43% 48.02% # Bytes accessed per row activation | 206system.physmem.bytesPerActivate::256-383 5460 8.43% 48.02% # Bytes accessed per row activation |
| 207system.physmem.bytesPerActivate::384-511 3097 4.78% 52.80% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2483 3.83% 56.63% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1877 2.90% 59.53% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1493 2.30% 61.83% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1431 2.21% 64.04% # Bytes accessed per row activation | 207system.physmem.bytesPerActivate::384-511 3096 4.78% 52.80% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2482 3.83% 56.63% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1882 2.90% 59.53% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1491 2.30% 61.83% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1429 2.21% 64.04% # Bytes accessed per row activation |
| 212system.physmem.bytesPerActivate::1024-1151 23299 35.96% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 64790 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4900 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 82.608776 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 3017.174786 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 4897 99.94% 99.94% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::total 4900 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 4900 # Writes before turning the bus around for reads | 212system.physmem.bytesPerActivate::1024-1151 23299 35.96% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 64790 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4900 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 82.608776 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 3017.174786 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 4897 99.94% 99.94% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::total 4900 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 4900 # Writes before turning the bus around for reads |
| 223system.physmem.wrPerTurnAround::mean 27.285714 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 18.337905 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 63.692079 # Writes before turning the bus around for reads | 223system.physmem.wrPerTurnAround::mean 27.282653 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 18.334547 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 63.863816 # Writes before turning the bus around for reads |
| 226system.physmem.wrPerTurnAround::0-31 4662 95.14% 95.14% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-63 56 1.14% 96.29% # Writes before turning the bus around for reads | 226system.physmem.wrPerTurnAround::0-31 4662 95.14% 95.14% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-63 56 1.14% 96.29% # Writes before turning the bus around for reads |
| 228system.physmem.wrPerTurnAround::64-95 11 0.22% 96.51% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::96-127 6 0.12% 96.63% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::128-159 26 0.53% 97.16% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::160-191 25 0.51% 97.67% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::192-223 16 0.33% 98.00% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::224-255 2 0.04% 98.04% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::256-287 6 0.12% 98.16% # Writes before turning the bus around for reads | 228system.physmem.wrPerTurnAround::64-95 12 0.24% 96.53% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::96-127 6 0.12% 96.65% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::128-159 26 0.53% 97.18% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::160-191 25 0.51% 97.69% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::192-223 16 0.33% 98.02% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::224-255 3 0.06% 98.08% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::256-287 4 0.08% 98.16% # Writes before turning the bus around for reads |
| 235system.physmem.wrPerTurnAround::288-319 8 0.16% 98.33% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::320-351 21 0.43% 98.76% # Writes before turning the bus around for reads | 235system.physmem.wrPerTurnAround::288-319 8 0.16% 98.33% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::320-351 21 0.43% 98.76% # Writes before turning the bus around for reads |
| 237system.physmem.wrPerTurnAround::352-383 21 0.43% 99.18% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::384-415 2 0.04% 99.22% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::448-479 6 0.12% 99.35% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::480-511 7 0.14% 99.49% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::512-543 9 0.18% 99.67% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::544-575 5 0.10% 99.78% # Writes before turning the bus around for reads | 237system.physmem.wrPerTurnAround::352-383 20 0.41% 99.16% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::384-415 2 0.04% 99.20% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::448-479 6 0.12% 99.33% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::480-511 7 0.14% 99.47% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::512-543 9 0.18% 99.65% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::544-575 6 0.12% 99.78% # Writes before turning the bus around for reads |
| 243system.physmem.wrPerTurnAround::672-703 3 0.06% 99.84% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::704-735 7 0.14% 99.98% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::1088-1119 1 0.02% 100.00% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::total 4900 # Writes before turning the bus around for reads | 243system.physmem.wrPerTurnAround::672-703 3 0.06% 99.84% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::704-735 7 0.14% 99.98% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::1088-1119 1 0.02% 100.00% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::total 4900 # Writes before turning the bus around for reads |
| 247system.physmem.totQLat 2145870750 # Total ticks spent queuing 248system.physmem.totMemAccLat 9735908250 # Total ticks spent from burst creation until serviced by the DRAM | 247system.physmem.totQLat 2145936500 # Total ticks spent queuing 248system.physmem.totMemAccLat 9735974000 # Total ticks spent from burst creation until serviced by the DRAM |
| 249system.physmem.totBusLat 2024010000 # Total ticks spent in databus transfers | 249system.physmem.totBusLat 2024010000 # Total ticks spent in databus transfers |
| 250system.physmem.avgQLat 5301.04 # Average queueing delay per DRAM burst | 250system.physmem.avgQLat 5301.20 # Average queueing delay per DRAM burst |
| 251system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 251system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 252system.physmem.avgMemAccLat 24051.04 # Average memory access latency per DRAM burst | 252system.physmem.avgMemAccLat 24051.20 # Average memory access latency per DRAM burst |
| 253system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s 254system.physmem.avgWrBW 4.53 # Average achieved write bandwidth in MiByte/s 255system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s 256system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s 257system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 258system.physmem.busUtil 0.14 # Data bus utilization in percentage 259system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 260system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes 261system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 262system.physmem.avgWrQLen 25.13 # Average write queue length when enqueuing 263system.physmem.readRowHits 363622 # Number of row buffer hits during reads | 253system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s 254system.physmem.avgWrBW 4.53 # Average achieved write bandwidth in MiByte/s 255system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s 256system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s 257system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 258system.physmem.busUtil 0.14 # Data bus utilization in percentage 259system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 260system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes 261system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 262system.physmem.avgWrQLen 25.13 # Average write queue length when enqueuing 263system.physmem.readRowHits 363622 # Number of row buffer hits during reads |
| 264system.physmem.writeRowHits 110090 # Number of row buffer hits during writes | 264system.physmem.writeRowHits 110075 # Number of row buffer hits during writes |
| 265system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads 266system.physmem.writeRowHitRate 82.32 # Row buffer hit rate for writes 267system.physmem.avgGap 3342790.44 # Average gap between requests 268system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined | 265system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads 266system.physmem.writeRowHitRate 82.32 # Row buffer hit rate for writes 267system.physmem.avgGap 3342790.44 # Average gap between requests 268system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined |
| 269system.physmem_0.actEnergy 238971600 # Energy for activate commands per rank (pJ) 270system.physmem_0.preEnergy 130391250 # Energy for precharge commands per rank (pJ) | 269system.physmem_0.actEnergy 238979160 # Energy for activate commands per rank (pJ) 270system.physmem_0.preEnergy 130395375 # Energy for precharge commands per rank (pJ) |
| 271system.physmem_0.readEnergy 1577557800 # Energy for read commands per rank (pJ) | 271system.physmem_0.readEnergy 1577557800 # Energy for read commands per rank (pJ) |
| 272system.physmem_0.writeEnergy 431114400 # Energy for write commands per rank (pJ) | 272system.physmem_0.writeEnergy 431146800 # Energy for write commands per rank (pJ) |
| 273system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) | 273system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) |
| 274system.physmem_0.actBackEnergy 60578040195 # Energy for active background per rank (pJ) 275system.physmem_0.preBackEnergy 1079167578750 # Energy for precharge background per rank (pJ) 276system.physmem_0.totalEnergy 1265384866875 # Total energy per rank (pJ) 277system.physmem_0.averagePower 670.517315 # Core power per rank (mW) 278system.physmem_0.memoryStateTime::IDLE 1795079554966 # Time in different power states | 274system.physmem_0.actBackEnergy 60577818750 # Energy for active background per rank (pJ) 275system.physmem_0.preBackEnergy 1079167773000 # Energy for precharge background per rank (pJ) 276system.physmem_0.totalEnergy 1265384883765 # Total energy per rank (pJ) 277system.physmem_0.averagePower 670.517324 # Core power per rank (mW) 278system.physmem_0.memoryStateTime::IDLE 1795079851716 # Time in different power states |
| 279system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states 280system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 279system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states 280system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 281system.physmem_0.memoryStateTime::ACT 29080496284 # Time in different power states | 281system.physmem_0.memoryStateTime::ACT 29080199534 # Time in different power states |
| 282system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 282system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 283system.physmem_1.actEnergy 250840800 # Energy for activate commands per rank (pJ) 284system.physmem_1.preEnergy 136867500 # Energy for precharge commands per rank (pJ) | 283system.physmem_1.actEnergy 250833240 # Energy for activate commands per rank (pJ) 284system.physmem_1.preEnergy 136863375 # Energy for precharge commands per rank (pJ) |
| 285system.physmem_1.readEnergy 1579897800 # Energy for read commands per rank (pJ) | 285system.physmem_1.readEnergy 1579897800 # Energy for read commands per rank (pJ) |
| 286system.physmem_1.writeEnergy 435261600 # Energy for write commands per rank (pJ) | 286system.physmem_1.writeEnergy 435132000 # Energy for write commands per rank (pJ) |
| 287system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) | 287system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) |
| 288system.physmem_1.actBackEnergy 61601133195 # Energy for active background per rank (pJ) 289system.physmem_1.preBackEnergy 1078270137000 # Energy for precharge background per rank (pJ) 290system.physmem_1.totalEnergy 1265535350775 # Total energy per rank (pJ) 291system.physmem_1.averagePower 670.597050 # Core power per rank (mW) 292system.physmem_1.memoryStateTime::IDLE 1793586337716 # Time in different power states | 288system.physmem_1.actBackEnergy 61600331205 # Energy for active background per rank (pJ) 289system.physmem_1.preBackEnergy 1078270840500 # Energy for precharge background per rank (pJ) 290system.physmem_1.totalEnergy 1265535111000 # Total energy per rank (pJ) 291system.physmem_1.averagePower 670.596923 # Core power per rank (mW) 292system.physmem_1.memoryStateTime::IDLE 1793587329216 # Time in different power states |
| 293system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states 294system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 293system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states 294system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 295system.physmem_1.memoryStateTime::ACT 30573727284 # Time in different power states | 295system.physmem_1.memoryStateTime::ACT 30572735784 # Time in different power states |
| 296system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 296system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 297system.cpu.branchPred.lookups 15007831 # Number of BP lookups | 297system.cpu.branchPred.lookups 15007833 # Number of BP lookups |
| 298system.cpu.branchPred.condPredicted 13016266 # Number of conditional branches predicted 299system.cpu.branchPred.condIncorrect 375462 # Number of conditional branches incorrect | 298system.cpu.branchPred.condPredicted 13016266 # Number of conditional branches predicted 299system.cpu.branchPred.condIncorrect 375462 # Number of conditional branches incorrect |
| 300system.cpu.branchPred.BTBLookups 9968114 # Number of BTB lookups | 300system.cpu.branchPred.BTBLookups 9968116 # Number of BTB lookups |
| 301system.cpu.branchPred.BTBHits 5203851 # Number of BTB hits 302system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 301system.cpu.branchPred.BTBHits 5203851 # Number of BTB hits 302system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 303system.cpu.branchPred.BTBHitPct 52.204971 # BTB Hit Percentage | 303system.cpu.branchPred.BTBHitPct 52.204960 # BTB Hit Percentage |
| 304system.cpu.branchPred.usedRAS 809053 # Number of times the RAS was used to get a target. 305system.cpu.branchPred.RASInCorrect 32834 # Number of incorrect RAS predictions. 306system.cpu_clk_domain.clock 500 # Clock period in ticks 307system.cpu.dtb.fetch_hits 0 # ITB hits 308system.cpu.dtb.fetch_misses 0 # ITB misses 309system.cpu.dtb.fetch_acv 0 # ITB acv 310system.cpu.dtb.fetch_accesses 0 # ITB accesses | 304system.cpu.branchPred.usedRAS 809053 # Number of times the RAS was used to get a target. 305system.cpu.branchPred.RASInCorrect 32834 # Number of incorrect RAS predictions. 306system.cpu_clk_domain.clock 500 # Clock period in ticks 307system.cpu.dtb.fetch_hits 0 # ITB hits 308system.cpu.dtb.fetch_misses 0 # ITB misses 309system.cpu.dtb.fetch_acv 0 # ITB acv 310system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 311system.cpu.dtb.read_hits 9242509 # DTB read hits | 311system.cpu.dtb.read_hits 9242504 # DTB read hits |
| 312system.cpu.dtb.read_misses 17824 # DTB read misses 313system.cpu.dtb.read_acv 211 # DTB read access violations 314system.cpu.dtb.read_accesses 766347 # DTB read accesses | 312system.cpu.dtb.read_misses 17824 # DTB read misses 313system.cpu.dtb.read_acv 211 # DTB read access violations 314system.cpu.dtb.read_accesses 766347 # DTB read accesses |
| 315system.cpu.dtb.write_hits 6385998 # DTB write hits | 315system.cpu.dtb.write_hits 6386002 # DTB write hits |
| 316system.cpu.dtb.write_misses 2322 # DTB write misses 317system.cpu.dtb.write_acv 159 # DTB write access violations 318system.cpu.dtb.write_accesses 298454 # DTB write accesses | 316system.cpu.dtb.write_misses 2322 # DTB write misses 317system.cpu.dtb.write_acv 159 # DTB write access violations 318system.cpu.dtb.write_accesses 298454 # DTB write accesses |
| 319system.cpu.dtb.data_hits 15628507 # DTB hits | 319system.cpu.dtb.data_hits 15628506 # DTB hits |
| 320system.cpu.dtb.data_misses 20146 # DTB misses 321system.cpu.dtb.data_acv 370 # DTB access violations 322system.cpu.dtb.data_accesses 1064801 # DTB accesses 323system.cpu.itb.fetch_hits 4019475 # ITB hits 324system.cpu.itb.fetch_misses 6849 # ITB misses 325system.cpu.itb.fetch_acv 693 # ITB acv 326system.cpu.itb.fetch_accesses 4026324 # ITB accesses 327system.cpu.itb.read_hits 0 # DTB read hits 328system.cpu.itb.read_misses 0 # DTB read misses 329system.cpu.itb.read_acv 0 # DTB read access violations 330system.cpu.itb.read_accesses 0 # DTB read accesses 331system.cpu.itb.write_hits 0 # DTB write hits 332system.cpu.itb.write_misses 0 # DTB write misses 333system.cpu.itb.write_acv 0 # DTB write access violations 334system.cpu.itb.write_accesses 0 # DTB write accesses 335system.cpu.itb.data_hits 0 # DTB hits 336system.cpu.itb.data_misses 0 # DTB misses 337system.cpu.itb.data_acv 0 # DTB access violations 338system.cpu.itb.data_accesses 0 # DTB accesses | 320system.cpu.dtb.data_misses 20146 # DTB misses 321system.cpu.dtb.data_acv 370 # DTB access violations 322system.cpu.dtb.data_accesses 1064801 # DTB accesses 323system.cpu.itb.fetch_hits 4019475 # ITB hits 324system.cpu.itb.fetch_misses 6849 # ITB misses 325system.cpu.itb.fetch_acv 693 # ITB acv 326system.cpu.itb.fetch_accesses 4026324 # ITB accesses 327system.cpu.itb.read_hits 0 # DTB read hits 328system.cpu.itb.read_misses 0 # DTB read misses 329system.cpu.itb.read_acv 0 # DTB read access violations 330system.cpu.itb.read_accesses 0 # DTB read accesses 331system.cpu.itb.write_hits 0 # DTB write hits 332system.cpu.itb.write_misses 0 # DTB write misses 333system.cpu.itb.write_acv 0 # DTB write access violations 334system.cpu.itb.write_accesses 0 # DTB write accesses 335system.cpu.itb.data_hits 0 # DTB hits 336system.cpu.itb.data_misses 0 # DTB misses 337system.cpu.itb.data_acv 0 # DTB access violations 338system.cpu.itb.data_accesses 0 # DTB accesses |
| 339system.cpu.numCycles 180833283 # number of cpu cycles simulated | 339system.cpu.numCycles 180833533 # number of cpu cycles simulated |
| 340system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 341system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 342system.cpu.committedInsts 56128524 # Number of instructions committed 343system.cpu.committedOps 56128524 # Number of ops (including micro ops) committed | 340system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 341system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 342system.cpu.committedInsts 56128524 # Number of instructions committed 343system.cpu.committedOps 56128524 # Number of ops (including micro ops) committed |
| 344system.cpu.discardedOps 2493053 # Number of ops (including micro ops) which were discarded before commit | 344system.cpu.discardedOps 2493054 # Number of ops (including micro ops) which were discarded before commit |
| 345system.cpu.numFetchSuspends 5493 # Number of times Execute suspended instruction fetching | 345system.cpu.numFetchSuspends 5493 # Number of times Execute suspended instruction fetching |
| 346system.cpu.quiesceCycles 3593535643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 347system.cpu.cpi 3.221772 # CPI: cycles per instruction | 346system.cpu.quiesceCycles 3593535393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 347system.cpu.cpi 3.221776 # CPI: cycles per instruction |
| 348system.cpu.ipc 0.310388 # IPC: instructions per cycle 349system.cpu.kern.inst.arm 0 # number of arm instructions executed 350system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 351system.cpu.kern.inst.hwrei 211489 # number of hwrei instructions executed 352system.cpu.kern.ipl_count::0 74799 40.94% 40.94% # number of times we switched to this ipl 353system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl 354system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl 355system.cpu.kern.ipl_count::31 105874 57.95% 100.00% # number of times we switched to this ipl 356system.cpu.kern.ipl_count::total 182705 # number of times we switched to this ipl 357system.cpu.kern.ipl_good::0 73432 49.32% 49.32% # number of times we switched to this ipl from a different ipl 358system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 359system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl 360system.cpu.kern.ipl_good::31 73432 49.32% 100.00% # number of times we switched to this ipl from a different ipl 361system.cpu.kern.ipl_good::total 148896 # number of times we switched to this ipl from a different ipl | 348system.cpu.ipc 0.310388 # IPC: instructions per cycle 349system.cpu.kern.inst.arm 0 # number of arm instructions executed 350system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 351system.cpu.kern.inst.hwrei 211489 # number of hwrei instructions executed 352system.cpu.kern.ipl_count::0 74799 40.94% 40.94% # number of times we switched to this ipl 353system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl 354system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl 355system.cpu.kern.ipl_count::31 105874 57.95% 100.00% # number of times we switched to this ipl 356system.cpu.kern.ipl_count::total 182705 # number of times we switched to this ipl 357system.cpu.kern.ipl_good::0 73432 49.32% 49.32% # number of times we switched to this ipl from a different ipl 358system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 359system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl 360system.cpu.kern.ipl_good::31 73432 49.32% 100.00% # number of times we switched to this ipl from a different ipl 361system.cpu.kern.ipl_good::total 148896 # number of times we switched to this ipl from a different ipl |
| 362system.cpu.kern.ipl_ticks::0 1834551091000 97.21% 97.21% # number of cycles we spent at this ipl | 362system.cpu.kern.ipl_ticks::0 1834551053500 97.21% 97.21% # number of cycles we spent at this ipl |
| 363system.cpu.kern.ipl_ticks::21 80458000 0.00% 97.22% # number of cycles we spent at this ipl 364system.cpu.kern.ipl_ticks::22 676198500 0.04% 97.25% # number of cycles we spent at this ipl | 363system.cpu.kern.ipl_ticks::21 80458000 0.00% 97.22% # number of cycles we spent at this ipl 364system.cpu.kern.ipl_ticks::22 676198500 0.04% 97.25% # number of cycles we spent at this ipl |
| 365system.cpu.kern.ipl_ticks::31 51875728000 2.75% 100.00% # number of cycles we spent at this ipl | 365system.cpu.kern.ipl_ticks::31 51875765500 2.75% 100.00% # number of cycles we spent at this ipl |
| 366system.cpu.kern.ipl_ticks::total 1887183475500 # number of cycles we spent at this ipl 367system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl 368system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 369system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 370system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl 371system.cpu.kern.ipl_used::total 0.814953 # fraction of swpipl calls that actually changed the ipl 372system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 373system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed --- 48 unchanged lines hidden (view full) --- 422system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches 423system.cpu.kern.mode_good::kernel 1906 424system.cpu.kern.mode_good::user 1739 425system.cpu.kern.mode_good::idle 167 426system.cpu.kern.mode_switch_good::kernel 0.324536 # fraction of useful protection mode switches 427system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 428system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches 429system.cpu.kern.mode_switch_good::total 0.392949 # fraction of useful protection mode switches | 366system.cpu.kern.ipl_ticks::total 1887183475500 # number of cycles we spent at this ipl 367system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl 368system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 369system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 370system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl 371system.cpu.kern.ipl_used::total 0.814953 # fraction of swpipl calls that actually changed the ipl 372system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 373system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed --- 48 unchanged lines hidden (view full) --- 422system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches 423system.cpu.kern.mode_good::kernel 1906 424system.cpu.kern.mode_good::user 1739 425system.cpu.kern.mode_good::idle 167 426system.cpu.kern.mode_switch_good::kernel 0.324536 # fraction of useful protection mode switches 427system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 428system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches 429system.cpu.kern.mode_switch_good::total 0.392949 # fraction of useful protection mode switches |
| 430system.cpu.kern.mode_ticks::kernel 36591764000 1.94% 1.94% # number of ticks spent at the given mode 431system.cpu.kern.mode_ticks::user 4134630500 0.22% 2.16% # number of ticks spent at the given mode 432system.cpu.kern.mode_ticks::idle 1846457071000 97.84% 100.00% # number of ticks spent at the given mode | 430system.cpu.kern.mode_ticks::kernel 36591863000 1.94% 1.94% # number of ticks spent at the given mode 431system.cpu.kern.mode_ticks::user 4134622500 0.22% 2.16% # number of ticks spent at the given mode 432system.cpu.kern.mode_ticks::idle 1846456980000 97.84% 100.00% # number of ticks spent at the given mode |
| 433system.cpu.kern.swap_context 4171 # number of times the context was actually changed | 433system.cpu.kern.swap_context 4171 # number of times the context was actually changed |
| 434system.cpu.tickCycles 84552258 # Number of cycles that the object actually ticked 435system.cpu.idleCycles 96281025 # Total number of cycles that the object has spent stopped 436system.cpu.dcache.tags.replacements 1395325 # number of replacements | 434system.cpu.tickCycles 84552243 # Number of cycles that the object actually ticked 435system.cpu.idleCycles 96281290 # Total number of cycles that the object has spent stopped 436system.cpu.dcache.tags.replacements 1395323 # number of replacements |
| 437system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use | 437system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use |
| 438system.cpu.dcache.tags.total_refs 13774282 # Total number of references to valid blocks. 439system.cpu.dcache.tags.sampled_refs 1395837 # Sample count of references to valid blocks. 440system.cpu.dcache.tags.avg_refs 9.868116 # Average number of references to valid blocks. | 438system.cpu.dcache.tags.total_refs 13774277 # Total number of references to valid blocks. 439system.cpu.dcache.tags.sampled_refs 1395835 # Sample count of references to valid blocks. 440system.cpu.dcache.tags.avg_refs 9.868127 # Average number of references to valid blocks. |
| 441system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. 442system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor 443system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy 444system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy 445system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 446system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 447system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 449system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 441system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. 442system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor 443system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy 444system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy 445system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 446system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 447system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 449system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 450system.cpu.dcache.tags.tag_accesses 63660758 # Number of tag accesses 451system.cpu.dcache.tags.data_accesses 63660758 # Number of data accesses 452system.cpu.dcache.ReadReq_hits::cpu.data 7815437 # number of ReadReq hits 453system.cpu.dcache.ReadReq_hits::total 7815437 # number of ReadReq hits | 450system.cpu.dcache.tags.tag_accesses 63660728 # Number of tag accesses 451system.cpu.dcache.tags.data_accesses 63660728 # Number of data accesses 452system.cpu.dcache.ReadReq_hits::cpu.data 7815432 # number of ReadReq hits 453system.cpu.dcache.ReadReq_hits::total 7815432 # number of ReadReq hits |
| 454system.cpu.dcache.WriteReq_hits::cpu.data 5576995 # number of WriteReq hits 455system.cpu.dcache.WriteReq_hits::total 5576995 # number of WriteReq hits 456system.cpu.dcache.LoadLockedReq_hits::cpu.data 182818 # number of LoadLockedReq hits 457system.cpu.dcache.LoadLockedReq_hits::total 182818 # number of LoadLockedReq hits 458system.cpu.dcache.StoreCondReq_hits::cpu.data 198995 # number of StoreCondReq hits 459system.cpu.dcache.StoreCondReq_hits::total 198995 # number of StoreCondReq hits | 454system.cpu.dcache.WriteReq_hits::cpu.data 5576995 # number of WriteReq hits 455system.cpu.dcache.WriteReq_hits::total 5576995 # number of WriteReq hits 456system.cpu.dcache.LoadLockedReq_hits::cpu.data 182818 # number of LoadLockedReq hits 457system.cpu.dcache.LoadLockedReq_hits::total 182818 # number of LoadLockedReq hits 458system.cpu.dcache.StoreCondReq_hits::cpu.data 198995 # number of StoreCondReq hits 459system.cpu.dcache.StoreCondReq_hits::total 198995 # number of StoreCondReq hits |
| 460system.cpu.dcache.demand_hits::cpu.data 13392432 # number of demand (read+write) hits 461system.cpu.dcache.demand_hits::total 13392432 # number of demand (read+write) hits 462system.cpu.dcache.overall_hits::cpu.data 13392432 # number of overall hits 463system.cpu.dcache.overall_hits::total 13392432 # number of overall hits 464system.cpu.dcache.ReadReq_misses::cpu.data 1201539 # number of ReadReq misses 465system.cpu.dcache.ReadReq_misses::total 1201539 # number of ReadReq misses | 460system.cpu.dcache.demand_hits::cpu.data 13392427 # number of demand (read+write) hits 461system.cpu.dcache.demand_hits::total 13392427 # number of demand (read+write) hits 462system.cpu.dcache.overall_hits::cpu.data 13392427 # number of overall hits 463system.cpu.dcache.overall_hits::total 13392427 # number of overall hits 464system.cpu.dcache.ReadReq_misses::cpu.data 1201537 # number of ReadReq misses 465system.cpu.dcache.ReadReq_misses::total 1201537 # number of ReadReq misses |
| 466system.cpu.dcache.WriteReq_misses::cpu.data 573249 # number of WriteReq misses 467system.cpu.dcache.WriteReq_misses::total 573249 # number of WriteReq misses 468system.cpu.dcache.LoadLockedReq_misses::cpu.data 17197 # number of LoadLockedReq misses 469system.cpu.dcache.LoadLockedReq_misses::total 17197 # number of LoadLockedReq misses | 466system.cpu.dcache.WriteReq_misses::cpu.data 573249 # number of WriteReq misses 467system.cpu.dcache.WriteReq_misses::total 573249 # number of WriteReq misses 468system.cpu.dcache.LoadLockedReq_misses::cpu.data 17197 # number of LoadLockedReq misses 469system.cpu.dcache.LoadLockedReq_misses::total 17197 # number of LoadLockedReq misses |
| 470system.cpu.dcache.demand_misses::cpu.data 1774788 # number of demand (read+write) misses 471system.cpu.dcache.demand_misses::total 1774788 # number of demand (read+write) misses 472system.cpu.dcache.overall_misses::cpu.data 1774788 # number of overall misses 473system.cpu.dcache.overall_misses::total 1774788 # number of overall misses 474system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999838250 # number of ReadReq miss cycles 475system.cpu.dcache.ReadReq_miss_latency::total 32999838250 # number of ReadReq miss cycles 476system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461596052 # number of WriteReq miss cycles 477system.cpu.dcache.WriteReq_miss_latency::total 22461596052 # number of WriteReq miss cycles | 470system.cpu.dcache.demand_misses::cpu.data 1774786 # number of demand (read+write) misses 471system.cpu.dcache.demand_misses::total 1774786 # number of demand (read+write) misses 472system.cpu.dcache.overall_misses::cpu.data 1774786 # number of overall misses 473system.cpu.dcache.overall_misses::total 1774786 # number of overall misses 474system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999736250 # number of ReadReq miss cycles 475system.cpu.dcache.ReadReq_miss_latency::total 32999736250 # number of ReadReq miss cycles 476system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461890056 # number of WriteReq miss cycles 477system.cpu.dcache.WriteReq_miss_latency::total 22461890056 # number of WriteReq miss cycles |
| 478system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230671750 # number of LoadLockedReq miss cycles 479system.cpu.dcache.LoadLockedReq_miss_latency::total 230671750 # number of LoadLockedReq miss cycles | 478system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230671750 # number of LoadLockedReq miss cycles 479system.cpu.dcache.LoadLockedReq_miss_latency::total 230671750 # number of LoadLockedReq miss cycles |
| 480system.cpu.dcache.demand_miss_latency::cpu.data 55461434302 # number of demand (read+write) miss cycles 481system.cpu.dcache.demand_miss_latency::total 55461434302 # number of demand (read+write) miss cycles 482system.cpu.dcache.overall_miss_latency::cpu.data 55461434302 # number of overall miss cycles 483system.cpu.dcache.overall_miss_latency::total 55461434302 # number of overall miss cycles 484system.cpu.dcache.ReadReq_accesses::cpu.data 9016976 # number of ReadReq accesses(hits+misses) 485system.cpu.dcache.ReadReq_accesses::total 9016976 # number of ReadReq accesses(hits+misses) | 480system.cpu.dcache.demand_miss_latency::cpu.data 55461626306 # number of demand (read+write) miss cycles 481system.cpu.dcache.demand_miss_latency::total 55461626306 # number of demand (read+write) miss cycles 482system.cpu.dcache.overall_miss_latency::cpu.data 55461626306 # number of overall miss cycles 483system.cpu.dcache.overall_miss_latency::total 55461626306 # number of overall miss cycles 484system.cpu.dcache.ReadReq_accesses::cpu.data 9016969 # number of ReadReq accesses(hits+misses) 485system.cpu.dcache.ReadReq_accesses::total 9016969 # number of ReadReq accesses(hits+misses) |
| 486system.cpu.dcache.WriteReq_accesses::cpu.data 6150244 # number of WriteReq accesses(hits+misses) 487system.cpu.dcache.WriteReq_accesses::total 6150244 # number of WriteReq accesses(hits+misses) 488system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200015 # number of LoadLockedReq accesses(hits+misses) 489system.cpu.dcache.LoadLockedReq_accesses::total 200015 # number of LoadLockedReq accesses(hits+misses) 490system.cpu.dcache.StoreCondReq_accesses::cpu.data 198995 # number of StoreCondReq accesses(hits+misses) 491system.cpu.dcache.StoreCondReq_accesses::total 198995 # number of StoreCondReq accesses(hits+misses) | 486system.cpu.dcache.WriteReq_accesses::cpu.data 6150244 # number of WriteReq accesses(hits+misses) 487system.cpu.dcache.WriteReq_accesses::total 6150244 # number of WriteReq accesses(hits+misses) 488system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200015 # number of LoadLockedReq accesses(hits+misses) 489system.cpu.dcache.LoadLockedReq_accesses::total 200015 # number of LoadLockedReq accesses(hits+misses) 490system.cpu.dcache.StoreCondReq_accesses::cpu.data 198995 # number of StoreCondReq accesses(hits+misses) 491system.cpu.dcache.StoreCondReq_accesses::total 198995 # number of StoreCondReq accesses(hits+misses) |
| 492system.cpu.dcache.demand_accesses::cpu.data 15167220 # number of demand (read+write) accesses 493system.cpu.dcache.demand_accesses::total 15167220 # number of demand (read+write) accesses 494system.cpu.dcache.overall_accesses::cpu.data 15167220 # number of overall (read+write) accesses 495system.cpu.dcache.overall_accesses::total 15167220 # number of overall (read+write) accesses | 492system.cpu.dcache.demand_accesses::cpu.data 15167213 # number of demand (read+write) accesses 493system.cpu.dcache.demand_accesses::total 15167213 # number of demand (read+write) accesses 494system.cpu.dcache.overall_accesses::cpu.data 15167213 # number of overall (read+write) accesses 495system.cpu.dcache.overall_accesses::total 15167213 # number of overall (read+write) accesses |
| 496system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses 497system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses 498system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093208 # miss rate for WriteReq accesses 499system.cpu.dcache.WriteReq_miss_rate::total 0.093208 # miss rate for WriteReq accesses 500system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085979 # miss rate for LoadLockedReq accesses 501system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085979 # miss rate for LoadLockedReq accesses 502system.cpu.dcache.demand_miss_rate::cpu.data 0.117015 # miss rate for demand accesses 503system.cpu.dcache.demand_miss_rate::total 0.117015 # miss rate for demand accesses 504system.cpu.dcache.overall_miss_rate::cpu.data 0.117015 # miss rate for overall accesses 505system.cpu.dcache.overall_miss_rate::total 0.117015 # miss rate for overall accesses | 496system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses 497system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses 498system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093208 # miss rate for WriteReq accesses 499system.cpu.dcache.WriteReq_miss_rate::total 0.093208 # miss rate for WriteReq accesses 500system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085979 # miss rate for LoadLockedReq accesses 501system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085979 # miss rate for LoadLockedReq accesses 502system.cpu.dcache.demand_miss_rate::cpu.data 0.117015 # miss rate for demand accesses 503system.cpu.dcache.demand_miss_rate::total 0.117015 # miss rate for demand accesses 504system.cpu.dcache.overall_miss_rate::cpu.data 0.117015 # miss rate for overall accesses 505system.cpu.dcache.overall_miss_rate::total 0.117015 # miss rate for overall accesses |
| 506system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.641805 # average ReadReq miss latency 507system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.641805 # average ReadReq miss latency 508system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39182.965957 # average WriteReq miss latency 509system.cpu.dcache.WriteReq_avg_miss_latency::total 39182.965957 # average WriteReq miss latency | 506system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.602630 # average ReadReq miss latency 507system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.602630 # average ReadReq miss latency 508system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39183.478830 # average WriteReq miss latency 509system.cpu.dcache.WriteReq_avg_miss_latency::total 39183.478830 # average WriteReq miss latency |
| 510system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.487818 # average LoadLockedReq miss latency 511system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.487818 # average LoadLockedReq miss latency | 510system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.487818 # average LoadLockedReq miss latency 511system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.487818 # average LoadLockedReq miss latency |
| 512system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency 513system.cpu.dcache.demand_avg_miss_latency::total 31249.610828 # average overall miss latency 514system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency 515system.cpu.dcache.overall_avg_miss_latency::total 31249.610828 # average overall miss latency | 512system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency 513system.cpu.dcache.demand_avg_miss_latency::total 31249.754227 # average overall miss latency 514system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency 515system.cpu.dcache.overall_avg_miss_latency::total 31249.754227 # average overall miss latency |
| 516system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 517system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 518system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 519system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 520system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 521system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 522system.cpu.dcache.fast_writes 0 # number of fast writes performed 523system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 528system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268996 # number of WriteReq MSHR hits 529system.cpu.dcache.WriteReq_mshr_hits::total 268996 # number of WriteReq MSHR hits 530system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 531system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 532system.cpu.dcache.demand_mshr_hits::cpu.data 396104 # number of demand (read+write) MSHR hits 533system.cpu.dcache.demand_mshr_hits::total 396104 # number of demand (read+write) MSHR hits 534system.cpu.dcache.overall_mshr_hits::cpu.data 396104 # number of overall MSHR hits 535system.cpu.dcache.overall_mshr_hits::total 396104 # number of overall MSHR hits | 516system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 517system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 518system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 519system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 520system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 521system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 522system.cpu.dcache.fast_writes 0 # number of fast writes performed 523system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 528system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268996 # number of WriteReq MSHR hits 529system.cpu.dcache.WriteReq_mshr_hits::total 268996 # number of WriteReq MSHR hits 530system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 531system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 532system.cpu.dcache.demand_mshr_hits::cpu.data 396104 # number of demand (read+write) MSHR hits 533system.cpu.dcache.demand_mshr_hits::total 396104 # number of demand (read+write) MSHR hits 534system.cpu.dcache.overall_mshr_hits::cpu.data 396104 # number of overall MSHR hits 535system.cpu.dcache.overall_mshr_hits::total 396104 # number of overall MSHR hits |
| 536system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074431 # number of ReadReq MSHR misses 537system.cpu.dcache.ReadReq_mshr_misses::total 1074431 # number of ReadReq MSHR misses | 536system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074429 # number of ReadReq MSHR misses 537system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses |
| 538system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304253 # number of WriteReq MSHR misses 539system.cpu.dcache.WriteReq_mshr_misses::total 304253 # number of WriteReq MSHR misses 540system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17194 # number of LoadLockedReq MSHR misses 541system.cpu.dcache.LoadLockedReq_mshr_misses::total 17194 # number of LoadLockedReq MSHR misses | 538system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304253 # number of WriteReq MSHR misses 539system.cpu.dcache.WriteReq_mshr_misses::total 304253 # number of WriteReq MSHR misses 540system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17194 # number of LoadLockedReq MSHR misses 541system.cpu.dcache.LoadLockedReq_mshr_misses::total 17194 # number of LoadLockedReq MSHR misses |
| 542system.cpu.dcache.demand_mshr_misses::cpu.data 1378684 # number of demand (read+write) MSHR misses 543system.cpu.dcache.demand_mshr_misses::total 1378684 # number of demand (read+write) MSHR misses 544system.cpu.dcache.overall_mshr_misses::cpu.data 1378684 # number of overall MSHR misses 545system.cpu.dcache.overall_mshr_misses::total 1378684 # number of overall MSHR misses 546system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29341442500 # number of ReadReq MSHR miss cycles 547system.cpu.dcache.ReadReq_mshr_miss_latency::total 29341442500 # number of ReadReq MSHR miss cycles 548system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11237495843 # number of WriteReq MSHR miss cycles 549system.cpu.dcache.WriteReq_mshr_miss_latency::total 11237495843 # number of WriteReq MSHR miss cycles | 542system.cpu.dcache.demand_mshr_misses::cpu.data 1378682 # number of demand (read+write) MSHR misses 543system.cpu.dcache.demand_mshr_misses::total 1378682 # number of demand (read+write) MSHR misses 544system.cpu.dcache.overall_mshr_misses::cpu.data 1378682 # number of overall MSHR misses 545system.cpu.dcache.overall_mshr_misses::total 1378682 # number of overall MSHR misses 546system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 547system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 548system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable 549system.cpu.dcache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable 550system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses 551system.cpu.dcache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses 552system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29341393000 # number of ReadReq MSHR miss cycles 553system.cpu.dcache.ReadReq_mshr_miss_latency::total 29341393000 # number of ReadReq MSHR miss cycles 554system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11237642841 # number of WriteReq MSHR miss cycles 555system.cpu.dcache.WriteReq_mshr_miss_latency::total 11237642841 # number of WriteReq MSHR miss cycles |
| 550system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204691750 # number of LoadLockedReq MSHR miss cycles 551system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204691750 # number of LoadLockedReq MSHR miss cycles | 556system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204691750 # number of LoadLockedReq MSHR miss cycles 557system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204691750 # number of LoadLockedReq MSHR miss cycles |
| 552system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40578938343 # number of demand (read+write) MSHR miss cycles 553system.cpu.dcache.demand_mshr_miss_latency::total 40578938343 # number of demand (read+write) MSHR miss cycles 554system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40578938343 # number of overall MSHR miss cycles 555system.cpu.dcache.overall_mshr_miss_latency::total 40578938343 # number of overall MSHR miss cycles | 558system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40579035841 # number of demand (read+write) MSHR miss cycles 559system.cpu.dcache.demand_mshr_miss_latency::total 40579035841 # number of demand (read+write) MSHR miss cycles 560system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40579035841 # number of overall MSHR miss cycles 561system.cpu.dcache.overall_mshr_miss_latency::total 40579035841 # number of overall MSHR miss cycles |
| 556system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433304500 # number of ReadReq MSHR uncacheable cycles 557system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433304500 # number of ReadReq MSHR uncacheable cycles | 562system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433304500 # number of ReadReq MSHR uncacheable cycles 563system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433304500 # number of ReadReq MSHR uncacheable cycles |
| 558system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2018255500 # number of WriteReq MSHR uncacheable cycles 559system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2018255500 # number of WriteReq MSHR uncacheable cycles 560system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3451560000 # number of overall MSHR uncacheable cycles 561system.cpu.dcache.overall_mshr_uncacheable_latency::total 3451560000 # number of overall MSHR uncacheable cycles | 564system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2018260000 # number of WriteReq MSHR uncacheable cycles 565system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2018260000 # number of WriteReq MSHR uncacheable cycles 566system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3451564500 # number of overall MSHR uncacheable cycles 567system.cpu.dcache.overall_mshr_uncacheable_latency::total 3451564500 # number of overall MSHR uncacheable cycles |
| 562system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119156 # mshr miss rate for ReadReq accesses 563system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119156 # mshr miss rate for ReadReq accesses 564system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049470 # mshr miss rate for WriteReq accesses 565system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses 566system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085964 # mshr miss rate for LoadLockedReq accesses 567system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085964 # mshr miss rate for LoadLockedReq accesses 568system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090899 # mshr miss rate for demand accesses 569system.cpu.dcache.demand_mshr_miss_rate::total 0.090899 # mshr miss rate for demand accesses 570system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090899 # mshr miss rate for overall accesses 571system.cpu.dcache.overall_mshr_miss_rate::total 0.090899 # mshr miss rate for overall accesses | 568system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119156 # mshr miss rate for ReadReq accesses 569system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119156 # mshr miss rate for ReadReq accesses 570system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049470 # mshr miss rate for WriteReq accesses 571system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses 572system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085964 # mshr miss rate for LoadLockedReq accesses 573system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085964 # mshr miss rate for LoadLockedReq accesses 574system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090899 # mshr miss rate for demand accesses 575system.cpu.dcache.demand_mshr_miss_rate::total 0.090899 # mshr miss rate for demand accesses 576system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090899 # mshr miss rate for overall accesses 577system.cpu.dcache.overall_mshr_miss_rate::total 0.090899 # mshr miss rate for overall accesses |
| 572system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27308.819738 # average ReadReq mshr miss latency 573system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27308.819738 # average ReadReq mshr miss latency 574system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36934.708427 # average WriteReq mshr miss latency 575system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36934.708427 # average WriteReq mshr miss latency | 578system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27308.824501 # average ReadReq mshr miss latency 579system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27308.824501 # average ReadReq mshr miss latency 580system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36935.191571 # average WriteReq mshr miss latency 581system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36935.191571 # average WriteReq mshr miss latency |
| 576system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.835989 # average LoadLockedReq mshr miss latency 577system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.835989 # average LoadLockedReq mshr miss latency | 582system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.835989 # average LoadLockedReq mshr miss latency 583system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.835989 # average LoadLockedReq mshr miss latency |
| 578system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29433.095868 # average overall mshr miss latency 579system.cpu.dcache.demand_avg_mshr_miss_latency::total 29433.095868 # average overall mshr miss latency 580system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29433.095868 # average overall mshr miss latency 581system.cpu.dcache.overall_avg_mshr_miss_latency::total 29433.095868 # average overall mshr miss latency 582system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 583system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 584system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 585system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 586system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 587system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 584system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29433.209283 # average overall mshr miss latency 585system.cpu.dcache.demand_avg_mshr_miss_latency::total 29433.209283 # average overall mshr miss latency 586system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29433.209283 # average overall mshr miss latency 587system.cpu.dcache.overall_avg_mshr_miss_latency::total 29433.209283 # average overall mshr miss latency 588system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206826.046176 # average ReadReq mshr uncacheable latency 589system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206826.046176 # average ReadReq mshr uncacheable latency 590system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209820.147624 # average WriteReq mshr uncacheable latency 591system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209820.147624 # average WriteReq mshr uncacheable latency 592system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208566.348420 # average overall mshr uncacheable latency 593system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208566.348420 # average overall mshr uncacheable latency |
| 588system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 589system.cpu.icache.tags.replacements 1459080 # number of replacements 590system.cpu.icache.tags.tagsinuse 509.440068 # Cycle average of tags in use 591system.cpu.icache.tags.total_refs 18968295 # Total number of references to valid blocks. 592system.cpu.icache.tags.sampled_refs 1459591 # Sample count of references to valid blocks. 593system.cpu.icache.tags.avg_refs 12.995623 # Average number of references to valid blocks. 594system.cpu.icache.tags.warmup_cycle 33851094250 # Cycle when the warmup percentage was hit. 595system.cpu.icache.tags.occ_blocks::cpu.inst 509.440068 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 609system.cpu.icache.overall_hits::cpu.inst 18968298 # number of overall hits 610system.cpu.icache.overall_hits::total 18968298 # number of overall hits 611system.cpu.icache.ReadReq_misses::cpu.inst 1459769 # number of ReadReq misses 612system.cpu.icache.ReadReq_misses::total 1459769 # number of ReadReq misses 613system.cpu.icache.demand_misses::cpu.inst 1459769 # number of demand (read+write) misses 614system.cpu.icache.demand_misses::total 1459769 # number of demand (read+write) misses 615system.cpu.icache.overall_misses::cpu.inst 1459769 # number of overall misses 616system.cpu.icache.overall_misses::total 1459769 # number of overall misses | 594system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 595system.cpu.icache.tags.replacements 1459080 # number of replacements 596system.cpu.icache.tags.tagsinuse 509.440068 # Cycle average of tags in use 597system.cpu.icache.tags.total_refs 18968295 # Total number of references to valid blocks. 598system.cpu.icache.tags.sampled_refs 1459591 # Sample count of references to valid blocks. 599system.cpu.icache.tags.avg_refs 12.995623 # Average number of references to valid blocks. 600system.cpu.icache.tags.warmup_cycle 33851094250 # Cycle when the warmup percentage was hit. 601system.cpu.icache.tags.occ_blocks::cpu.inst 509.440068 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 615system.cpu.icache.overall_hits::cpu.inst 18968298 # number of overall hits 616system.cpu.icache.overall_hits::total 18968298 # number of overall hits 617system.cpu.icache.ReadReq_misses::cpu.inst 1459769 # number of ReadReq misses 618system.cpu.icache.ReadReq_misses::total 1459769 # number of ReadReq misses 619system.cpu.icache.demand_misses::cpu.inst 1459769 # number of demand (read+write) misses 620system.cpu.icache.demand_misses::total 1459769 # number of demand (read+write) misses 621system.cpu.icache.overall_misses::cpu.inst 1459769 # number of overall misses 622system.cpu.icache.overall_misses::total 1459769 # number of overall misses |
| 617system.cpu.icache.ReadReq_miss_latency::cpu.inst 20155087658 # number of ReadReq miss cycles 618system.cpu.icache.ReadReq_miss_latency::total 20155087658 # number of ReadReq miss cycles 619system.cpu.icache.demand_miss_latency::cpu.inst 20155087658 # number of demand (read+write) miss cycles 620system.cpu.icache.demand_miss_latency::total 20155087658 # number of demand (read+write) miss cycles 621system.cpu.icache.overall_miss_latency::cpu.inst 20155087658 # number of overall miss cycles 622system.cpu.icache.overall_miss_latency::total 20155087658 # number of overall miss cycles | 623system.cpu.icache.ReadReq_miss_latency::cpu.inst 20155075408 # number of ReadReq miss cycles 624system.cpu.icache.ReadReq_miss_latency::total 20155075408 # number of ReadReq miss cycles 625system.cpu.icache.demand_miss_latency::cpu.inst 20155075408 # number of demand (read+write) miss cycles 626system.cpu.icache.demand_miss_latency::total 20155075408 # number of demand (read+write) miss cycles 627system.cpu.icache.overall_miss_latency::cpu.inst 20155075408 # number of overall miss cycles 628system.cpu.icache.overall_miss_latency::total 20155075408 # number of overall miss cycles |
| 623system.cpu.icache.ReadReq_accesses::cpu.inst 20428067 # number of ReadReq accesses(hits+misses) 624system.cpu.icache.ReadReq_accesses::total 20428067 # number of ReadReq accesses(hits+misses) 625system.cpu.icache.demand_accesses::cpu.inst 20428067 # number of demand (read+write) accesses 626system.cpu.icache.demand_accesses::total 20428067 # number of demand (read+write) accesses 627system.cpu.icache.overall_accesses::cpu.inst 20428067 # number of overall (read+write) accesses 628system.cpu.icache.overall_accesses::total 20428067 # number of overall (read+write) accesses 629system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071459 # miss rate for ReadReq accesses 630system.cpu.icache.ReadReq_miss_rate::total 0.071459 # miss rate for ReadReq accesses 631system.cpu.icache.demand_miss_rate::cpu.inst 0.071459 # miss rate for demand accesses 632system.cpu.icache.demand_miss_rate::total 0.071459 # miss rate for demand accesses 633system.cpu.icache.overall_miss_rate::cpu.inst 0.071459 # miss rate for overall accesses 634system.cpu.icache.overall_miss_rate::total 0.071459 # miss rate for overall accesses | 629system.cpu.icache.ReadReq_accesses::cpu.inst 20428067 # number of ReadReq accesses(hits+misses) 630system.cpu.icache.ReadReq_accesses::total 20428067 # number of ReadReq accesses(hits+misses) 631system.cpu.icache.demand_accesses::cpu.inst 20428067 # number of demand (read+write) accesses 632system.cpu.icache.demand_accesses::total 20428067 # number of demand (read+write) accesses 633system.cpu.icache.overall_accesses::cpu.inst 20428067 # number of overall (read+write) accesses 634system.cpu.icache.overall_accesses::total 20428067 # number of overall (read+write) accesses 635system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071459 # miss rate for ReadReq accesses 636system.cpu.icache.ReadReq_miss_rate::total 0.071459 # miss rate for ReadReq accesses 637system.cpu.icache.demand_miss_rate::cpu.inst 0.071459 # miss rate for demand accesses 638system.cpu.icache.demand_miss_rate::total 0.071459 # miss rate for demand accesses 639system.cpu.icache.overall_miss_rate::cpu.inst 0.071459 # miss rate for overall accesses 640system.cpu.icache.overall_miss_rate::total 0.071459 # miss rate for overall accesses |
| 635system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13807.039099 # average ReadReq miss latency 636system.cpu.icache.ReadReq_avg_miss_latency::total 13807.039099 # average ReadReq miss latency 637system.cpu.icache.demand_avg_miss_latency::cpu.inst 13807.039099 # average overall miss latency 638system.cpu.icache.demand_avg_miss_latency::total 13807.039099 # average overall miss latency 639system.cpu.icache.overall_avg_miss_latency::cpu.inst 13807.039099 # average overall miss latency 640system.cpu.icache.overall_avg_miss_latency::total 13807.039099 # average overall miss latency | 641system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13807.030707 # average ReadReq miss latency 642system.cpu.icache.ReadReq_avg_miss_latency::total 13807.030707 # average ReadReq miss latency 643system.cpu.icache.demand_avg_miss_latency::cpu.inst 13807.030707 # average overall miss latency 644system.cpu.icache.demand_avg_miss_latency::total 13807.030707 # average overall miss latency 645system.cpu.icache.overall_avg_miss_latency::cpu.inst 13807.030707 # average overall miss latency 646system.cpu.icache.overall_avg_miss_latency::total 13807.030707 # average overall miss latency |
| 641system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 642system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 643system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 644system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 645system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 646system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 647system.cpu.icache.fast_writes 0 # number of fast writes performed 648system.cpu.icache.cache_copies 0 # number of cache copies performed 649system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459769 # number of ReadReq MSHR misses 650system.cpu.icache.ReadReq_mshr_misses::total 1459769 # number of ReadReq MSHR misses 651system.cpu.icache.demand_mshr_misses::cpu.inst 1459769 # number of demand (read+write) MSHR misses 652system.cpu.icache.demand_mshr_misses::total 1459769 # number of demand (read+write) MSHR misses 653system.cpu.icache.overall_mshr_misses::cpu.inst 1459769 # number of overall MSHR misses 654system.cpu.icache.overall_mshr_misses::total 1459769 # number of overall MSHR misses | 647system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 648system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 649system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 650system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 651system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 652system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 653system.cpu.icache.fast_writes 0 # number of fast writes performed 654system.cpu.icache.cache_copies 0 # number of cache copies performed 655system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459769 # number of ReadReq MSHR misses 656system.cpu.icache.ReadReq_mshr_misses::total 1459769 # number of ReadReq MSHR misses 657system.cpu.icache.demand_mshr_misses::cpu.inst 1459769 # number of demand (read+write) MSHR misses 658system.cpu.icache.demand_mshr_misses::total 1459769 # number of demand (read+write) MSHR misses 659system.cpu.icache.overall_mshr_misses::cpu.inst 1459769 # number of overall MSHR misses 660system.cpu.icache.overall_mshr_misses::total 1459769 # number of overall MSHR misses |
| 655system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17958185842 # number of ReadReq MSHR miss cycles 656system.cpu.icache.ReadReq_mshr_miss_latency::total 17958185842 # number of ReadReq MSHR miss cycles 657system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17958185842 # number of demand (read+write) MSHR miss cycles 658system.cpu.icache.demand_mshr_miss_latency::total 17958185842 # number of demand (read+write) MSHR miss cycles 659system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17958185842 # number of overall MSHR miss cycles 660system.cpu.icache.overall_mshr_miss_latency::total 17958185842 # number of overall MSHR miss cycles | 661system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17958174092 # number of ReadReq MSHR miss cycles 662system.cpu.icache.ReadReq_mshr_miss_latency::total 17958174092 # number of ReadReq MSHR miss cycles 663system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17958174092 # number of demand (read+write) MSHR miss cycles 664system.cpu.icache.demand_mshr_miss_latency::total 17958174092 # number of demand (read+write) MSHR miss cycles 665system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17958174092 # number of overall MSHR miss cycles 666system.cpu.icache.overall_mshr_miss_latency::total 17958174092 # number of overall MSHR miss cycles |
| 661system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for ReadReq accesses 662system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071459 # mshr miss rate for ReadReq accesses 663system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for demand accesses 664system.cpu.icache.demand_mshr_miss_rate::total 0.071459 # mshr miss rate for demand accesses 665system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for overall accesses 666system.cpu.icache.overall_mshr_miss_rate::total 0.071459 # mshr miss rate for overall accesses | 667system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for ReadReq accesses 668system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071459 # mshr miss rate for ReadReq accesses 669system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for demand accesses 670system.cpu.icache.demand_mshr_miss_rate::total 0.071459 # mshr miss rate for demand accesses 671system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for overall accesses 672system.cpu.icache.overall_mshr_miss_rate::total 0.071459 # mshr miss rate for overall accesses |
| 667system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12302.073713 # average ReadReq mshr miss latency 668system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12302.073713 # average ReadReq mshr miss latency 669system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12302.073713 # average overall mshr miss latency 670system.cpu.icache.demand_avg_mshr_miss_latency::total 12302.073713 # average overall mshr miss latency 671system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12302.073713 # average overall mshr miss latency 672system.cpu.icache.overall_avg_mshr_miss_latency::total 12302.073713 # average overall mshr miss latency | 673system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12302.065664 # average ReadReq mshr miss latency 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12302.065664 # average ReadReq mshr miss latency 675system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12302.065664 # average overall mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::total 12302.065664 # average overall mshr miss latency 677system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12302.065664 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::total 12302.065664 # average overall mshr miss latency |
| 673system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 674system.cpu.l2cache.tags.replacements 339394 # number of replacements | 679system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 680system.cpu.l2cache.tags.replacements 339394 # number of replacements |
| 675system.cpu.l2cache.tags.tagsinuse 65314.689309 # Cycle average of tags in use 676system.cpu.l2cache.tags.total_refs 2982707 # Total number of references to valid blocks. | 681system.cpu.l2cache.tags.tagsinuse 65314.689332 # Cycle average of tags in use 682system.cpu.l2cache.tags.total_refs 2982705 # Total number of references to valid blocks. |
| 677system.cpu.l2cache.tags.sampled_refs 404554 # Sample count of references to valid blocks. | 683system.cpu.l2cache.tags.sampled_refs 404554 # Sample count of references to valid blocks. |
| 678system.cpu.l2cache.tags.avg_refs 7.372828 # Average number of references to valid blocks. | 684system.cpu.l2cache.tags.avg_refs 7.372823 # Average number of references to valid blocks. |
| 679system.cpu.l2cache.tags.warmup_cycle 6335415750 # Cycle when the warmup percentage was hit. | 685system.cpu.l2cache.tags.warmup_cycle 6335415750 # Cycle when the warmup percentage was hit. |
| 680system.cpu.l2cache.tags.occ_blocks::writebacks 54416.774547 # Average occupied blocks per requestor 681system.cpu.l2cache.tags.occ_blocks::cpu.inst 5825.207065 # Average occupied blocks per requestor | 686system.cpu.l2cache.tags.occ_blocks::writebacks 54416.774568 # Average occupied blocks per requestor 687system.cpu.l2cache.tags.occ_blocks::cpu.inst 5825.207067 # Average occupied blocks per requestor |
| 682system.cpu.l2cache.tags.occ_blocks::cpu.data 5072.707697 # Average occupied blocks per requestor 683system.cpu.l2cache.tags.occ_percent::writebacks 0.830334 # Average percentage of cache occupancy 684system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088886 # Average percentage of cache occupancy 685system.cpu.l2cache.tags.occ_percent::cpu.data 0.077403 # Average percentage of cache occupancy 686system.cpu.l2cache.tags.occ_percent::total 0.996623 # Average percentage of cache occupancy 687system.cpu.l2cache.tags.occ_task_id_blocks::1024 65160 # Occupied blocks per task id 688system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id 689system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1413 # Occupied blocks per task id 690system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5172 # Occupied blocks per task id 691system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2816 # Occupied blocks per task id 692system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55531 # Occupied blocks per task id 693system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994263 # Percentage of cache occupancy per task id | 688system.cpu.l2cache.tags.occ_blocks::cpu.data 5072.707697 # Average occupied blocks per requestor 689system.cpu.l2cache.tags.occ_percent::writebacks 0.830334 # Average percentage of cache occupancy 690system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088886 # Average percentage of cache occupancy 691system.cpu.l2cache.tags.occ_percent::cpu.data 0.077403 # Average percentage of cache occupancy 692system.cpu.l2cache.tags.occ_percent::total 0.996623 # Average percentage of cache occupancy 693system.cpu.l2cache.tags.occ_task_id_blocks::1024 65160 # Occupied blocks per task id 694system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id 695system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1413 # Occupied blocks per task id 696system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5172 # Occupied blocks per task id 697system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2816 # Occupied blocks per task id 698system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55531 # Occupied blocks per task id 699system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994263 # Percentage of cache occupancy per task id |
| 694system.cpu.l2cache.tags.tag_accesses 30259084 # Number of tag accesses 695system.cpu.l2cache.tags.data_accesses 30259084 # Number of data accesses | 700system.cpu.l2cache.tags.tag_accesses 30259068 # Number of tag accesses 701system.cpu.l2cache.tags.data_accesses 30259068 # Number of data accesses |
| 696system.cpu.l2cache.ReadReq_hits::cpu.inst 1443260 # number of ReadReq hits | 702system.cpu.l2cache.ReadReq_hits::cpu.inst 1443260 # number of ReadReq hits |
| 697system.cpu.l2cache.ReadReq_hits::cpu.data 819387 # number of ReadReq hits 698system.cpu.l2cache.ReadReq_hits::total 2262647 # number of ReadReq hits | 703system.cpu.l2cache.ReadReq_hits::cpu.data 819385 # number of ReadReq hits 704system.cpu.l2cache.ReadReq_hits::total 2262645 # number of ReadReq hits |
| 699system.cpu.l2cache.Writeback_hits::writebacks 838171 # number of Writeback hits 700system.cpu.l2cache.Writeback_hits::total 838171 # number of Writeback hits 701system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 702system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 705system.cpu.l2cache.Writeback_hits::writebacks 838171 # number of Writeback hits 706system.cpu.l2cache.Writeback_hits::total 838171 # number of Writeback hits 707system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 708system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 703system.cpu.l2cache.ReadExReq_hits::cpu.data 187599 # number of ReadExReq hits 704system.cpu.l2cache.ReadExReq_hits::total 187599 # number of ReadExReq hits | 709system.cpu.l2cache.ReadExReq_hits::cpu.data 187597 # number of ReadExReq hits 710system.cpu.l2cache.ReadExReq_hits::total 187597 # number of ReadExReq hits |
| 705system.cpu.l2cache.demand_hits::cpu.inst 1443260 # number of demand (read+write) hits | 711system.cpu.l2cache.demand_hits::cpu.inst 1443260 # number of demand (read+write) hits |
| 706system.cpu.l2cache.demand_hits::cpu.data 1006986 # number of demand (read+write) hits 707system.cpu.l2cache.demand_hits::total 2450246 # number of demand (read+write) hits | 712system.cpu.l2cache.demand_hits::cpu.data 1006982 # number of demand (read+write) hits 713system.cpu.l2cache.demand_hits::total 2450242 # number of demand (read+write) hits |
| 708system.cpu.l2cache.overall_hits::cpu.inst 1443260 # number of overall hits | 714system.cpu.l2cache.overall_hits::cpu.inst 1443260 # number of overall hits |
| 709system.cpu.l2cache.overall_hits::cpu.data 1006986 # number of overall hits 710system.cpu.l2cache.overall_hits::total 2450246 # number of overall hits | 715system.cpu.l2cache.overall_hits::cpu.data 1006982 # number of overall hits 716system.cpu.l2cache.overall_hits::total 2450242 # number of overall hits |
| 711system.cpu.l2cache.ReadReq_misses::cpu.inst 16444 # number of ReadReq misses 712system.cpu.l2cache.ReadReq_misses::cpu.data 272210 # number of ReadReq misses 713system.cpu.l2cache.ReadReq_misses::total 288654 # number of ReadReq misses 714system.cpu.l2cache.UpgradeReq_misses::cpu.data 20 # number of UpgradeReq misses 715system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses | 717system.cpu.l2cache.ReadReq_misses::cpu.inst 16444 # number of ReadReq misses 718system.cpu.l2cache.ReadReq_misses::cpu.data 272210 # number of ReadReq misses 719system.cpu.l2cache.ReadReq_misses::total 288654 # number of ReadReq misses 720system.cpu.l2cache.UpgradeReq_misses::cpu.data 20 # number of UpgradeReq misses 721system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses |
| 716system.cpu.l2cache.ReadExReq_misses::cpu.data 116658 # number of ReadExReq misses 717system.cpu.l2cache.ReadExReq_misses::total 116658 # number of ReadExReq misses | 722system.cpu.l2cache.ReadExReq_misses::cpu.data 116660 # number of ReadExReq misses 723system.cpu.l2cache.ReadExReq_misses::total 116660 # number of ReadExReq misses |
| 718system.cpu.l2cache.demand_misses::cpu.inst 16444 # number of demand (read+write) misses | 724system.cpu.l2cache.demand_misses::cpu.inst 16444 # number of demand (read+write) misses |
| 719system.cpu.l2cache.demand_misses::cpu.data 388868 # number of demand (read+write) misses 720system.cpu.l2cache.demand_misses::total 405312 # number of demand (read+write) misses | 725system.cpu.l2cache.demand_misses::cpu.data 388870 # number of demand (read+write) misses 726system.cpu.l2cache.demand_misses::total 405314 # number of demand (read+write) misses |
| 721system.cpu.l2cache.overall_misses::cpu.inst 16444 # number of overall misses | 727system.cpu.l2cache.overall_misses::cpu.inst 16444 # number of overall misses |
| 722system.cpu.l2cache.overall_misses::cpu.data 388868 # number of overall misses 723system.cpu.l2cache.overall_misses::total 405312 # number of overall misses 724system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1322916250 # number of ReadReq miss cycles 725system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19744352250 # number of ReadReq miss cycles 726system.cpu.l2cache.ReadReq_miss_latency::total 21067268500 # number of ReadReq miss cycles | 728system.cpu.l2cache.overall_misses::cpu.data 388870 # number of overall misses 729system.cpu.l2cache.overall_misses::total 405314 # number of overall misses 730system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1322904500 # number of ReadReq miss cycles 731system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19744325250 # number of ReadReq miss cycles 732system.cpu.l2cache.ReadReq_miss_latency::total 21067229750 # number of ReadReq miss cycles |
| 727system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 253997 # number of UpgradeReq miss cycles 728system.cpu.l2cache.UpgradeReq_miss_latency::total 253997 # number of UpgradeReq miss cycles | 733system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 253997 # number of UpgradeReq miss cycles 734system.cpu.l2cache.UpgradeReq_miss_latency::total 253997 # number of UpgradeReq miss cycles |
| 729system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8959337611 # number of ReadExReq miss cycles 730system.cpu.l2cache.ReadExReq_miss_latency::total 8959337611 # number of ReadExReq miss cycles 731system.cpu.l2cache.demand_miss_latency::cpu.inst 1322916250 # number of demand (read+write) miss cycles 732system.cpu.l2cache.demand_miss_latency::cpu.data 28703689861 # number of demand (read+write) miss cycles 733system.cpu.l2cache.demand_miss_latency::total 30026606111 # number of demand (read+write) miss cycles 734system.cpu.l2cache.overall_miss_latency::cpu.inst 1322916250 # number of overall miss cycles 735system.cpu.l2cache.overall_miss_latency::cpu.data 28703689861 # number of overall miss cycles 736system.cpu.l2cache.overall_miss_latency::total 30026606111 # number of overall miss cycles | 735system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8959505609 # number of ReadExReq miss cycles 736system.cpu.l2cache.ReadExReq_miss_latency::total 8959505609 # number of ReadExReq miss cycles 737system.cpu.l2cache.demand_miss_latency::cpu.inst 1322904500 # number of demand (read+write) miss cycles 738system.cpu.l2cache.demand_miss_latency::cpu.data 28703830859 # number of demand (read+write) miss cycles 739system.cpu.l2cache.demand_miss_latency::total 30026735359 # number of demand (read+write) miss cycles 740system.cpu.l2cache.overall_miss_latency::cpu.inst 1322904500 # number of overall miss cycles 741system.cpu.l2cache.overall_miss_latency::cpu.data 28703830859 # number of overall miss cycles 742system.cpu.l2cache.overall_miss_latency::total 30026735359 # number of overall miss cycles |
| 737system.cpu.l2cache.ReadReq_accesses::cpu.inst 1459704 # number of ReadReq accesses(hits+misses) | 743system.cpu.l2cache.ReadReq_accesses::cpu.inst 1459704 # number of ReadReq accesses(hits+misses) |
| 738system.cpu.l2cache.ReadReq_accesses::cpu.data 1091597 # number of ReadReq accesses(hits+misses) 739system.cpu.l2cache.ReadReq_accesses::total 2551301 # number of ReadReq accesses(hits+misses) | 744system.cpu.l2cache.ReadReq_accesses::cpu.data 1091595 # number of ReadReq accesses(hits+misses) 745system.cpu.l2cache.ReadReq_accesses::total 2551299 # number of ReadReq accesses(hits+misses) |
| 740system.cpu.l2cache.Writeback_accesses::writebacks 838171 # number of Writeback accesses(hits+misses) 741system.cpu.l2cache.Writeback_accesses::total 838171 # number of Writeback accesses(hits+misses) 742system.cpu.l2cache.UpgradeReq_accesses::cpu.data 24 # number of UpgradeReq accesses(hits+misses) 743system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses) 744system.cpu.l2cache.ReadExReq_accesses::cpu.data 304257 # number of ReadExReq accesses(hits+misses) 745system.cpu.l2cache.ReadExReq_accesses::total 304257 # number of ReadExReq accesses(hits+misses) 746system.cpu.l2cache.demand_accesses::cpu.inst 1459704 # number of demand (read+write) accesses | 746system.cpu.l2cache.Writeback_accesses::writebacks 838171 # number of Writeback accesses(hits+misses) 747system.cpu.l2cache.Writeback_accesses::total 838171 # number of Writeback accesses(hits+misses) 748system.cpu.l2cache.UpgradeReq_accesses::cpu.data 24 # number of UpgradeReq accesses(hits+misses) 749system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses) 750system.cpu.l2cache.ReadExReq_accesses::cpu.data 304257 # number of ReadExReq accesses(hits+misses) 751system.cpu.l2cache.ReadExReq_accesses::total 304257 # number of ReadExReq accesses(hits+misses) 752system.cpu.l2cache.demand_accesses::cpu.inst 1459704 # number of demand (read+write) accesses |
| 747system.cpu.l2cache.demand_accesses::cpu.data 1395854 # number of demand (read+write) accesses 748system.cpu.l2cache.demand_accesses::total 2855558 # number of demand (read+write) accesses | 753system.cpu.l2cache.demand_accesses::cpu.data 1395852 # number of demand (read+write) accesses 754system.cpu.l2cache.demand_accesses::total 2855556 # number of demand (read+write) accesses |
| 749system.cpu.l2cache.overall_accesses::cpu.inst 1459704 # number of overall (read+write) accesses | 755system.cpu.l2cache.overall_accesses::cpu.inst 1459704 # number of overall (read+write) accesses |
| 750system.cpu.l2cache.overall_accesses::cpu.data 1395854 # number of overall (read+write) accesses 751system.cpu.l2cache.overall_accesses::total 2855558 # number of overall (read+write) accesses | 756system.cpu.l2cache.overall_accesses::cpu.data 1395852 # number of overall (read+write) accesses 757system.cpu.l2cache.overall_accesses::total 2855556 # number of overall (read+write) accesses |
| 752system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.011265 # miss rate for ReadReq accesses 753system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.249369 # miss rate for ReadReq accesses 754system.cpu.l2cache.ReadReq_miss_rate::total 0.113140 # miss rate for ReadReq accesses 755system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.833333 # miss rate for UpgradeReq accesses 756system.cpu.l2cache.UpgradeReq_miss_rate::total 0.833333 # miss rate for UpgradeReq accesses | 758system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.011265 # miss rate for ReadReq accesses 759system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.249369 # miss rate for ReadReq accesses 760system.cpu.l2cache.ReadReq_miss_rate::total 0.113140 # miss rate for ReadReq accesses 761system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.833333 # miss rate for UpgradeReq accesses 762system.cpu.l2cache.UpgradeReq_miss_rate::total 0.833333 # miss rate for UpgradeReq accesses |
| 757system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383419 # miss rate for ReadExReq accesses 758system.cpu.l2cache.ReadExReq_miss_rate::total 0.383419 # miss rate for ReadExReq accesses | 763system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383426 # miss rate for ReadExReq accesses 764system.cpu.l2cache.ReadExReq_miss_rate::total 0.383426 # miss rate for ReadExReq accesses |
| 759system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011265 # miss rate for demand accesses | 765system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011265 # miss rate for demand accesses |
| 760system.cpu.l2cache.demand_miss_rate::cpu.data 0.278588 # miss rate for demand accesses 761system.cpu.l2cache.demand_miss_rate::total 0.141938 # miss rate for demand accesses | 766system.cpu.l2cache.demand_miss_rate::cpu.data 0.278590 # miss rate for demand accesses 767system.cpu.l2cache.demand_miss_rate::total 0.141939 # miss rate for demand accesses |
| 762system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011265 # miss rate for overall accesses | 768system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011265 # miss rate for overall accesses |
| 763system.cpu.l2cache.overall_miss_rate::cpu.data 0.278588 # miss rate for overall accesses 764system.cpu.l2cache.overall_miss_rate::total 0.141938 # miss rate for overall accesses 765system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80449.784116 # average ReadReq miss latency 766system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72533.530179 # average ReadReq miss latency 767system.cpu.l2cache.ReadReq_avg_miss_latency::total 72984.502207 # average ReadReq miss latency | 769system.cpu.l2cache.overall_miss_rate::cpu.data 0.278590 # miss rate for overall accesses 770system.cpu.l2cache.overall_miss_rate::total 0.141939 # miss rate for overall accesses 771system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80449.069569 # average ReadReq miss latency 772system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72533.430991 # average ReadReq miss latency 773system.cpu.l2cache.ReadReq_avg_miss_latency::total 72984.367963 # average ReadReq miss latency |
| 768system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12699.850000 # average UpgradeReq miss latency 769system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12699.850000 # average UpgradeReq miss latency | 774system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12699.850000 # average UpgradeReq miss latency 775system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12699.850000 # average UpgradeReq miss latency |
| 770system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76800.027525 # average ReadExReq miss latency 771system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76800.027525 # average ReadExReq miss latency 772system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80449.784116 # average overall miss latency 773system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73813.453051 # average overall miss latency 774system.cpu.l2cache.demand_avg_miss_latency::total 74082.697061 # average overall miss latency 775system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80449.784116 # average overall miss latency 776system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73813.453051 # average overall miss latency 777system.cpu.l2cache.overall_avg_miss_latency::total 74082.697061 # average overall miss latency | 776system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76800.150943 # average ReadExReq miss latency 777system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76800.150943 # average ReadExReq miss latency 778system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80449.069569 # average overall miss latency 779system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73813.436004 # average overall miss latency 780system.cpu.l2cache.demand_avg_miss_latency::total 74082.650387 # average overall miss latency 781system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80449.069569 # average overall miss latency 782system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73813.436004 # average overall miss latency 783system.cpu.l2cache.overall_avg_miss_latency::total 74082.650387 # average overall miss latency |
| 778system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 779system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 780system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 781system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 782system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 783system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 784system.cpu.l2cache.fast_writes 0 # number of fast writes performed 785system.cpu.l2cache.cache_copies 0 # number of cache copies performed 786system.cpu.l2cache.writebacks::writebacks 76588 # number of writebacks 787system.cpu.l2cache.writebacks::total 76588 # number of writebacks 788system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16444 # number of ReadReq MSHR misses 789system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272210 # number of ReadReq MSHR misses 790system.cpu.l2cache.ReadReq_mshr_misses::total 288654 # number of ReadReq MSHR misses 791system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses 792system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses | 784system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 785system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 786system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 787system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 788system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 789system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 790system.cpu.l2cache.fast_writes 0 # number of fast writes performed 791system.cpu.l2cache.cache_copies 0 # number of cache copies performed 792system.cpu.l2cache.writebacks::writebacks 76588 # number of writebacks 793system.cpu.l2cache.writebacks::total 76588 # number of writebacks 794system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16444 # number of ReadReq MSHR misses 795system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272210 # number of ReadReq MSHR misses 796system.cpu.l2cache.ReadReq_mshr_misses::total 288654 # number of ReadReq MSHR misses 797system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses 798system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses |
| 793system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116658 # number of ReadExReq MSHR misses 794system.cpu.l2cache.ReadExReq_mshr_misses::total 116658 # number of ReadExReq MSHR misses | 799system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116660 # number of ReadExReq MSHR misses 800system.cpu.l2cache.ReadExReq_mshr_misses::total 116660 # number of ReadExReq MSHR misses |
| 795system.cpu.l2cache.demand_mshr_misses::cpu.inst 16444 # number of demand (read+write) MSHR misses | 801system.cpu.l2cache.demand_mshr_misses::cpu.inst 16444 # number of demand (read+write) MSHR misses |
| 796system.cpu.l2cache.demand_mshr_misses::cpu.data 388868 # number of demand (read+write) MSHR misses 797system.cpu.l2cache.demand_mshr_misses::total 405312 # number of demand (read+write) MSHR misses | 802system.cpu.l2cache.demand_mshr_misses::cpu.data 388870 # number of demand (read+write) MSHR misses 803system.cpu.l2cache.demand_mshr_misses::total 405314 # number of demand (read+write) MSHR misses |
| 798system.cpu.l2cache.overall_mshr_misses::cpu.inst 16444 # number of overall MSHR misses | 804system.cpu.l2cache.overall_mshr_misses::cpu.inst 16444 # number of overall MSHR misses |
| 799system.cpu.l2cache.overall_mshr_misses::cpu.data 388868 # number of overall MSHR misses 800system.cpu.l2cache.overall_mshr_misses::total 405312 # number of overall MSHR misses 801system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1116961750 # number of ReadReq MSHR miss cycles 802system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16343103250 # number of ReadReq MSHR miss cycles 803system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17460065000 # number of ReadReq MSHR miss cycles | 805system.cpu.l2cache.overall_mshr_misses::cpu.data 388870 # number of overall MSHR misses 806system.cpu.l2cache.overall_mshr_misses::total 405314 # number of overall MSHR misses 807system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 808system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 809system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable 810system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable 811system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses 812system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses 813system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1116950000 # number of ReadReq MSHR miss cycles 814system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16343076250 # number of ReadReq MSHR miss cycles 815system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17460026250 # number of ReadReq MSHR miss cycles |
| 804system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 455517 # number of UpgradeReq MSHR miss cycles 805system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 455517 # number of UpgradeReq MSHR miss cycles | 816system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 455517 # number of UpgradeReq MSHR miss cycles 817system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 455517 # number of UpgradeReq MSHR miss cycles |
| 806system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7500878889 # number of ReadExReq MSHR miss cycles 807system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7500878889 # number of ReadExReq MSHR miss cycles 808system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1116961750 # number of demand (read+write) MSHR miss cycles 809system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23843982139 # number of demand (read+write) MSHR miss cycles 810system.cpu.l2cache.demand_mshr_miss_latency::total 24960943889 # number of demand (read+write) MSHR miss cycles 811system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1116961750 # number of overall MSHR miss cycles 812system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23843982139 # number of overall MSHR miss cycles 813system.cpu.l2cache.overall_mshr_miss_latency::total 24960943889 # number of overall MSHR miss cycles | 818system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7501019891 # number of ReadExReq MSHR miss cycles 819system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7501019891 # number of ReadExReq MSHR miss cycles 820system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1116950000 # number of demand (read+write) MSHR miss cycles 821system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23844096141 # number of demand (read+write) MSHR miss cycles 822system.cpu.l2cache.demand_mshr_miss_latency::total 24961046141 # number of demand (read+write) MSHR miss cycles 823system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1116950000 # number of overall MSHR miss cycles 824system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23844096141 # number of overall MSHR miss cycles 825system.cpu.l2cache.overall_mshr_miss_latency::total 24961046141 # number of overall MSHR miss cycles |
| 814system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336266500 # number of ReadReq MSHR uncacheable cycles 815system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336266500 # number of ReadReq MSHR uncacheable cycles | 826system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336266500 # number of ReadReq MSHR uncacheable cycles 827system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336266500 # number of ReadReq MSHR uncacheable cycles |
| 816system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893208000 # number of WriteReq MSHR uncacheable cycles 817system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893208000 # number of WriteReq MSHR uncacheable cycles 818system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229474500 # number of overall MSHR uncacheable cycles 819system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229474500 # number of overall MSHR uncacheable cycles | 828system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893212500 # number of WriteReq MSHR uncacheable cycles 829system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893212500 # number of WriteReq MSHR uncacheable cycles 830system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229479000 # number of overall MSHR uncacheable cycles 831system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229479000 # number of overall MSHR uncacheable cycles |
| 820system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for ReadReq accesses 821system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249369 # mshr miss rate for ReadReq accesses 822system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113140 # mshr miss rate for ReadReq accesses 823system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.833333 # mshr miss rate for UpgradeReq accesses 824system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses | 832system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for ReadReq accesses 833system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249369 # mshr miss rate for ReadReq accesses 834system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113140 # mshr miss rate for ReadReq accesses 835system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.833333 # mshr miss rate for UpgradeReq accesses 836system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses |
| 825system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383419 # mshr miss rate for ReadExReq accesses 826system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383419 # mshr miss rate for ReadExReq accesses | 837system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383426 # mshr miss rate for ReadExReq accesses 838system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383426 # mshr miss rate for ReadExReq accesses |
| 827system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for demand accesses | 839system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for demand accesses |
| 828system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for demand accesses 829system.cpu.l2cache.demand_mshr_miss_rate::total 0.141938 # mshr miss rate for demand accesses | 840system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for demand accesses 841system.cpu.l2cache.demand_mshr_miss_rate::total 0.141939 # mshr miss rate for demand accesses |
| 830system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for overall accesses | 842system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for overall accesses |
| 831system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for overall accesses 832system.cpu.l2cache.overall_mshr_miss_rate::total 0.141938 # mshr miss rate for overall accesses 833system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67925.185478 # average ReadReq mshr miss latency 834system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.585100 # average ReadReq mshr miss latency 835system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.867828 # average ReadReq mshr miss latency | 843system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for overall accesses 844system.cpu.l2cache.overall_mshr_miss_rate::total 0.141939 # mshr miss rate for overall accesses 845system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67924.470932 # average ReadReq mshr miss latency 846system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.485912 # average ReadReq mshr miss latency 847system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.733584 # average ReadReq mshr miss latency |
| 836system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22775.850000 # average UpgradeReq mshr miss latency 837system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22775.850000 # average UpgradeReq mshr miss latency | 848system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22775.850000 # average UpgradeReq mshr miss latency 849system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22775.850000 # average UpgradeReq mshr miss latency |
| 838system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.024045 # average ReadExReq mshr miss latency 839system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.024045 # average ReadExReq mshr miss latency 840system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency 841system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency 842system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency 843system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency 844system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency 845system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency 846system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 847system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 848system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 849system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 850system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 851system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 850system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.130387 # average ReadExReq mshr miss latency 851system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.130387 # average ReadExReq mshr miss latency 852system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency 853system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency 854system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency 855system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency 856system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency 857system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency 858system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192823.448773 # average ReadReq mshr uncacheable latency 859system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192823.448773 # average ReadReq mshr uncacheable latency 860system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196820.095644 # average WriteReq mshr uncacheable latency 861system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196820.095644 # average WriteReq mshr uncacheable latency 862system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195146.474107 # average overall mshr uncacheable latency 863system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195146.474107 # average overall mshr uncacheable latency |
| 852system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 864system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 853system.cpu.toL2Bus.trans_dist::ReadReq 2558469 # Transaction distribution 854system.cpu.toL2Bus.trans_dist::ReadResp 2558436 # Transaction distribution | 865system.cpu.toL2Bus.trans_dist::ReadReq 2558467 # Transaction distribution 866system.cpu.toL2Bus.trans_dist::ReadResp 2558434 # Transaction distribution |
| 855system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution 856system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution 857system.cpu.toL2Bus.trans_dist::Writeback 838171 # Transaction distribution | 867system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution 869system.cpu.toL2Bus.trans_dist::Writeback 838171 # Transaction distribution |
| 858system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41593 # Transaction distribution | 870system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41592 # Transaction distribution |
| 859system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution 860system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution 861system.cpu.toL2Bus.trans_dist::ReadExReq 304257 # Transaction distribution 862system.cpu.toL2Bus.trans_dist::ReadExResp 304257 # Transaction distribution 863system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution 864system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2919473 # Packet count per connected master and slave (bytes) | 871system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution 872system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution 873system.cpu.toL2Bus.trans_dist::ReadExReq 304257 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::ReadExResp 304257 # Transaction distribution 875system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution 876system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2919473 # Packet count per connected master and slave (bytes) |
| 865system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663181 # Packet count per connected master and slave (bytes) 866system.cpu.toL2Bus.pkt_count::total 6582654 # Packet count per connected master and slave (bytes) | 877system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663177 # Packet count per connected master and slave (bytes) 878system.cpu.toL2Bus.pkt_count::total 6582650 # Packet count per connected master and slave (bytes) |
| 867system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93421056 # Cumulative packet size per connected master and slave (bytes) | 879system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93421056 # Cumulative packet size per connected master and slave (bytes) |
| 868system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030876 # Cumulative packet size per connected master and slave (bytes) 869system.cpu.toL2Bus.pkt_size::total 236451932 # Cumulative packet size per connected master and slave (bytes) 870system.cpu.toL2Bus.snoops 41987 # Total snoops (count) 871system.cpu.toL2Bus.snoop_fanout::samples 3735584 # Request fanout histogram 872system.cpu.toL2Bus.snoop_fanout::mean 1.011181 # Request fanout histogram 873system.cpu.toL2Bus.snoop_fanout::stdev 0.105146 # Request fanout histogram | 880system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030748 # Cumulative packet size per connected master and slave (bytes) 881system.cpu.toL2Bus.pkt_size::total 236451804 # Cumulative packet size per connected master and slave (bytes) 882system.cpu.toL2Bus.snoops 41986 # Total snoops (count) 883system.cpu.toL2Bus.snoop_fanout::samples 3752130 # Request fanout histogram 884system.cpu.toL2Bus.snoop_fanout::mean 1.011131 # Request fanout histogram 885system.cpu.toL2Bus.snoop_fanout::stdev 0.104915 # Request fanout histogram |
| 874system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 875system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 886system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 887system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 876system.cpu.toL2Bus.snoop_fanout::1 3693818 98.88% 98.88% # Request fanout histogram 877system.cpu.toL2Bus.snoop_fanout::2 41766 1.12% 100.00% # Request fanout histogram | 888system.cpu.toL2Bus.snoop_fanout::1 3710365 98.89% 98.89% # Request fanout histogram 889system.cpu.toL2Bus.snoop_fanout::2 41765 1.11% 100.00% # Request fanout histogram |
| 878system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 879system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 880system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 890system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 891system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 892system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 881system.cpu.toL2Bus.snoop_fanout::total 3735584 # Request fanout histogram 882system.cpu.toL2Bus.reqLayer0.occupancy 2698164499 # Layer occupancy (ticks) | 893system.cpu.toL2Bus.snoop_fanout::total 3752130 # Request fanout histogram 894system.cpu.toL2Bus.reqLayer0.occupancy 2698163499 # Layer occupancy (ticks) |
| 883system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 884system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 885system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 895system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 896system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 897system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 886system.cpu.toL2Bus.respLayer0.occupancy 2193277658 # Layer occupancy (ticks) | 898system.cpu.toL2Bus.respLayer0.occupancy 2193277408 # Layer occupancy (ticks) |
| 887system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 899system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 888system.cpu.toL2Bus.respLayer1.occupancy 2194690407 # Layer occupancy (ticks) | 900system.cpu.toL2Bus.respLayer1.occupancy 2194687409 # Layer occupancy (ticks) |
| 889system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 890system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 891system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 892system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 893system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 894system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 895system.disk0.dma_write_txs 395 # Number of DMA write transactions. 896system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 56 unchanged lines hidden (view full) --- 953system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 954system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 955system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 956system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 957system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 958system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 959system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 960system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 901system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 902system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 903system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 904system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 905system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 906system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 907system.disk0.dma_write_txs 395 # Number of DMA write transactions. 908system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 56 unchanged lines hidden (view full) --- 965system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 966system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 967system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 968system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 969system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 970system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 971system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 972system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 961system.iobus.reqLayer29.occupancy 242093194 # Layer occupancy (ticks) | 973system.iobus.reqLayer29.occupancy 242092694 # Layer occupancy (ticks) |
| 962system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 963system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 964system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 965system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) 966system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 967system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) 968system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 969system.iocache.tags.replacements 41685 # number of replacements --- 15 unchanged lines hidden (view full) --- 985system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 986system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 987system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 988system.iocache.demand_misses::total 173 # number of demand (read+write) misses 989system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 990system.iocache.overall_misses::total 173 # number of overall misses 991system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles 992system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles | 974system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 975system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 976system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 977system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) 978system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 979system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) 980system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 981system.iocache.tags.replacements 41685 # number of replacements --- 15 unchanged lines hidden (view full) --- 997system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 998system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 999system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1000system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1001system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1002system.iocache.overall_misses::total 173 # number of overall misses 1003system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles 1004system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles |
| 993system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8777958811 # number of WriteInvalidateReq miss cycles 994system.iocache.WriteInvalidateReq_miss_latency::total 8777958811 # number of WriteInvalidateReq miss cycles | 1005system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775999311 # number of WriteInvalidateReq miss cycles 1006system.iocache.WriteInvalidateReq_miss_latency::total 8775999311 # number of WriteInvalidateReq miss cycles |
| 995system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles 996system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles 997system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles 998system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles 999system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1000system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1001system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1002system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 1009system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1010system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1011system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1012system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1013system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1014system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1015system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency 1016system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency | 1007system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles 1008system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles 1009system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles 1010system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles 1011system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1012system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1013system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1014system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 1021system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1022system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1023system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1024system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1025system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1026system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1027system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency 1028system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency |
| 1017system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211252.378008 # average WriteInvalidateReq miss latency 1018system.iocache.WriteInvalidateReq_avg_miss_latency::total 211252.378008 # average WriteInvalidateReq miss latency | 1029system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211205.220230 # average WriteInvalidateReq miss latency 1030system.iocache.WriteInvalidateReq_avg_miss_latency::total 211205.220230 # average WriteInvalidateReq miss latency |
| 1019system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency 1020system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency 1021system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency 1022system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency | 1031system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency 1032system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency 1033system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency 1034system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency |
| 1023system.iocache.blocked_cycles::no_mshrs 73082 # number of cycles access was blocked | 1035system.iocache.blocked_cycles::no_mshrs 73059 # number of cycles access was blocked |
| 1024system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1036system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1025system.iocache.blocked::no_mshrs 10004 # number of cycles access was blocked | 1037system.iocache.blocked::no_mshrs 10002 # number of cycles access was blocked |
| 1026system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1038system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1027system.iocache.avg_blocked_cycles::no_mshrs 7.305278 # average number of cycles each access was blocked | 1039system.iocache.avg_blocked_cycles::no_mshrs 7.304439 # average number of cycles each access was blocked |
| 1028system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1029system.iocache.fast_writes 0 # number of fast writes performed 1030system.iocache.cache_copies 0 # number of cache copies performed 1031system.iocache.writebacks::writebacks 41512 # number of writebacks 1032system.iocache.writebacks::total 41512 # number of writebacks 1033system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1034system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1035system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1036system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 1037system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1038system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1039system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1040system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1041system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles 1042system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles | 1040system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1041system.iocache.fast_writes 0 # number of fast writes performed 1042system.iocache.cache_copies 0 # number of cache copies performed 1043system.iocache.writebacks::writebacks 41512 # number of writebacks 1044system.iocache.writebacks::total 41512 # number of writebacks 1045system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1046system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1047system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1048system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 1049system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1050system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1051system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1052system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1053system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles 1054system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles |
| 1043system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6617254811 # number of WriteInvalidateReq MSHR miss cycles 1044system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6617254811 # number of WriteInvalidateReq MSHR miss cycles | 1055system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6615295311 # number of WriteInvalidateReq MSHR miss cycles 1056system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6615295311 # number of WriteInvalidateReq MSHR miss cycles |
| 1045system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles 1046system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles 1047system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles 1048system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles 1049system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1050system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1051system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1052system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1053system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1054system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1055system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1056system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1057system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency 1058system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency | 1057system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles 1058system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles 1059system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles 1060system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles 1061system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1062system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1063system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1064system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1065system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1066system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1067system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1068system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1069system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency 1070system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency |
| 1059system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159252.378008 # average WriteInvalidateReq mshr miss latency 1060system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159252.378008 # average WriteInvalidateReq mshr miss latency | 1071system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159205.220230 # average WriteInvalidateReq mshr miss latency 1072system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159205.220230 # average WriteInvalidateReq mshr miss latency |
| 1061system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency 1062system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency 1063system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency 1064system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency 1065system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1066system.membus.trans_dist::ReadReq 295757 # Transaction distribution 1067system.membus.trans_dist::ReadResp 295741 # Transaction distribution 1068system.membus.trans_dist::WriteReq 9619 # Transaction distribution 1069system.membus.trans_dist::WriteResp 9619 # Transaction distribution 1070system.membus.trans_dist::Writeback 118100 # Transaction distribution 1071system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1072system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution | 1073system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency 1074system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency 1075system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency 1076system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency 1077system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1078system.membus.trans_dist::ReadReq 295757 # Transaction distribution 1079system.membus.trans_dist::ReadResp 295741 # Transaction distribution 1080system.membus.trans_dist::WriteReq 9619 # Transaction distribution 1081system.membus.trans_dist::WriteResp 9619 # Transaction distribution 1082system.membus.trans_dist::Writeback 118100 # Transaction distribution 1083system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1084system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution |
| 1073system.membus.trans_dist::UpgradeReq 159 # Transaction distribution 1074system.membus.trans_dist::UpgradeResp 159 # Transaction distribution | 1085system.membus.trans_dist::UpgradeReq 161 # Transaction distribution 1086system.membus.trans_dist::UpgradeResp 161 # Transaction distribution |
| 1075system.membus.trans_dist::ReadExReq 116519 # Transaction distribution 1076system.membus.trans_dist::ReadExResp 116519 # Transaction distribution 1077system.membus.trans_dist::BadAddressError 16 # Transaction distribution 1078system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) | 1087system.membus.trans_dist::ReadExReq 116519 # Transaction distribution 1088system.membus.trans_dist::ReadExResp 116519 # Transaction distribution 1089system.membus.trans_dist::BadAddressError 16 # Transaction distribution 1090system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) |
| 1079system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886945 # Packet count per connected master and slave (bytes) | 1091system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886949 # Packet count per connected master and slave (bytes) |
| 1080system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) | 1092system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) |
| 1081system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920075 # Packet count per connected master and slave (bytes) | 1093system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920079 # Packet count per connected master and slave (bytes) |
| 1082system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1083system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) | 1094system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1095system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) |
| 1084system.membus.pkt_count::total 1044879 # Packet count per connected master and slave (bytes) | 1096system.membus.pkt_count::total 1044883 # Packet count per connected master and slave (bytes) |
| 1085system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) 1086system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30814208 # Cumulative packet size per connected master and slave (bytes) 1087system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30858524 # Cumulative packet size per connected master and slave (bytes) 1088system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1089system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) 1090system.membus.pkt_size::total 36175580 # Cumulative packet size per connected master and slave (bytes) 1091system.membus.snoops 433 # Total snoops (count) | 1097system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) 1098system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30814208 # Cumulative packet size per connected master and slave (bytes) 1099system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30858524 # Cumulative packet size per connected master and slave (bytes) 1100system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1101system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) 1102system.membus.pkt_size::total 36175580 # Cumulative packet size per connected master and slave (bytes) 1103system.membus.snoops 433 # Total snoops (count) |
| 1092system.membus.snoop_fanout::samples 565206 # Request fanout histogram | 1104system.membus.snoop_fanout::samples 581756 # Request fanout histogram |
| 1093system.membus.snoop_fanout::mean 1 # Request fanout histogram 1094system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1095system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1096system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1105system.membus.snoop_fanout::mean 1 # Request fanout histogram 1106system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1107system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1108system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1097system.membus.snoop_fanout::1 565206 100.00% 100.00% # Request fanout histogram | 1109system.membus.snoop_fanout::1 581756 100.00% 100.00% # Request fanout histogram |
| 1098system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1099system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1100system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1101system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1110system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1111system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1112system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1113system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1102system.membus.snoop_fanout::total 565206 # Request fanout histogram 1103system.membus.reqLayer0.occupancy 30238000 # Layer occupancy (ticks) | 1114system.membus.snoop_fanout::total 581756 # Request fanout histogram 1115system.membus.reqLayer0.occupancy 30242500 # Layer occupancy (ticks) |
| 1104system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1116system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1105system.membus.reqLayer1.occupancy 1230315562 # Layer occupancy (ticks) | 1117system.membus.reqLayer1.occupancy 1230317312 # Layer occupancy (ticks) |
| 1106system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1118system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1107system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) | 1119system.membus.reqLayer2.occupancy 21000 # Layer occupancy (ticks) |
| 1108system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1120system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1109system.membus.respLayer1.occupancy 2160768093 # Layer occupancy (ticks) | 1121system.membus.respLayer1.occupancy 2160772841 # Layer occupancy (ticks) |
| 1110system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1111system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) 1112system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1113system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1114system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1115system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1116system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1117system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 28 unchanged lines hidden --- | 1122system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1123system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) 1124system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1125system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1126system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1127system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1128system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1129system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 28 unchanged lines hidden --- |