| stats.txt (10513:ca4438b6e39a) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.883224 # Number of seconds simulated 4sim_ticks 1883224346500 # Number of ticks simulated 5final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.884241 # Number of seconds simulated 4sim_ticks 1884241273000 # Number of ticks simulated 5final_tick 1884241273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 279379 # Simulator instruction rate (inst/s) 8host_op_rate 279379 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9375076807 # Simulator tick rate (ticks/s) 10host_mem_usage 311380 # Number of bytes of host memory used 11host_seconds 200.88 # Real time elapsed on the host 12sim_insts 56120453 # Number of instructions simulated 13sim_ops 56120453 # Number of ops (including micro ops) simulated | 7host_inst_rate 193195 # Simulator instruction rate (inst/s) 8host_op_rate 193195 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6486085343 # Simulator tick rate (ticks/s) 10host_mem_usage 317148 # Number of bytes of host memory used 11host_seconds 290.51 # Real time elapsed on the host 12sim_insts 56124126 # Number of instructions simulated 13sim_ops 56124126 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 25931648 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 25914944 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 17system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::total 25932608 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4903936 # Number of bytes written to this memory 22system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7563264 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 405182 # Number of read requests responded to by this memory | 18system.physmem.bytes_read::total 25915904 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 1052928 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 1052928 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 7561408 # Number of bytes written to this memory 22system.physmem.bytes_written::total 7561408 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 404921 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 24system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::total 405197 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 76624 # Number of write requests responded to by this memory 28system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 118176 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 13769813 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::total 13770323 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::cpu.inst 559041 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::total 559041 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_write::writebacks 2604011 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_write::tsunami.ide 1412114 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4016125 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 2604011 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 13769813 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::total 17786448 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.readReqs 405197 # Number of read requests accepted 43system.physmem.writeReqs 118176 # Number of write requests accepted 44system.physmem.readBursts 405197 # Number of DRAM read bursts, including those serviced by the write queue 45system.physmem.writeBursts 118176 # Number of DRAM write bursts, including those merged in the write queue 46system.physmem.bytesReadDRAM 25920704 # Total number of bytes read from DRAM 47system.physmem.bytesReadWrQ 11904 # Total number of bytes read from write queue 48system.physmem.bytesWritten 7562112 # Total number of bytes written to DRAM 49system.physmem.bytesReadSys 25932608 # Total read bytes from the system interface side 50system.physmem.bytesWrittenSys 7563264 # Total written bytes from the system interface side 51system.physmem.servicedByWrQ 186 # Number of DRAM read bursts serviced by the write queue 52system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 53system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write 54system.physmem.perBankRdBursts::0 25484 # Per bank write bursts 55system.physmem.perBankRdBursts::1 25740 # Per bank write bursts 56system.physmem.perBankRdBursts::2 25857 # Per bank write bursts 57system.physmem.perBankRdBursts::3 25788 # Per bank write bursts 58system.physmem.perBankRdBursts::4 25237 # Per bank write bursts 59system.physmem.perBankRdBursts::5 24959 # Per bank write bursts | 25system.physmem.num_reads::total 404936 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 118147 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 118147 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 13753517 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 13754026 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 558807 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 558807 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 4012972 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 4012972 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 4012972 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 13753517 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 17766999 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 404936 # Number of read requests accepted 40system.physmem.writeReqs 159699 # Number of write requests accepted 41system.physmem.readBursts 404936 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 159699 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 25909568 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue 45system.physmem.bytesWritten 10083392 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 25915904 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 10220736 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 2126 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 153 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 25482 # Per bank write bursts 52system.physmem.perBankRdBursts::1 25742 # Per bank write bursts 53system.physmem.perBankRdBursts::2 25842 # Per bank write bursts 54system.physmem.perBankRdBursts::3 25776 # Per bank write bursts 55system.physmem.perBankRdBursts::4 25226 # Per bank write bursts 56system.physmem.perBankRdBursts::5 24953 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::6 24814 # Per bank write bursts | 57system.physmem.perBankRdBursts::6 24814 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::7 24586 # Per bank write bursts 62system.physmem.perBankRdBursts::8 25127 # Per bank write bursts 63system.physmem.perBankRdBursts::9 25284 # Per bank write bursts 64system.physmem.perBankRdBursts::10 25531 # Per bank write bursts 65system.physmem.perBankRdBursts::11 24857 # Per bank write bursts 66system.physmem.perBankRdBursts::12 24549 # Per bank write bursts 67system.physmem.perBankRdBursts::13 25592 # Per bank write bursts 68system.physmem.perBankRdBursts::14 25866 # Per bank write bursts 69system.physmem.perBankRdBursts::15 25740 # Per bank write bursts 70system.physmem.perBankWrBursts::0 7812 # Per bank write bursts 71system.physmem.perBankWrBursts::1 7680 # Per bank write bursts 72system.physmem.perBankWrBursts::2 8067 # Per bank write bursts 73system.physmem.perBankWrBursts::3 7745 # Per bank write bursts 74system.physmem.perBankWrBursts::4 7320 # Per bank write bursts 75system.physmem.perBankWrBursts::5 6957 # Per bank write bursts 76system.physmem.perBankWrBursts::6 6792 # Per bank write bursts 77system.physmem.perBankWrBursts::7 6401 # Per bank write bursts 78system.physmem.perBankWrBursts::8 7236 # Per bank write bursts 79system.physmem.perBankWrBursts::9 6892 # Per bank write bursts 80system.physmem.perBankWrBursts::10 7391 # Per bank write bursts 81system.physmem.perBankWrBursts::11 6866 # Per bank write bursts 82system.physmem.perBankWrBursts::12 7045 # Per bank write bursts 83system.physmem.perBankWrBursts::13 8010 # Per bank write bursts 84system.physmem.perBankWrBursts::14 7989 # Per bank write bursts 85system.physmem.perBankWrBursts::15 7955 # Per bank write bursts | 58system.physmem.perBankRdBursts::7 24563 # Per bank write bursts 59system.physmem.perBankRdBursts::8 25102 # Per bank write bursts 60system.physmem.perBankRdBursts::9 25273 # Per bank write bursts 61system.physmem.perBankRdBursts::10 25528 # Per bank write bursts 62system.physmem.perBankRdBursts::11 24851 # Per bank write bursts 63system.physmem.perBankRdBursts::12 24526 # Per bank write bursts 64system.physmem.perBankRdBursts::13 25574 # Per bank write bursts 65system.physmem.perBankRdBursts::14 25842 # Per bank write bursts 66system.physmem.perBankRdBursts::15 25743 # Per bank write bursts 67system.physmem.perBankWrBursts::0 10288 # Per bank write bursts 68system.physmem.perBankWrBursts::1 10037 # Per bank write bursts 69system.physmem.perBankWrBursts::2 10678 # Per bank write bursts 70system.physmem.perBankWrBursts::3 10053 # Per bank write bursts 71system.physmem.perBankWrBursts::4 9806 # Per bank write bursts 72system.physmem.perBankWrBursts::5 9437 # Per bank write bursts 73system.physmem.perBankWrBursts::6 9137 # Per bank write bursts 74system.physmem.perBankWrBursts::7 8750 # Per bank write bursts 75system.physmem.perBankWrBursts::8 9885 # Per bank write bursts 76system.physmem.perBankWrBursts::9 8937 # Per bank write bursts 77system.physmem.perBankWrBursts::10 9881 # Per bank write bursts 78system.physmem.perBankWrBursts::11 9301 # Per bank write bursts 79system.physmem.perBankWrBursts::12 9770 # Per bank write bursts 80system.physmem.perBankWrBursts::13 10691 # Per bank write bursts 81system.physmem.perBankWrBursts::14 10395 # Per bank write bursts 82system.physmem.perBankWrBursts::15 10507 # Per bank write bursts |
| 86system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 87system.physmem.numWrRetry 7 # Number of times write queue was full causing retry 88system.physmem.totGap 1883215617500 # Total gap between requests | 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 1884232486500 # Total gap between requests |
| 89system.physmem.readPktSize::0 0 # Read request sizes (log2) 90system.physmem.readPktSize::1 0 # Read request sizes (log2) 91system.physmem.readPktSize::2 0 # Read request sizes (log2) 92system.physmem.readPktSize::3 0 # Read request sizes (log2) 93system.physmem.readPktSize::4 0 # Read request sizes (log2) 94system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 95system.physmem.readPktSize::6 405197 # Read request sizes (log2) | 92system.physmem.readPktSize::6 404936 # Read request sizes (log2) |
| 96system.physmem.writePktSize::0 0 # Write request sizes (log2) 97system.physmem.writePktSize::1 0 # Write request sizes (log2) 98system.physmem.writePktSize::2 0 # Write request sizes (log2) 99system.physmem.writePktSize::3 0 # Write request sizes (log2) 100system.physmem.writePktSize::4 0 # Write request sizes (log2) 101system.physmem.writePktSize::5 0 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 102system.physmem.writePktSize::6 118176 # Write request sizes (log2) 103system.physmem.rdQLenPdf::0 402689 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::1 2242 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see | 99system.physmem.writePktSize::6 159699 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 402545 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 2209 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 142system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 103system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 150system.physmem.wrQLenPdf::15 1502 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::16 2155 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::18 5922 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::19 6116 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::21 7165 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::22 8341 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::24 8743 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::25 8450 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::26 8575 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::27 7104 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::28 6692 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::29 5817 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::30 5536 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::31 5545 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::32 5502 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::34 184 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::35 186 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::36 168 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::43 152 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::49 96 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::53 94 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::55 125 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see 199system.physmem.bytesPerActivate::samples 63140 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::mean 530.294837 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::gmean 322.585016 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::stdev 415.640457 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::0-127 14650 23.20% 23.20% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::128-255 10589 16.77% 39.97% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::256-383 5075 8.04% 48.01% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::384-511 3003 4.76% 52.77% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::512-639 2370 3.75% 56.52% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::640-767 2105 3.33% 59.85% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::768-895 1364 2.16% 62.01% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::896-1023 1607 2.55% 64.56% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::1024-1151 22377 35.44% 100.00% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::total 63140 # Bytes accessed per row activation 213system.physmem.rdPerTurnAround::samples 5316 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::mean 76.186983 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::stdev 2896.748549 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::0-8191 5313 99.94% 99.94% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes | 147system.physmem.wrQLenPdf::15 1884 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 3925 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 8041 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 9181 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 9850 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 10687 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 11113 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 12053 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 11634 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 11766 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 10716 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 9987 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 8498 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 8067 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 6879 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 6438 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 6292 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 6203 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 397 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 371 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 339 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 278 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 254 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 248 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 226 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 219 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 65749 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 547.429771 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 335.789885 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 418.130322 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 14719 22.39% 22.39% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 10714 16.30% 38.68% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 4807 7.31% 45.99% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 3176 4.83% 50.82% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2550 3.88% 54.70% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1953 2.97% 57.67% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1437 2.19% 59.86% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1697 2.58% 62.44% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 24696 37.56% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 65749 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5738 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 70.553154 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 2788.767091 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-8191 5735 99.95% 99.95% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 215system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 220system.physmem.rdPerTurnAround::total 5316 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 5316 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 22.226862 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 18.933757 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 20.590348 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16-19 4662 87.70% 87.70% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::20-23 15 0.28% 87.98% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::24-27 21 0.40% 88.37% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::28-31 225 4.23% 92.61% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-35 46 0.87% 93.47% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::36-39 10 0.19% 93.66% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::40-43 7 0.13% 93.79% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::44-47 7 0.13% 93.92% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::48-51 19 0.36% 94.28% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::52-55 3 0.06% 94.34% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::56-59 2 0.04% 94.38% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::60-63 2 0.04% 94.41% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::64-67 12 0.23% 94.64% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::68-71 1 0.02% 94.66% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::72-75 6 0.11% 94.77% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::80-83 29 0.55% 95.32% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::84-87 14 0.26% 95.58% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::88-91 2 0.04% 95.62% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::92-95 12 0.23% 95.84% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::96-99 164 3.09% 98.93% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::100-103 5 0.09% 99.02% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::104-107 1 0.02% 99.04% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::112-115 2 0.04% 99.08% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::120-123 3 0.06% 99.13% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::124-127 1 0.02% 99.15% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::128-131 4 0.08% 99.23% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::132-135 3 0.06% 99.29% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::136-139 8 0.15% 99.44% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::140-143 6 0.11% 99.55% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::144-147 12 0.23% 99.77% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::148-151 1 0.02% 99.79% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::152-155 3 0.06% 99.85% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::164-167 1 0.02% 99.87% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::168-171 1 0.02% 99.89% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::176-179 3 0.06% 99.94% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 5316 # Writes before turning the bus around for reads 262system.physmem.totQLat 2156220500 # Total ticks spent queuing 263system.physmem.totMemAccLat 9750176750 # Total ticks spent from burst creation until serviced by the DRAM 264system.physmem.totBusLat 2025055000 # Total ticks spent in databus transfers 265system.physmem.avgQLat 5323.86 # Average queueing delay per DRAM burst | 217system.physmem.rdPerTurnAround::total 5738 # Reads before turning the bus around for writes 218system.physmem.wrPerTurnAround::samples 5738 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::mean 27.457825 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::gmean 20.746842 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::stdev 34.017596 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::16-23 4693 81.79% 81.79% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::24-31 187 3.26% 85.05% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::32-39 275 4.79% 89.84% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::40-47 67 1.17% 91.01% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::48-55 92 1.60% 92.61% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::56-63 47 0.82% 93.43% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::64-71 24 0.42% 93.85% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::72-79 11 0.19% 94.04% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::80-87 19 0.33% 94.37% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::88-95 7 0.12% 94.49% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::96-103 14 0.24% 94.74% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::104-111 6 0.10% 94.84% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::112-119 7 0.12% 94.96% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::120-127 4 0.07% 95.03% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::128-135 17 0.30% 95.33% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::136-143 47 0.82% 96.15% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::144-151 17 0.30% 96.44% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::152-159 17 0.30% 96.74% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::160-167 79 1.38% 98.12% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::168-175 32 0.56% 98.68% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::176-183 20 0.35% 99.02% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::184-191 19 0.33% 99.36% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::192-199 15 0.26% 99.62% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::200-207 7 0.12% 99.74% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::208-215 4 0.07% 99.81% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::216-223 3 0.05% 99.86% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::224-231 1 0.02% 99.88% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::232-239 3 0.05% 99.93% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::total 5738 # Writes before turning the bus around for reads 254system.physmem.totQLat 2167079250 # Total ticks spent queuing 255system.physmem.totMemAccLat 9757773000 # Total ticks spent from burst creation until serviced by the DRAM 256system.physmem.totBusLat 2024185000 # Total ticks spent in databus transfers 257system.physmem.avgQLat 5352.97 # Average queueing delay per DRAM burst |
| 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 258system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 267system.physmem.avgMemAccLat 24073.86 # Average memory access latency per DRAM burst 268system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 4.02 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s | 259system.physmem.avgMemAccLat 24102.97 # Average memory access latency per DRAM burst 260system.physmem.avgRdBW 13.75 # Average DRAM read bandwidth in MiByte/s 261system.physmem.avgWrBW 5.35 # Average achieved write bandwidth in MiByte/s 262system.physmem.avgRdBWSys 13.75 # Average system read bandwidth in MiByte/s 263system.physmem.avgWrBWSys 5.42 # Average system write bandwidth in MiByte/s |
| 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 264system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 273system.physmem.busUtil 0.14 # Data bus utilization in percentage | 265system.physmem.busUtil 0.15 # Data bus utilization in percentage |
| 274system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads | 266system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads |
| 275system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 267system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes |
| 276system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 268system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 277system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing 278system.physmem.readRowHits 364400 # Number of row buffer hits during reads 279system.physmem.writeRowHits 95629 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 89.97 # Row buffer hit rate for reads 281system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes 282system.physmem.avgGap 3598228.45 # Average gap between requests 283system.physmem.pageHitRate 87.93 # Row buffer hit rate, read and write combined 284system.physmem.memoryStateTime::IDLE 1774012993500 # Time in different power states 285system.physmem.memoryStateTime::REF 62884900000 # Time in different power states | 269system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing 270system.physmem.readRowHits 364185 # Number of row buffer hits during reads 271system.physmem.writeRowHits 132456 # Number of row buffer hits during writes 272system.physmem.readRowHitRate 89.96 # Row buffer hit rate for reads 273system.physmem.writeRowHitRate 84.06 # Row buffer hit rate for writes 274system.physmem.avgGap 3337080.57 # Average gap between requests 275system.physmem.pageHitRate 88.31 # Row buffer hit rate, read and write combined 276system.physmem.memoryStateTime::IDLE 1774592996500 # Time in different power states 277system.physmem.memoryStateTime::REF 62918700000 # Time in different power states |
| 286system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 278system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 287system.physmem.memoryStateTime::ACT 46323736500 # Time in different power states | 279system.physmem.memoryStateTime::ACT 46722146000 # Time in different power states |
| 288system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 280system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 289system.physmem.actEnergy::0 232613640 # Energy for activate commands per rank (pJ) 290system.physmem.actEnergy::1 244724760 # Energy for activate commands per rank (pJ) 291system.physmem.preEnergy::0 126922125 # Energy for precharge commands per rank (pJ) 292system.physmem.preEnergy::1 133530375 # Energy for precharge commands per rank (pJ) 293system.physmem.readEnergy::0 1579227000 # Energy for read commands per rank (pJ) 294system.physmem.readEnergy::1 1579858800 # Energy for read commands per rank (pJ) 295system.physmem.writeEnergy::0 380855520 # Energy for write commands per rank (pJ) 296system.physmem.writeEnergy::1 384808320 # Energy for write commands per rank (pJ) 297system.physmem.refreshEnergy::0 123002864400 # Energy for refresh commands per rank (pJ) 298system.physmem.refreshEnergy::1 123002864400 # Energy for refresh commands per rank (pJ) 299system.physmem.actBackEnergy::0 59595719580 # Energy for active background per rank (pJ) 300system.physmem.actBackEnergy::1 60657122565 # Energy for active background per rank (pJ) 301system.physmem.preBackEnergy::0 1077656022750 # Energy for precharge background per rank (pJ) 302system.physmem.preBackEnergy::1 1076724967500 # Energy for precharge background per rank (pJ) 303system.physmem.totalEnergy::0 1262574225015 # Total energy per rank (pJ) 304system.physmem.totalEnergy::1 1262727876720 # Total energy per rank (pJ) 305system.physmem.averagePower::0 670.433163 # Core power per rank (mW) 306system.physmem.averagePower::1 670.514753 # Core power per rank (mW) 307system.membus.trans_dist::ReadReq 295760 # Transaction distribution 308system.membus.trans_dist::ReadResp 295744 # Transaction distribution 309system.membus.trans_dist::WriteReq 9618 # Transaction distribution 310system.membus.trans_dist::WriteResp 9618 # Transaction distribution 311system.membus.trans_dist::Writeback 76624 # Transaction distribution 312system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 313system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 314system.membus.trans_dist::UpgradeReq 154 # Transaction distribution 315system.membus.trans_dist::UpgradeResp 154 # Transaction distribution 316system.membus.trans_dist::ReadExReq 116541 # Transaction distribution 317system.membus.trans_dist::ReadExResp 116541 # Transaction distribution 318system.membus.trans_dist::BadAddressError 16 # Transaction distribution 319system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes) 320system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887296 # Packet count per connected master and slave (bytes) 321system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) 322system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920424 # Packet count per connected master and slave (bytes) 323system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) 324system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) 325system.membus.pkt_count::total 1003716 # Packet count per connected master and slave (bytes) 326system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes) 327system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30835584 # Cumulative packet size per connected master and slave (bytes) 328system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30879892 # Cumulative packet size per connected master and slave (bytes) 329system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 330system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 331system.membus.pkt_size::total 33540180 # Cumulative packet size per connected master and slave (bytes) 332system.membus.snoops 158 # Total snoops (count) 333system.membus.snoop_fanout::samples 523708 # Request fanout histogram 334system.membus.snoop_fanout::mean 1 # Request fanout histogram 335system.membus.snoop_fanout::stdev 0 # Request fanout histogram 336system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 337system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 338system.membus.snoop_fanout::1 523708 100.00% 100.00% # Request fanout histogram 339system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 340system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 341system.membus.snoop_fanout::min_value 1 # Request fanout histogram 342system.membus.snoop_fanout::max_value 1 # Request fanout histogram 343system.membus.snoop_fanout::total 523708 # Request fanout histogram 344system.membus.reqLayer0.occupancy 30927500 # Layer occupancy (ticks) 345system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 346system.membus.reqLayer1.occupancy 1547261750 # Layer occupancy (ticks) 347system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 348system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) 349system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 350system.membus.respLayer1.occupancy 3825161596 # Layer occupancy (ticks) 351system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 352system.membus.respLayer2.occupancy 43114249 # Layer occupancy (ticks) 353system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 354system.iocache.tags.replacements 41685 # number of replacements 355system.iocache.tags.tagsinuse 1.288180 # Cycle average of tags in use 356system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 357system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 358system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 359system.iocache.tags.warmup_cycle 1728025257000 # Cycle when the warmup percentage was hit. 360system.iocache.tags.occ_blocks::tsunami.ide 1.288180 # Average occupied blocks per requestor 361system.iocache.tags.occ_percent::tsunami.ide 0.080511 # Average percentage of cache occupancy 362system.iocache.tags.occ_percent::total 0.080511 # Average percentage of cache occupancy 363system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 364system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 365system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 366system.iocache.tags.tag_accesses 375525 # Number of tag accesses 367system.iocache.tags.data_accesses 375525 # Number of data accesses 368system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 369system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 370system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 371system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 372system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 373system.iocache.demand_misses::total 173 # number of demand (read+write) misses 374system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 375system.iocache.overall_misses::total 173 # number of overall misses 376system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 377system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 378system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 379system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 380system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 381system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles 382system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 383system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 384system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 385system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 386system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 387system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 388system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 389system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 390system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 391system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 392system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 393system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 394system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 395system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 396system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 397system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 398system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 399system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency 400system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 401system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency 402system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 403system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 404system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 405system.iocache.blocked::no_targets 0 # number of cycles access was blocked 406system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 407system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 408system.iocache.fast_writes 41552 # number of fast writes performed 409system.iocache.cache_copies 0 # number of cache copies performed 410system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 411system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 412system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 413system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 414system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 415system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 416system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 417system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 418system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512658057 # number of WriteInvalidateReq MSHR miss cycles 419system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512658057 # number of WriteInvalidateReq MSHR miss cycles 420system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 421system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 422system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 423system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 424system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 425system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 426system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 427system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 428system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 429system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 430system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 431system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency 432system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency 433system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 434system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 435system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 436system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 437system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 438system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 439system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 440system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 441system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 442system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 443system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 444system.disk0.dma_write_txs 395 # Number of DMA write transactions. 445system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 446system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 447system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 448system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 449system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 450system.disk2.dma_write_txs 1 # Number of DMA write transactions. 451system.cpu.branchPred.lookups 14964931 # Number of BP lookups 452system.cpu.branchPred.condPredicted 12983118 # Number of conditional branches predicted 453system.cpu.branchPred.condIncorrect 374694 # Number of conditional branches incorrect 454system.cpu.branchPred.BTBLookups 9691016 # Number of BTB lookups 455system.cpu.branchPred.BTBHits 5184483 # Number of BTB hits | 281system.physmem.actEnergy::0 242668440 # Energy for activate commands per rank (pJ) 282system.physmem.actEnergy::1 254394000 # Energy for activate commands per rank (pJ) 283system.physmem.preEnergy::0 132408375 # Energy for precharge commands per rank (pJ) 284system.physmem.preEnergy::1 138806250 # Energy for precharge commands per rank (pJ) 285system.physmem.readEnergy::0 1578704400 # Energy for read commands per rank (pJ) 286system.physmem.readEnergy::1 1579024200 # Energy for read commands per rank (pJ) 287system.physmem.writeEnergy::0 506645280 # Energy for write commands per rank (pJ) 288system.physmem.writeEnergy::1 514298160 # Energy for write commands per rank (pJ) 289system.physmem.refreshEnergy::0 123068977200 # Energy for refresh commands per rank (pJ) 290system.physmem.refreshEnergy::1 123068977200 # Energy for refresh commands per rank (pJ) 291system.physmem.actBackEnergy::0 59931006120 # Energy for active background per rank (pJ) 292system.physmem.actBackEnergy::1 60719870160 # Energy for active background per rank (pJ) 293system.physmem.preBackEnergy::0 1077969239250 # Energy for precharge background per rank (pJ) 294system.physmem.preBackEnergy::1 1077277253250 # Energy for precharge background per rank (pJ) 295system.physmem.totalEnergy::0 1263429649065 # Total energy per rank (pJ) 296system.physmem.totalEnergy::1 1263552623220 # Total energy per rank (pJ) 297system.physmem.averagePower::0 670.526996 # Core power per rank (mW) 298system.physmem.averagePower::1 670.592261 # Core power per rank (mW) 299system.cpu.branchPred.lookups 15011318 # Number of BP lookups 300system.cpu.branchPred.condPredicted 13019220 # Number of conditional branches predicted 301system.cpu.branchPred.condIncorrect 376037 # Number of conditional branches incorrect 302system.cpu.branchPred.BTBLookups 9980368 # Number of BTB lookups 303system.cpu.branchPred.BTBHits 5204970 # Number of BTB hits |
| 456system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 304system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 457system.cpu.branchPred.BTBHitPct 53.497827 # BTB Hit Percentage 458system.cpu.branchPred.usedRAS 807557 # Number of times the RAS was used to get a target. 459system.cpu.branchPred.RASInCorrect 32108 # Number of incorrect RAS predictions. | 305system.cpu.branchPred.BTBHitPct 52.152085 # BTB Hit Percentage 306system.cpu.branchPred.usedRAS 808971 # Number of times the RAS was used to get a target. 307system.cpu.branchPred.RASInCorrect 32603 # Number of incorrect RAS predictions. |
| 460system.cpu_clk_domain.clock 500 # Clock period in ticks 461system.cpu.dtb.fetch_hits 0 # ITB hits 462system.cpu.dtb.fetch_misses 0 # ITB misses 463system.cpu.dtb.fetch_acv 0 # ITB acv 464system.cpu.dtb.fetch_accesses 0 # ITB accesses | 308system.cpu_clk_domain.clock 500 # Clock period in ticks 309system.cpu.dtb.fetch_hits 0 # ITB hits 310system.cpu.dtb.fetch_misses 0 # ITB misses 311system.cpu.dtb.fetch_acv 0 # ITB acv 312system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 465system.cpu.dtb.read_hits 9237824 # DTB read hits 466system.cpu.dtb.read_misses 17804 # DTB read misses | 313system.cpu.dtb.read_hits 9241438 # DTB read hits 314system.cpu.dtb.read_misses 17791 # DTB read misses |
| 467system.cpu.dtb.read_acv 211 # DTB read access violations | 315system.cpu.dtb.read_acv 211 # DTB read access violations |
| 468system.cpu.dtb.read_accesses 766148 # DTB read accesses 469system.cpu.dtb.write_hits 6384867 # DTB write hits 470system.cpu.dtb.write_misses 2306 # DTB write misses | 316system.cpu.dtb.read_accesses 766265 # DTB read accesses 317system.cpu.dtb.write_hits 6385998 # DTB write hits 318system.cpu.dtb.write_misses 2317 # DTB write misses |
| 471system.cpu.dtb.write_acv 159 # DTB write access violations | 319system.cpu.dtb.write_acv 159 # DTB write access violations |
| 472system.cpu.dtb.write_accesses 298467 # DTB write accesses 473system.cpu.dtb.data_hits 15622691 # DTB hits 474system.cpu.dtb.data_misses 20110 # DTB misses | 320system.cpu.dtb.write_accesses 298404 # DTB write accesses 321system.cpu.dtb.data_hits 15627436 # DTB hits 322system.cpu.dtb.data_misses 20108 # DTB misses |
| 475system.cpu.dtb.data_acv 370 # DTB access violations | 323system.cpu.dtb.data_acv 370 # DTB access violations |
| 476system.cpu.dtb.data_accesses 1064615 # DTB accesses 477system.cpu.itb.fetch_hits 3999749 # ITB hits 478system.cpu.itb.fetch_misses 6851 # ITB misses 479system.cpu.itb.fetch_acv 647 # ITB acv 480system.cpu.itb.fetch_accesses 4006600 # ITB accesses | 324system.cpu.dtb.data_accesses 1064669 # DTB accesses 325system.cpu.itb.fetch_hits 4019003 # ITB hits 326system.cpu.itb.fetch_misses 6884 # ITB misses 327system.cpu.itb.fetch_acv 661 # ITB acv 328system.cpu.itb.fetch_accesses 4025887 # ITB accesses |
| 481system.cpu.itb.read_hits 0 # DTB read hits 482system.cpu.itb.read_misses 0 # DTB read misses 483system.cpu.itb.read_acv 0 # DTB read access violations 484system.cpu.itb.read_accesses 0 # DTB read accesses 485system.cpu.itb.write_hits 0 # DTB write hits 486system.cpu.itb.write_misses 0 # DTB write misses 487system.cpu.itb.write_acv 0 # DTB write access violations 488system.cpu.itb.write_accesses 0 # DTB write accesses 489system.cpu.itb.data_hits 0 # DTB hits 490system.cpu.itb.data_misses 0 # DTB misses 491system.cpu.itb.data_acv 0 # DTB access violations 492system.cpu.itb.data_accesses 0 # DTB accesses | 329system.cpu.itb.read_hits 0 # DTB read hits 330system.cpu.itb.read_misses 0 # DTB read misses 331system.cpu.itb.read_acv 0 # DTB read access violations 332system.cpu.itb.read_accesses 0 # DTB read accesses 333system.cpu.itb.write_hits 0 # DTB write hits 334system.cpu.itb.write_misses 0 # DTB write misses 335system.cpu.itb.write_acv 0 # DTB write access violations 336system.cpu.itb.write_accesses 0 # DTB write accesses 337system.cpu.itb.data_hits 0 # DTB hits 338system.cpu.itb.data_misses 0 # DTB misses 339system.cpu.itb.data_acv 0 # DTB access violations 340system.cpu.itb.data_accesses 0 # DTB accesses |
| 493system.cpu.numCycles 174888375 # number of cpu cycles simulated | 341system.cpu.numCycles 175285694 # number of cpu cycles simulated |
| 494system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 495system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 342system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 343system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 496system.cpu.committedInsts 56120453 # Number of instructions committed 497system.cpu.committedOps 56120453 # Number of ops (including micro ops) committed 498system.cpu.discardedOps 2530516 # Number of ops (including micro ops) which were discarded before commit 499system.cpu.numFetchSuspends 5527 # Number of times Execute suspended instruction fetching 500system.cpu.quiesceCycles 3591560318 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 501system.cpu.cpi 3.116304 # CPI: cycles per instruction 502system.cpu.ipc 0.320893 # IPC: instructions per cycle | 344system.cpu.committedInsts 56124126 # Number of instructions committed 345system.cpu.committedOps 56124126 # Number of ops (including micro ops) committed 346system.cpu.discardedOps 2495853 # Number of ops (including micro ops) which were discarded before commit 347system.cpu.numFetchSuspends 5575 # Number of times Execute suspended instruction fetching 348system.cpu.quiesceCycles 3593196852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 349system.cpu.cpi 3.123179 # CPI: cycles per instruction 350system.cpu.ipc 0.320187 # IPC: instructions per cycle |
| 503system.cpu.kern.inst.arm 0 # number of arm instructions executed | 351system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 504system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed 505system.cpu.kern.inst.hwrei 211459 # number of hwrei instructions executed 506system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl | 352system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed 353system.cpu.kern.inst.hwrei 211480 # number of hwrei instructions executed 354system.cpu.kern.ipl_count::0 74791 40.94% 40.94% # number of times we switched to this ipl |
| 507system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl | 355system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl |
| 508system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl 509system.cpu.kern.ipl_count::31 105855 57.95% 100.00% # number of times we switched to this ipl 510system.cpu.kern.ipl_count::total 182673 # number of times we switched to this ipl 511system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 356system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl 357system.cpu.kern.ipl_count::31 105868 57.95% 100.00% # number of times we switched to this ipl 358system.cpu.kern.ipl_count::total 182691 # number of times we switched to this ipl 359system.cpu.kern.ipl_good::0 73424 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 512system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl | 360system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl |
| 513system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl 514system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl 515system.cpu.kern.ipl_good::total 148871 # number of times we switched to this ipl from a different ipl 516system.cpu.kern.ipl_ticks::0 1832868777500 97.33% 97.33% # number of cycles we spent at this ipl 517system.cpu.kern.ipl_ticks::21 80360500 0.00% 97.33% # number of cycles we spent at this ipl 518system.cpu.kern.ipl_ticks::22 672864500 0.04% 97.37% # number of cycles we spent at this ipl 519system.cpu.kern.ipl_ticks::31 49601349000 2.63% 100.00% # number of cycles we spent at this ipl 520system.cpu.kern.ipl_ticks::total 1883223351500 # number of cycles we spent at this ipl 521system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl | 361system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl 362system.cpu.kern.ipl_good::31 73424 49.32% 100.00% # number of times we switched to this ipl from a different ipl 363system.cpu.kern.ipl_good::total 148880 # number of times we switched to this ipl from a different ipl 364system.cpu.kern.ipl_ticks::0 1833816082000 97.32% 97.32% # number of cycles we spent at this ipl 365system.cpu.kern.ipl_ticks::21 80474500 0.00% 97.33% # number of cycles we spent at this ipl 366system.cpu.kern.ipl_ticks::22 673053000 0.04% 97.36% # number of cycles we spent at this ipl 367system.cpu.kern.ipl_ticks::31 49670669500 2.64% 100.00% # number of cycles we spent at this ipl 368system.cpu.kern.ipl_ticks::total 1884240279000 # number of cycles we spent at this ipl 369system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl |
| 522system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 523system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 370system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 371system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 524system.cpu.kern.ipl_used::31 0.693590 # fraction of swpipl calls that actually changed the ipl 525system.cpu.kern.ipl_used::total 0.814959 # fraction of swpipl calls that actually changed the ipl | 372system.cpu.kern.ipl_used::31 0.693543 # fraction of swpipl calls that actually changed the ipl 373system.cpu.kern.ipl_used::total 0.814928 # fraction of swpipl calls that actually changed the ipl |
| 526system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 527system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 528system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 529system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 530system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 531system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 532system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 533system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 553system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 554system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 555system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 556system.cpu.kern.syscall::total 326 # number of syscalls executed 557system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 558system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 559system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 560system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 374system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 375system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 376system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 377system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 378system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 379system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 380system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 381system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 401system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 402system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 403system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 404system.cpu.kern.syscall::total 326 # number of syscalls executed 405system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 406system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 407system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 408system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 561system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed | 409system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed |
| 562system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 563system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 410system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 411system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 564system.cpu.kern.callpal::swpipl 175516 91.23% 93.43% # number of callpals executed 565system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed 566system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed | 412system.cpu.kern.callpal::swpipl 175532 91.22% 93.43% # number of callpals executed 413system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed 414system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed |
| 567system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 568system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 569system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed | 415system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 416system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 417system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed |
| 570system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed | 418system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed |
| 571system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 572system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 419system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 420system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 573system.cpu.kern.callpal::total 192398 # number of callpals executed 574system.cpu.kern.mode_switch::kernel 5867 # number of protection mode switches 575system.cpu.kern.mode_switch::user 1741 # number of protection mode switches | 421system.cpu.kern.callpal::total 192418 # number of callpals executed 422system.cpu.kern.mode_switch::kernel 5870 # number of protection mode switches 423system.cpu.kern.mode_switch::user 1743 # number of protection mode switches |
| 576system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches | 424system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches |
| 577system.cpu.kern.mode_good::kernel 1910 578system.cpu.kern.mode_good::user 1741 579system.cpu.kern.mode_good::idle 169 580system.cpu.kern.mode_switch_good::kernel 0.325550 # fraction of useful protection mode switches | 425system.cpu.kern.mode_good::kernel 1913 426system.cpu.kern.mode_good::user 1743 427system.cpu.kern.mode_good::idle 170 428system.cpu.kern.mode_switch_good::kernel 0.325894 # fraction of useful protection mode switches |
| 581system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 429system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 582system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches 583system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches 584system.cpu.kern.mode_ticks::kernel 36222818500 1.92% 1.92% # number of ticks spent at the given mode 585system.cpu.kern.mode_ticks::user 4061127000 0.22% 2.14% # number of ticks spent at the given mode 586system.cpu.kern.mode_ticks::idle 1842939396000 97.86% 100.00% # number of ticks spent at the given mode 587system.cpu.kern.swap_context 4175 # number of times the context was actually changed 588system.cpu.tickCycles 83840328 # Number of cycles that the object actually ticked 589system.cpu.idleCycles 91048047 # Total number of cycles that the object has spent stopped 590system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 591system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 592system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 593system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 594system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 595system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 596system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 597system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 598system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 599system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 600system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 601system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 602system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 603system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 604system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 605system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 606system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 607system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 608system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 609system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 610system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 611system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 612system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 613system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 614system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 615system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 616system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 617system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 618system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 619system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 620system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 430system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches 431system.cpu.kern.mode_switch_good::total 0.393986 # fraction of useful protection mode switches 432system.cpu.kern.mode_ticks::kernel 36270859500 1.92% 1.92% # number of ticks spent at the given mode 433system.cpu.kern.mode_ticks::user 4083023000 0.22% 2.14% # number of ticks spent at the given mode 434system.cpu.kern.mode_ticks::idle 1843886386500 97.86% 100.00% # number of ticks spent at the given mode 435system.cpu.kern.swap_context 4177 # number of times the context was actually changed 436system.cpu.tickCycles 84485847 # Number of cycles that the object actually ticked 437system.cpu.idleCycles 90799847 # Total number of cycles that the object has spent stopped 438system.cpu.dcache.tags.replacements 1395229 # number of replacements 439system.cpu.dcache.tags.tagsinuse 511.982334 # Cycle average of tags in use 440system.cpu.dcache.tags.total_refs 13773041 # Total number of references to valid blocks. 441system.cpu.dcache.tags.sampled_refs 1395741 # Sample count of references to valid blocks. 442system.cpu.dcache.tags.avg_refs 9.867906 # Average number of references to valid blocks. 443system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit. 444system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982334 # Average occupied blocks per requestor 445system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy 447system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 449system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 450system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 451system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 452system.cpu.dcache.tags.tag_accesses 63657366 # Number of tag accesses 453system.cpu.dcache.tags.data_accesses 63657366 # Number of data accesses 454system.cpu.dcache.ReadReq_hits::cpu.inst 7814636 # number of ReadReq hits 455system.cpu.dcache.ReadReq_hits::total 7814636 # number of ReadReq hits 456system.cpu.dcache.WriteReq_hits::cpu.inst 5576637 # number of WriteReq hits 457system.cpu.dcache.WriteReq_hits::total 5576637 # number of WriteReq hits 458system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182736 # number of LoadLockedReq hits 459system.cpu.dcache.LoadLockedReq_hits::total 182736 # number of LoadLockedReq hits 460system.cpu.dcache.StoreCondReq_hits::cpu.inst 198999 # number of StoreCondReq hits 461system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits 462system.cpu.dcache.demand_hits::cpu.inst 13391273 # number of demand (read+write) hits 463system.cpu.dcache.demand_hits::total 13391273 # number of demand (read+write) hits 464system.cpu.dcache.overall_hits::cpu.inst 13391273 # number of overall hits 465system.cpu.dcache.overall_hits::total 13391273 # number of overall hits 466system.cpu.dcache.ReadReq_misses::cpu.inst 1201532 # number of ReadReq misses 467system.cpu.dcache.ReadReq_misses::total 1201532 # number of ReadReq misses 468system.cpu.dcache.WriteReq_misses::cpu.inst 573582 # number of WriteReq misses 469system.cpu.dcache.WriteReq_misses::total 573582 # number of WriteReq misses 470system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17284 # number of LoadLockedReq misses 471system.cpu.dcache.LoadLockedReq_misses::total 17284 # number of LoadLockedReq misses 472system.cpu.dcache.demand_misses::cpu.inst 1775114 # number of demand (read+write) misses 473system.cpu.dcache.demand_misses::total 1775114 # number of demand (read+write) misses 474system.cpu.dcache.overall_misses::cpu.inst 1775114 # number of overall misses 475system.cpu.dcache.overall_misses::total 1775114 # number of overall misses 476system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31036730750 # number of ReadReq miss cycles 477system.cpu.dcache.ReadReq_miss_latency::total 31036730750 # number of ReadReq miss cycles 478system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20700048539 # number of WriteReq miss cycles 479system.cpu.dcache.WriteReq_miss_latency::total 20700048539 # number of WriteReq miss cycles 480system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231020000 # number of LoadLockedReq miss cycles 481system.cpu.dcache.LoadLockedReq_miss_latency::total 231020000 # number of LoadLockedReq miss cycles 482system.cpu.dcache.demand_miss_latency::cpu.inst 51736779289 # number of demand (read+write) miss cycles 483system.cpu.dcache.demand_miss_latency::total 51736779289 # number of demand (read+write) miss cycles 484system.cpu.dcache.overall_miss_latency::cpu.inst 51736779289 # number of overall miss cycles 485system.cpu.dcache.overall_miss_latency::total 51736779289 # number of overall miss cycles 486system.cpu.dcache.ReadReq_accesses::cpu.inst 9016168 # number of ReadReq accesses(hits+misses) 487system.cpu.dcache.ReadReq_accesses::total 9016168 # number of ReadReq accesses(hits+misses) 488system.cpu.dcache.WriteReq_accesses::cpu.inst 6150219 # number of WriteReq accesses(hits+misses) 489system.cpu.dcache.WriteReq_accesses::total 6150219 # number of WriteReq accesses(hits+misses) 490system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200020 # number of LoadLockedReq accesses(hits+misses) 491system.cpu.dcache.LoadLockedReq_accesses::total 200020 # number of LoadLockedReq accesses(hits+misses) 492system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198999 # number of StoreCondReq accesses(hits+misses) 493system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses) 494system.cpu.dcache.demand_accesses::cpu.inst 15166387 # number of demand (read+write) accesses 495system.cpu.dcache.demand_accesses::total 15166387 # number of demand (read+write) accesses 496system.cpu.dcache.overall_accesses::cpu.inst 15166387 # number of overall (read+write) accesses 497system.cpu.dcache.overall_accesses::total 15166387 # number of overall (read+write) accesses 498system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133264 # miss rate for ReadReq accesses 499system.cpu.dcache.ReadReq_miss_rate::total 0.133264 # miss rate for ReadReq accesses 500system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093262 # miss rate for WriteReq accesses 501system.cpu.dcache.WriteReq_miss_rate::total 0.093262 # miss rate for WriteReq accesses 502system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086411 # miss rate for LoadLockedReq accesses 503system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086411 # miss rate for LoadLockedReq accesses 504system.cpu.dcache.demand_miss_rate::cpu.inst 0.117043 # miss rate for demand accesses 505system.cpu.dcache.demand_miss_rate::total 0.117043 # miss rate for demand accesses 506system.cpu.dcache.overall_miss_rate::cpu.inst 0.117043 # miss rate for overall accesses 507system.cpu.dcache.overall_miss_rate::total 0.117043 # miss rate for overall accesses 508system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25830.964760 # average ReadReq miss latency 509system.cpu.dcache.ReadReq_avg_miss_latency::total 25830.964760 # average ReadReq miss latency 510system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36089.083233 # average WriteReq miss latency 511system.cpu.dcache.WriteReq_avg_miss_latency::total 36089.083233 # average WriteReq miss latency 512system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13366.118954 # average LoadLockedReq miss latency 513system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.118954 # average LoadLockedReq miss latency 514system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29145.609403 # average overall miss latency 515system.cpu.dcache.demand_avg_miss_latency::total 29145.609403 # average overall miss latency 516system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29145.609403 # average overall miss latency 517system.cpu.dcache.overall_avg_miss_latency::total 29145.609403 # average overall miss latency 518system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 519system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 520system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 521system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 522system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 523system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 524system.cpu.dcache.fast_writes 0 # number of fast writes performed 525system.cpu.dcache.cache_copies 0 # number of cache copies performed 526system.cpu.dcache.writebacks::writebacks 838115 # number of writebacks 527system.cpu.dcache.writebacks::total 838115 # number of writebacks 528system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127210 # number of ReadReq MSHR hits 529system.cpu.dcache.ReadReq_mshr_hits::total 127210 # number of ReadReq MSHR hits 530system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269406 # number of WriteReq MSHR hits 531system.cpu.dcache.WriteReq_mshr_hits::total 269406 # number of WriteReq MSHR hits 532system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits 533system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 534system.cpu.dcache.demand_mshr_hits::cpu.inst 396616 # number of demand (read+write) MSHR hits 535system.cpu.dcache.demand_mshr_hits::total 396616 # number of demand (read+write) MSHR hits 536system.cpu.dcache.overall_mshr_hits::cpu.inst 396616 # number of overall MSHR hits 537system.cpu.dcache.overall_mshr_hits::total 396616 # number of overall MSHR hits 538system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074322 # number of ReadReq MSHR misses 539system.cpu.dcache.ReadReq_mshr_misses::total 1074322 # number of ReadReq MSHR misses 540system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304176 # number of WriteReq MSHR misses 541system.cpu.dcache.WriteReq_mshr_misses::total 304176 # number of WriteReq MSHR misses 542system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17281 # number of LoadLockedReq MSHR misses 543system.cpu.dcache.LoadLockedReq_mshr_misses::total 17281 # number of LoadLockedReq MSHR misses 544system.cpu.dcache.demand_mshr_misses::cpu.inst 1378498 # number of demand (read+write) MSHR misses 545system.cpu.dcache.demand_mshr_misses::total 1378498 # number of demand (read+write) MSHR misses 546system.cpu.dcache.overall_mshr_misses::cpu.inst 1378498 # number of overall MSHR misses 547system.cpu.dcache.overall_mshr_misses::total 1378498 # number of overall MSHR misses 548system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26919627250 # number of ReadReq MSHR miss cycles 549system.cpu.dcache.ReadReq_mshr_miss_latency::total 26919627250 # number of ReadReq MSHR miss cycles 550system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10259801597 # number of WriteReq MSHR miss cycles 551system.cpu.dcache.WriteReq_mshr_miss_latency::total 10259801597 # number of WriteReq MSHR miss cycles 552system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196291500 # number of LoadLockedReq MSHR miss cycles 553system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196291500 # number of LoadLockedReq MSHR miss cycles 554system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179428847 # number of demand (read+write) MSHR miss cycles 555system.cpu.dcache.demand_mshr_miss_latency::total 37179428847 # number of demand (read+write) MSHR miss cycles 556system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179428847 # number of overall MSHR miss cycles 557system.cpu.dcache.overall_mshr_miss_latency::total 37179428847 # number of overall MSHR miss cycles 558system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423887000 # number of ReadReq MSHR uncacheable cycles 559system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423887000 # number of ReadReq MSHR uncacheable cycles 560system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002910000 # number of WriteReq MSHR uncacheable cycles 561system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002910000 # number of WriteReq MSHR uncacheable cycles 562system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426797000 # number of overall MSHR uncacheable cycles 563system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426797000 # number of overall MSHR uncacheable cycles 564system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119155 # mshr miss rate for ReadReq accesses 565system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119155 # mshr miss rate for ReadReq accesses 566system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049458 # mshr miss rate for WriteReq accesses 567system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049458 # mshr miss rate for WriteReq accesses 568system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086396 # mshr miss rate for LoadLockedReq accesses 569system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086396 # mshr miss rate for LoadLockedReq accesses 570system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090892 # mshr miss rate for demand accesses 571system.cpu.dcache.demand_mshr_miss_rate::total 0.090892 # mshr miss rate for demand accesses 572system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090892 # mshr miss rate for overall accesses 573system.cpu.dcache.overall_mshr_miss_rate::total 0.090892 # mshr miss rate for overall accesses 574system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25057.317313 # average ReadReq mshr miss latency 575system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25057.317313 # average ReadReq mshr miss latency 576system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33729.819568 # average WriteReq mshr miss latency 577system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33729.819568 # average WriteReq mshr miss latency 578system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11358.804467 # average LoadLockedReq mshr miss latency 579system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11358.804467 # average LoadLockedReq mshr miss latency 580system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26970.970467 # average overall mshr miss latency 581system.cpu.dcache.demand_avg_mshr_miss_latency::total 26970.970467 # average overall mshr miss latency 582system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26970.970467 # average overall mshr miss latency 583system.cpu.dcache.overall_avg_mshr_miss_latency::total 26970.970467 # average overall mshr miss latency 584system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 585system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 586system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 587system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 588system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 589system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 590system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 591system.cpu.icache.tags.replacements 1458001 # number of replacements 592system.cpu.icache.tags.tagsinuse 509.626489 # Cycle average of tags in use 593system.cpu.icache.tags.total_refs 18970775 # Total number of references to valid blocks. 594system.cpu.icache.tags.sampled_refs 1458512 # Sample count of references to valid blocks. 595system.cpu.icache.tags.avg_refs 13.006938 # Average number of references to valid blocks. 596system.cpu.icache.tags.warmup_cycle 31607473250 # Cycle when the warmup percentage was hit. 597system.cpu.icache.tags.occ_blocks::cpu.inst 509.626489 # Average occupied blocks per requestor 598system.cpu.icache.tags.occ_percent::cpu.inst 0.995364 # Average percentage of cache occupancy 599system.cpu.icache.tags.occ_percent::total 0.995364 # Average percentage of cache occupancy 600system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 601system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 602system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 603system.cpu.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id 604system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 605system.cpu.icache.tags.tag_accesses 21888154 # Number of tag accesses 606system.cpu.icache.tags.data_accesses 21888154 # Number of data accesses 607system.cpu.icache.ReadReq_hits::cpu.inst 18970778 # number of ReadReq hits 608system.cpu.icache.ReadReq_hits::total 18970778 # number of ReadReq hits 609system.cpu.icache.demand_hits::cpu.inst 18970778 # number of demand (read+write) hits 610system.cpu.icache.demand_hits::total 18970778 # number of demand (read+write) hits 611system.cpu.icache.overall_hits::cpu.inst 18970778 # number of overall hits 612system.cpu.icache.overall_hits::total 18970778 # number of overall hits 613system.cpu.icache.ReadReq_misses::cpu.inst 1458688 # number of ReadReq misses 614system.cpu.icache.ReadReq_misses::total 1458688 # number of ReadReq misses 615system.cpu.icache.demand_misses::cpu.inst 1458688 # number of demand (read+write) misses 616system.cpu.icache.demand_misses::total 1458688 # number of demand (read+write) misses 617system.cpu.icache.overall_misses::cpu.inst 1458688 # number of overall misses 618system.cpu.icache.overall_misses::total 1458688 # number of overall misses 619system.cpu.icache.ReadReq_miss_latency::cpu.inst 20029373869 # number of ReadReq miss cycles 620system.cpu.icache.ReadReq_miss_latency::total 20029373869 # number of ReadReq miss cycles 621system.cpu.icache.demand_miss_latency::cpu.inst 20029373869 # number of demand (read+write) miss cycles 622system.cpu.icache.demand_miss_latency::total 20029373869 # number of demand (read+write) miss cycles 623system.cpu.icache.overall_miss_latency::cpu.inst 20029373869 # number of overall miss cycles 624system.cpu.icache.overall_miss_latency::total 20029373869 # number of overall miss cycles 625system.cpu.icache.ReadReq_accesses::cpu.inst 20429466 # number of ReadReq accesses(hits+misses) 626system.cpu.icache.ReadReq_accesses::total 20429466 # number of ReadReq accesses(hits+misses) 627system.cpu.icache.demand_accesses::cpu.inst 20429466 # number of demand (read+write) accesses 628system.cpu.icache.demand_accesses::total 20429466 # number of demand (read+write) accesses 629system.cpu.icache.overall_accesses::cpu.inst 20429466 # number of overall (read+write) accesses 630system.cpu.icache.overall_accesses::total 20429466 # number of overall (read+write) accesses 631system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071401 # miss rate for ReadReq accesses 632system.cpu.icache.ReadReq_miss_rate::total 0.071401 # miss rate for ReadReq accesses 633system.cpu.icache.demand_miss_rate::cpu.inst 0.071401 # miss rate for demand accesses 634system.cpu.icache.demand_miss_rate::total 0.071401 # miss rate for demand accesses 635system.cpu.icache.overall_miss_rate::cpu.inst 0.071401 # miss rate for overall accesses 636system.cpu.icache.overall_miss_rate::total 0.071401 # miss rate for overall accesses 637system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13731.088395 # average ReadReq miss latency 638system.cpu.icache.ReadReq_avg_miss_latency::total 13731.088395 # average ReadReq miss latency 639system.cpu.icache.demand_avg_miss_latency::cpu.inst 13731.088395 # average overall miss latency 640system.cpu.icache.demand_avg_miss_latency::total 13731.088395 # average overall miss latency 641system.cpu.icache.overall_avg_miss_latency::cpu.inst 13731.088395 # average overall miss latency 642system.cpu.icache.overall_avg_miss_latency::total 13731.088395 # average overall miss latency 643system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 644system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 645system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 646system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 647system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 648system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 649system.cpu.icache.fast_writes 0 # number of fast writes performed 650system.cpu.icache.cache_copies 0 # number of cache copies performed 651system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458688 # number of ReadReq MSHR misses 652system.cpu.icache.ReadReq_mshr_misses::total 1458688 # number of ReadReq MSHR misses 653system.cpu.icache.demand_mshr_misses::cpu.inst 1458688 # number of demand (read+write) MSHR misses 654system.cpu.icache.demand_mshr_misses::total 1458688 # number of demand (read+write) MSHR misses 655system.cpu.icache.overall_mshr_misses::cpu.inst 1458688 # number of overall MSHR misses 656system.cpu.icache.overall_mshr_misses::total 1458688 # number of overall MSHR misses 657system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17104729131 # number of ReadReq MSHR miss cycles 658system.cpu.icache.ReadReq_mshr_miss_latency::total 17104729131 # number of ReadReq MSHR miss cycles 659system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17104729131 # number of demand (read+write) MSHR miss cycles 660system.cpu.icache.demand_mshr_miss_latency::total 17104729131 # number of demand (read+write) MSHR miss cycles 661system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17104729131 # number of overall MSHR miss cycles 662system.cpu.icache.overall_mshr_miss_latency::total 17104729131 # number of overall MSHR miss cycles 663system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for ReadReq accesses 664system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071401 # mshr miss rate for ReadReq accesses 665system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for demand accesses 666system.cpu.icache.demand_mshr_miss_rate::total 0.071401 # mshr miss rate for demand accesses 667system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for overall accesses 668system.cpu.icache.overall_mshr_miss_rate::total 0.071401 # mshr miss rate for overall accesses 669system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11726.105330 # average ReadReq mshr miss latency 670system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11726.105330 # average ReadReq mshr miss latency 671system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11726.105330 # average overall mshr miss latency 672system.cpu.icache.demand_avg_mshr_miss_latency::total 11726.105330 # average overall mshr miss latency 673system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11726.105330 # average overall mshr miss latency 674system.cpu.icache.overall_avg_mshr_miss_latency::total 11726.105330 # average overall mshr miss latency 675system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 676system.cpu.l2cache.tags.replacements 339435 # number of replacements 677system.cpu.l2cache.tags.tagsinuse 65326.200893 # Cycle average of tags in use 678system.cpu.l2cache.tags.total_refs 2981535 # Total number of references to valid blocks. 679system.cpu.l2cache.tags.sampled_refs 404597 # Sample count of references to valid blocks. 680system.cpu.l2cache.tags.avg_refs 7.369148 # Average number of references to valid blocks. 681system.cpu.l2cache.tags.warmup_cycle 5873248750 # Cycle when the warmup percentage was hit. 682system.cpu.l2cache.tags.occ_blocks::writebacks 54494.769777 # Average occupied blocks per requestor 683system.cpu.l2cache.tags.occ_blocks::cpu.inst 10831.431116 # Average occupied blocks per requestor 684system.cpu.l2cache.tags.occ_percent::writebacks 0.831524 # Average percentage of cache occupancy 685system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165275 # Average percentage of cache occupancy 686system.cpu.l2cache.tags.occ_percent::total 0.996799 # Average percentage of cache occupancy 687system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 688system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 689system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1458 # Occupied blocks per task id 690system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5147 # Occupied blocks per task id 691system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2791 # Occupied blocks per task id 692system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55536 # Occupied blocks per task id 693system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id 694system.cpu.l2cache.tags.tag_accesses 30249203 # Number of tag accesses 695system.cpu.l2cache.tags.data_accesses 30249203 # Number of data accesses 696system.cpu.l2cache.ReadReq_hits::cpu.inst 2261508 # number of ReadReq hits 697system.cpu.l2cache.ReadReq_hits::total 2261508 # number of ReadReq hits 698system.cpu.l2cache.Writeback_hits::writebacks 838115 # number of Writeback hits 699system.cpu.l2cache.Writeback_hits::total 838115 # number of Writeback hits 700system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits 701system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 702system.cpu.l2cache.ReadExReq_hits::cpu.inst 187530 # number of ReadExReq hits 703system.cpu.l2cache.ReadExReq_hits::total 187530 # number of ReadExReq hits 704system.cpu.l2cache.demand_hits::cpu.inst 2449038 # number of demand (read+write) hits 705system.cpu.l2cache.demand_hits::total 2449038 # number of demand (read+write) hits 706system.cpu.l2cache.overall_hits::cpu.inst 2449038 # number of overall hits 707system.cpu.l2cache.overall_hits::total 2449038 # number of overall hits 708system.cpu.l2cache.ReadReq_misses::cpu.inst 288693 # number of ReadReq misses 709system.cpu.l2cache.ReadReq_misses::total 288693 # number of ReadReq misses 710system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses 711system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses 712system.cpu.l2cache.ReadExReq_misses::cpu.inst 116655 # number of ReadExReq misses 713system.cpu.l2cache.ReadExReq_misses::total 116655 # number of ReadExReq misses 714system.cpu.l2cache.demand_misses::cpu.inst 405348 # number of demand (read+write) misses 715system.cpu.l2cache.demand_misses::total 405348 # number of demand (read+write) misses 716system.cpu.l2cache.overall_misses::cpu.inst 405348 # number of overall misses 717system.cpu.l2cache.overall_misses::total 405348 # number of overall misses 718system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18932535000 # number of ReadReq miss cycles 719system.cpu.l2cache.ReadReq_miss_latency::total 18932535000 # number of ReadReq miss cycles 720system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 214497 # number of UpgradeReq miss cycles 721system.cpu.l2cache.UpgradeReq_miss_latency::total 214497 # number of UpgradeReq miss cycles 722system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8075894612 # number of ReadExReq miss cycles 723system.cpu.l2cache.ReadExReq_miss_latency::total 8075894612 # number of ReadExReq miss cycles 724system.cpu.l2cache.demand_miss_latency::cpu.inst 27008429612 # number of demand (read+write) miss cycles 725system.cpu.l2cache.demand_miss_latency::total 27008429612 # number of demand (read+write) miss cycles 726system.cpu.l2cache.overall_miss_latency::cpu.inst 27008429612 # number of overall miss cycles 727system.cpu.l2cache.overall_miss_latency::total 27008429612 # number of overall miss cycles 728system.cpu.l2cache.ReadReq_accesses::cpu.inst 2550201 # number of ReadReq accesses(hits+misses) 729system.cpu.l2cache.ReadReq_accesses::total 2550201 # number of ReadReq accesses(hits+misses) 730system.cpu.l2cache.Writeback_accesses::writebacks 838115 # number of Writeback accesses(hits+misses) 731system.cpu.l2cache.Writeback_accesses::total 838115 # number of Writeback accesses(hits+misses) 732system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses) 733system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) 734system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304185 # number of ReadExReq accesses(hits+misses) 735system.cpu.l2cache.ReadExReq_accesses::total 304185 # number of ReadExReq accesses(hits+misses) 736system.cpu.l2cache.demand_accesses::cpu.inst 2854386 # number of demand (read+write) accesses 737system.cpu.l2cache.demand_accesses::total 2854386 # number of demand (read+write) accesses 738system.cpu.l2cache.overall_accesses::cpu.inst 2854386 # number of overall (read+write) accesses 739system.cpu.l2cache.overall_accesses::total 2854386 # number of overall (read+write) accesses 740system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113204 # miss rate for ReadReq accesses 741system.cpu.l2cache.ReadReq_miss_rate::total 0.113204 # miss rate for ReadReq accesses 742system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses 743system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses 744system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383500 # miss rate for ReadExReq accesses 745system.cpu.l2cache.ReadExReq_miss_rate::total 0.383500 # miss rate for ReadExReq accesses 746system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142009 # miss rate for demand accesses 747system.cpu.l2cache.demand_miss_rate::total 0.142009 # miss rate for demand accesses 748system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142009 # miss rate for overall accesses 749system.cpu.l2cache.overall_miss_rate::total 0.142009 # miss rate for overall accesses 750system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65580.166474 # average ReadReq miss latency 751system.cpu.l2cache.ReadReq_avg_miss_latency::total 65580.166474 # average ReadReq miss latency 752system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 12617.470588 # average UpgradeReq miss latency 753system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12617.470588 # average UpgradeReq miss latency 754system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69228.876705 # average ReadExReq miss latency 755system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69228.876705 # average ReadExReq miss latency 756system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66630.227883 # average overall miss latency 757system.cpu.l2cache.demand_avg_miss_latency::total 66630.227883 # average overall miss latency 758system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66630.227883 # average overall miss latency 759system.cpu.l2cache.overall_avg_miss_latency::total 66630.227883 # average overall miss latency 760system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 761system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 763system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 764system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 765system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.cpu.l2cache.fast_writes 0 # number of fast writes performed 767system.cpu.l2cache.cache_copies 0 # number of cache copies performed 768system.cpu.l2cache.writebacks::writebacks 76635 # number of writebacks 769system.cpu.l2cache.writebacks::total 76635 # number of writebacks 770system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288693 # number of ReadReq MSHR misses 771system.cpu.l2cache.ReadReq_mshr_misses::total 288693 # number of ReadReq MSHR misses 772system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses 773system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses 774system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116655 # number of ReadExReq MSHR misses 775system.cpu.l2cache.ReadExReq_mshr_misses::total 116655 # number of ReadExReq MSHR misses 776system.cpu.l2cache.demand_mshr_misses::cpu.inst 405348 # number of demand (read+write) MSHR misses 777system.cpu.l2cache.demand_mshr_misses::total 405348 # number of demand (read+write) MSHR misses 778system.cpu.l2cache.overall_mshr_misses::cpu.inst 405348 # number of overall MSHR misses 779system.cpu.l2cache.overall_mshr_misses::total 405348 # number of overall MSHR misses 780system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15323296500 # number of ReadReq MSHR miss cycles 781system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15323296500 # number of ReadReq MSHR miss cycles 782system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 271014 # number of UpgradeReq MSHR miss cycles 783system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271014 # number of UpgradeReq MSHR miss cycles 784system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6608324888 # number of ReadExReq MSHR miss cycles 785system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6608324888 # number of ReadExReq MSHR miss cycles 786system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21931621388 # number of demand (read+write) MSHR miss cycles 787system.cpu.l2cache.demand_mshr_miss_latency::total 21931621388 # number of demand (read+write) MSHR miss cycles 788system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21931621388 # number of overall MSHR miss cycles 789system.cpu.l2cache.overall_mshr_miss_latency::total 21931621388 # number of overall MSHR miss cycles 790system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333779000 # number of ReadReq MSHR uncacheable cycles 791system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333779000 # number of ReadReq MSHR uncacheable cycles 792system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887481500 # number of WriteReq MSHR uncacheable cycles 793system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887481500 # number of WriteReq MSHR uncacheable cycles 794system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221260500 # number of overall MSHR uncacheable cycles 795system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221260500 # number of overall MSHR uncacheable cycles 796system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113204 # mshr miss rate for ReadReq accesses 797system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113204 # mshr miss rate for ReadReq accesses 798system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses 799system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses 800system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383500 # mshr miss rate for ReadExReq accesses 801system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383500 # mshr miss rate for ReadExReq accesses 802system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for demand accesses 803system.cpu.l2cache.demand_mshr_miss_rate::total 0.142009 # mshr miss rate for demand accesses 804system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for overall accesses 805system.cpu.l2cache.overall_mshr_miss_rate::total 0.142009 # mshr miss rate for overall accesses 806system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53078.171275 # average ReadReq mshr miss latency 807system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53078.171275 # average ReadReq mshr miss latency 808system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15942 # average UpgradeReq mshr miss latency 809system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency 810system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56648.449599 # average ReadExReq mshr miss latency 811system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56648.449599 # average ReadExReq mshr miss latency 812system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54105.660785 # average overall mshr miss latency 813system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54105.660785 # average overall mshr miss latency 814system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54105.660785 # average overall mshr miss latency 815system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54105.660785 # average overall mshr miss latency 816system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 817system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 818system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 819system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 820system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 821system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 822system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 823system.cpu.toL2Bus.trans_dist::ReadReq 2557364 # Transaction distribution 824system.cpu.toL2Bus.trans_dist::ReadResp 2557331 # Transaction distribution 825system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution 826system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution 827system.cpu.toL2Bus.trans_dist::Writeback 838115 # Transaction distribution 828system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 829system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution 830system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution 831system.cpu.toL2Bus.trans_dist::ReadExReq 304185 # Transaction distribution 832system.cpu.toL2Bus.trans_dist::ReadExResp 304185 # Transaction distribution 833system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution 834system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917316 # Packet count per connected master and slave (bytes) 835system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662927 # Packet count per connected master and slave (bytes) 836system.cpu.toL2Bus.pkt_count::total 6580243 # Packet count per connected master and slave (bytes) 837system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352192 # Cumulative packet size per connected master and slave (bytes) 838system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143021148 # Cumulative packet size per connected master and slave (bytes) 839system.cpu.toL2Bus.pkt_size::total 236373340 # Cumulative packet size per connected master and slave (bytes) 840system.cpu.toL2Bus.snoops 41941 # Total snoops (count) 841system.cpu.toL2Bus.snoop_fanout::samples 3734307 # Request fanout histogram 842system.cpu.toL2Bus.snoop_fanout::mean 1.011173 # Request fanout histogram 843system.cpu.toL2Bus.snoop_fanout::stdev 0.105112 # Request fanout histogram 844system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 845system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 846system.cpu.toL2Bus.snoop_fanout::1 3692582 98.88% 98.88% # Request fanout histogram 847system.cpu.toL2Bus.snoop_fanout::2 41725 1.12% 100.00% # Request fanout histogram 848system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 849system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 850system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 851system.cpu.toL2Bus.snoop_fanout::total 3734307 # Request fanout histogram 852system.cpu.toL2Bus.reqLayer0.occupancy 2697490998 # Layer occupancy (ticks) 853system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 854system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 855system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 856system.cpu.toL2Bus.respLayer0.occupancy 2191666369 # Layer occupancy (ticks) 857system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 858system.cpu.toL2Bus.respLayer1.occupancy 2194528153 # Layer occupancy (ticks) 859system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 860system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 861system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 862system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 863system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 864system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 865system.disk0.dma_write_txs 395 # Number of DMA write transactions. 866system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 867system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 868system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 869system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 870system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 871system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 621system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 622system.iobus.trans_dist::ReadResp 7103 # Transaction distribution | 872system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 873system.iobus.trans_dist::ReadResp 7103 # Transaction distribution |
| 623system.iobus.trans_dist::WriteReq 51170 # Transaction distribution 624system.iobus.trans_dist::WriteResp 51170 # Transaction distribution 625system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes) | 874system.iobus.trans_dist::WriteReq 51171 # Transaction distribution 875system.iobus.trans_dist::WriteResp 9619 # Transaction distribution 876system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 877system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes) |
| 626system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 627system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 628system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 629system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 630system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 631system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 632system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 633system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 634system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 635system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 636system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 878system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 879system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 880system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 881system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 882system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 883system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 884system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 885system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 886system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 887system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 888system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 637system.iobus.pkt_count_system.bridge.master::total 33096 # Packet count per connected master and slave (bytes) | 889system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes) |
| 638system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 639system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) | 890system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 891system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) |
| 640system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes) 641system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes) | 892system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes) 893system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes) |
| 642system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 643system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 644system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 645system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 646system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 647system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 648system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 649system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 650system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 651system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 652system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 894system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 895system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 896system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 897system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 898system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 899system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 900system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 901system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 902system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 903system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 904system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 653system.iobus.pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes) | 905system.iobus.pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes) |
| 654system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 655system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) | 906system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 907system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) |
| 656system.iobus.pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes) 657system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks) | 908system.iobus.pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes) 909system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks) |
| 658system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 659system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 660system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 662system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 663system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 664system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 665system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 671system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 672system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 673system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 674system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 675system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 676system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 677system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 678system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 910system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 911system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 912system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 913system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 914system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 915system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 916system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 917system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 923system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 924system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 925system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 926system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 927system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 928system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 929system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 930system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 679system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks) | 931system.iobus.reqLayer29.occupancy 406196790 # Layer occupancy (ticks) |
| 680system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 681system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 682system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | 932system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 933system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 934system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) |
| 683system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks) | 935system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) |
| 684system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 936system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 685system.iobus.respLayer1.occupancy 42013751 # Layer occupancy (ticks) | 937system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) |
| 686system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 938system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 687system.cpu.icache.tags.replacements 1457910 # number of replacements 688system.cpu.icache.tags.tagsinuse 509.626980 # Cycle average of tags in use 689system.cpu.icache.tags.total_refs 18940924 # Total number of references to valid blocks. 690system.cpu.icache.tags.sampled_refs 1458421 # Sample count of references to valid blocks. 691system.cpu.icache.tags.avg_refs 12.987281 # Average number of references to valid blocks. 692system.cpu.icache.tags.warmup_cycle 31560714250 # Cycle when the warmup percentage was hit. 693system.cpu.icache.tags.occ_blocks::cpu.inst 509.626980 # Average occupied blocks per requestor 694system.cpu.icache.tags.occ_percent::cpu.inst 0.995365 # Average percentage of cache occupancy 695system.cpu.icache.tags.occ_percent::total 0.995365 # Average percentage of cache occupancy 696system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 697system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 698system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 699system.cpu.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id 700system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 701system.cpu.icache.tags.tag_accesses 21858119 # Number of tag accesses 702system.cpu.icache.tags.data_accesses 21858119 # Number of data accesses 703system.cpu.icache.ReadReq_hits::cpu.inst 18940927 # number of ReadReq hits 704system.cpu.icache.ReadReq_hits::total 18940927 # number of ReadReq hits 705system.cpu.icache.demand_hits::cpu.inst 18940927 # number of demand (read+write) hits 706system.cpu.icache.demand_hits::total 18940927 # number of demand (read+write) hits 707system.cpu.icache.overall_hits::cpu.inst 18940927 # number of overall hits 708system.cpu.icache.overall_hits::total 18940927 # number of overall hits 709system.cpu.icache.ReadReq_misses::cpu.inst 1458596 # number of ReadReq misses 710system.cpu.icache.ReadReq_misses::total 1458596 # number of ReadReq misses 711system.cpu.icache.demand_misses::cpu.inst 1458596 # number of demand (read+write) misses 712system.cpu.icache.demand_misses::total 1458596 # number of demand (read+write) misses 713system.cpu.icache.overall_misses::cpu.inst 1458596 # number of overall misses 714system.cpu.icache.overall_misses::total 1458596 # number of overall misses 715system.cpu.icache.ReadReq_miss_latency::cpu.inst 20022164568 # number of ReadReq miss cycles 716system.cpu.icache.ReadReq_miss_latency::total 20022164568 # number of ReadReq miss cycles 717system.cpu.icache.demand_miss_latency::cpu.inst 20022164568 # number of demand (read+write) miss cycles 718system.cpu.icache.demand_miss_latency::total 20022164568 # number of demand (read+write) miss cycles 719system.cpu.icache.overall_miss_latency::cpu.inst 20022164568 # number of overall miss cycles 720system.cpu.icache.overall_miss_latency::total 20022164568 # number of overall miss cycles 721system.cpu.icache.ReadReq_accesses::cpu.inst 20399523 # number of ReadReq accesses(hits+misses) 722system.cpu.icache.ReadReq_accesses::total 20399523 # number of ReadReq accesses(hits+misses) 723system.cpu.icache.demand_accesses::cpu.inst 20399523 # number of demand (read+write) accesses 724system.cpu.icache.demand_accesses::total 20399523 # number of demand (read+write) accesses 725system.cpu.icache.overall_accesses::cpu.inst 20399523 # number of overall (read+write) accesses 726system.cpu.icache.overall_accesses::total 20399523 # number of overall (read+write) accesses 727system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071501 # miss rate for ReadReq accesses 728system.cpu.icache.ReadReq_miss_rate::total 0.071501 # miss rate for ReadReq accesses 729system.cpu.icache.demand_miss_rate::cpu.inst 0.071501 # miss rate for demand accesses 730system.cpu.icache.demand_miss_rate::total 0.071501 # miss rate for demand accesses 731system.cpu.icache.overall_miss_rate::cpu.inst 0.071501 # miss rate for overall accesses 732system.cpu.icache.overall_miss_rate::total 0.071501 # miss rate for overall accesses 733system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.011844 # average ReadReq miss latency 734system.cpu.icache.ReadReq_avg_miss_latency::total 13727.011844 # average ReadReq miss latency 735system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency 736system.cpu.icache.demand_avg_miss_latency::total 13727.011844 # average overall miss latency 737system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency 738system.cpu.icache.overall_avg_miss_latency::total 13727.011844 # average overall miss latency 739system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 740system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 741system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 742system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 743system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 744system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 745system.cpu.icache.fast_writes 0 # number of fast writes performed 746system.cpu.icache.cache_copies 0 # number of cache copies performed 747system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458596 # number of ReadReq MSHR misses 748system.cpu.icache.ReadReq_mshr_misses::total 1458596 # number of ReadReq MSHR misses 749system.cpu.icache.demand_mshr_misses::cpu.inst 1458596 # number of demand (read+write) MSHR misses 750system.cpu.icache.demand_mshr_misses::total 1458596 # number of demand (read+write) MSHR misses 751system.cpu.icache.overall_mshr_misses::cpu.inst 1458596 # number of overall MSHR misses 752system.cpu.icache.overall_mshr_misses::total 1458596 # number of overall MSHR misses 753system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097663432 # number of ReadReq MSHR miss cycles 754system.cpu.icache.ReadReq_mshr_miss_latency::total 17097663432 # number of ReadReq MSHR miss cycles 755system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097663432 # number of demand (read+write) MSHR miss cycles 756system.cpu.icache.demand_mshr_miss_latency::total 17097663432 # number of demand (read+write) MSHR miss cycles 757system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097663432 # number of overall MSHR miss cycles 758system.cpu.icache.overall_mshr_miss_latency::total 17097663432 # number of overall MSHR miss cycles 759system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for ReadReq accesses 760system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071501 # mshr miss rate for ReadReq accesses 761system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for demand accesses 762system.cpu.icache.demand_mshr_miss_rate::total 0.071501 # mshr miss rate for demand accesses 763system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for overall accesses 764system.cpu.icache.overall_mshr_miss_rate::total 0.071501 # mshr miss rate for overall accesses 765system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.000768 # average ReadReq mshr miss latency 766system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.000768 # average ReadReq mshr miss latency 767system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency 768system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency 769system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency 770system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency 771system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 772system.cpu.toL2Bus.trans_dist::ReadReq 2557139 # Transaction distribution 773system.cpu.toL2Bus.trans_dist::ReadResp 2557106 # Transaction distribution 774system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution 775system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution 776system.cpu.toL2Bus.trans_dist::Writeback 838111 # Transaction distribution 777system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution 778system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution 779system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution 780system.cpu.toL2Bus.trans_dist::ReadExReq 304253 # Transaction distribution 781system.cpu.toL2Bus.trans_dist::ReadExResp 304253 # Transaction distribution 782system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution 783system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917133 # Packet count per connected master and slave (bytes) 784system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662791 # Packet count per connected master and slave (bytes) 785system.cpu.toL2Bus.pkt_count::total 6579924 # Packet count per connected master and slave (bytes) 786system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93346368 # Cumulative packet size per connected master and slave (bytes) 787system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143016724 # Cumulative packet size per connected master and slave (bytes) 788system.cpu.toL2Bus.pkt_size::total 236363092 # Cumulative packet size per connected master and slave (bytes) 789system.cpu.toL2Bus.snoops 41947 # Total snoops (count) 790system.cpu.toL2Bus.snoop_fanout::samples 3734153 # Request fanout histogram 791system.cpu.toL2Bus.snoop_fanout::mean 1.011176 # Request fanout histogram 792system.cpu.toL2Bus.snoop_fanout::stdev 0.105123 # Request fanout histogram 793system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 794system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 795system.cpu.toL2Bus.snoop_fanout::1 3692421 98.88% 98.88% # Request fanout histogram 796system.cpu.toL2Bus.snoop_fanout::2 41732 1.12% 100.00% # Request fanout histogram 797system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 798system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 799system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 800system.cpu.toL2Bus.snoop_fanout::total 3734153 # Request fanout histogram 801system.cpu.toL2Bus.reqLayer0.occupancy 2697404999 # Layer occupancy (ticks) 802system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 803system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 804system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 805system.cpu.toL2Bus.respLayer0.occupancy 2191548568 # Layer occupancy (ticks) 806system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 807system.cpu.toL2Bus.respLayer1.occupancy 2194491404 # Layer occupancy (ticks) 808system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 809system.cpu.l2cache.tags.replacements 339424 # number of replacements 810system.cpu.l2cache.tags.tagsinuse 65327.181695 # Cycle average of tags in use 811system.cpu.l2cache.tags.total_refs 2981337 # Total number of references to valid blocks. 812system.cpu.l2cache.tags.sampled_refs 404586 # Sample count of references to valid blocks. 813system.cpu.l2cache.tags.avg_refs 7.368859 # Average number of references to valid blocks. 814system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit. 815system.cpu.l2cache.tags.occ_blocks::writebacks 54492.967363 # Average occupied blocks per requestor 816system.cpu.l2cache.tags.occ_blocks::cpu.inst 10834.214332 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_percent::writebacks 0.831497 # Average percentage of cache occupancy 818system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165317 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_percent::total 0.996814 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 821system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 822system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1457 # Occupied blocks per task id 823system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5166 # Occupied blocks per task id 824system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2781 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id 826system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id 827system.cpu.l2cache.tags.tag_accesses 30247978 # Number of tag accesses 828system.cpu.l2cache.tags.data_accesses 30247978 # Number of data accesses 829system.cpu.l2cache.ReadReq_hits::cpu.inst 2261320 # number of ReadReq hits 830system.cpu.l2cache.ReadReq_hits::total 2261320 # number of ReadReq hits 831system.cpu.l2cache.Writeback_hits::writebacks 838111 # number of Writeback hits 832system.cpu.l2cache.Writeback_hits::total 838111 # number of Writeback hits 833system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits 834system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 835system.cpu.l2cache.ReadExReq_hits::cpu.inst 187575 # number of ReadExReq hits 836system.cpu.l2cache.ReadExReq_hits::total 187575 # number of ReadExReq hits 837system.cpu.l2cache.demand_hits::cpu.inst 2448895 # number of demand (read+write) hits 838system.cpu.l2cache.demand_hits::total 2448895 # number of demand (read+write) hits 839system.cpu.l2cache.overall_hits::cpu.inst 2448895 # number of overall hits 840system.cpu.l2cache.overall_hits::total 2448895 # number of overall hits 841system.cpu.l2cache.ReadReq_misses::cpu.inst 288657 # number of ReadReq misses 842system.cpu.l2cache.ReadReq_misses::total 288657 # number of ReadReq misses 843system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses 844system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses 845system.cpu.l2cache.ReadExReq_misses::cpu.inst 116678 # number of ReadExReq misses 846system.cpu.l2cache.ReadExReq_misses::total 116678 # number of ReadExReq misses 847system.cpu.l2cache.demand_misses::cpu.inst 405335 # number of demand (read+write) misses 848system.cpu.l2cache.demand_misses::total 405335 # number of demand (read+write) misses 849system.cpu.l2cache.overall_misses::cpu.inst 405335 # number of overall misses 850system.cpu.l2cache.overall_misses::total 405335 # number of overall misses 851system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18918279000 # number of ReadReq miss cycles 852system.cpu.l2cache.ReadReq_miss_latency::total 18918279000 # number of ReadReq miss cycles 853system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 115495 # number of UpgradeReq miss cycles 854system.cpu.l2cache.UpgradeReq_miss_latency::total 115495 # number of UpgradeReq miss cycles 855system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8105432113 # number of ReadExReq miss cycles 856system.cpu.l2cache.ReadExReq_miss_latency::total 8105432113 # number of ReadExReq miss cycles 857system.cpu.l2cache.demand_miss_latency::cpu.inst 27023711113 # number of demand (read+write) miss cycles 858system.cpu.l2cache.demand_miss_latency::total 27023711113 # number of demand (read+write) miss cycles 859system.cpu.l2cache.overall_miss_latency::cpu.inst 27023711113 # number of overall miss cycles 860system.cpu.l2cache.overall_miss_latency::total 27023711113 # number of overall miss cycles 861system.cpu.l2cache.ReadReq_accesses::cpu.inst 2549977 # number of ReadReq accesses(hits+misses) 862system.cpu.l2cache.ReadReq_accesses::total 2549977 # number of ReadReq accesses(hits+misses) 863system.cpu.l2cache.Writeback_accesses::writebacks 838111 # number of Writeback accesses(hits+misses) 864system.cpu.l2cache.Writeback_accesses::total 838111 # number of Writeback accesses(hits+misses) 865system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses) 866system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) 867system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304253 # number of ReadExReq accesses(hits+misses) 868system.cpu.l2cache.ReadExReq_accesses::total 304253 # number of ReadExReq accesses(hits+misses) 869system.cpu.l2cache.demand_accesses::cpu.inst 2854230 # number of demand (read+write) accesses 870system.cpu.l2cache.demand_accesses::total 2854230 # number of demand (read+write) accesses 871system.cpu.l2cache.overall_accesses::cpu.inst 2854230 # number of overall (read+write) accesses 872system.cpu.l2cache.overall_accesses::total 2854230 # number of overall (read+write) accesses 873system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113200 # miss rate for ReadReq accesses 874system.cpu.l2cache.ReadReq_miss_rate::total 0.113200 # miss rate for ReadReq accesses 875system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses 876system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses 877system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383490 # miss rate for ReadExReq accesses 878system.cpu.l2cache.ReadExReq_miss_rate::total 0.383490 # miss rate for ReadExReq accesses 879system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142012 # miss rate for demand accesses 880system.cpu.l2cache.demand_miss_rate::total 0.142012 # miss rate for demand accesses 881system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142012 # miss rate for overall accesses 882system.cpu.l2cache.overall_miss_rate::total 0.142012 # miss rate for overall accesses 883system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65538.958002 # average ReadReq miss latency 884system.cpu.l2cache.ReadReq_avg_miss_latency::total 65538.958002 # average ReadReq miss latency 885system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 6793.823529 # average UpgradeReq miss latency 886system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6793.823529 # average UpgradeReq miss latency 887system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69468.384040 # average ReadExReq miss latency 888system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69468.384040 # average ReadExReq miss latency 889system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency 890system.cpu.l2cache.demand_avg_miss_latency::total 66670.065780 # average overall miss latency 891system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency 892system.cpu.l2cache.overall_avg_miss_latency::total 66670.065780 # average overall miss latency 893system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 894system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 895system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 896system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 897system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 898system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 899system.cpu.l2cache.fast_writes 0 # number of fast writes performed 900system.cpu.l2cache.cache_copies 0 # number of cache copies performed 901system.cpu.l2cache.writebacks::writebacks 76624 # number of writebacks 902system.cpu.l2cache.writebacks::total 76624 # number of writebacks 903system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288657 # number of ReadReq MSHR misses 904system.cpu.l2cache.ReadReq_mshr_misses::total 288657 # number of ReadReq MSHR misses 905system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses 906system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses 907system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116678 # number of ReadExReq MSHR misses 908system.cpu.l2cache.ReadExReq_mshr_misses::total 116678 # number of ReadExReq MSHR misses 909system.cpu.l2cache.demand_mshr_misses::cpu.inst 405335 # number of demand (read+write) MSHR misses 910system.cpu.l2cache.demand_mshr_misses::total 405335 # number of demand (read+write) MSHR misses 911system.cpu.l2cache.overall_mshr_misses::cpu.inst 405335 # number of overall MSHR misses 912system.cpu.l2cache.overall_mshr_misses::total 405335 # number of overall MSHR misses 913system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15309425000 # number of ReadReq MSHR miss cycles 914system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15309425000 # number of ReadReq MSHR miss cycles 915system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 170516 # number of UpgradeReq MSHR miss cycles 916system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 170516 # number of UpgradeReq MSHR miss cycles 917system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6604759387 # number of ReadExReq MSHR miss cycles 918system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6604759387 # number of ReadExReq MSHR miss cycles 919system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21914184387 # number of demand (read+write) MSHR miss cycles 920system.cpu.l2cache.demand_mshr_miss_latency::total 21914184387 # number of demand (read+write) MSHR miss cycles 921system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21914184387 # number of overall MSHR miss cycles 922system.cpu.l2cache.overall_mshr_miss_latency::total 21914184387 # number of overall MSHR miss cycles 923system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333304000 # number of ReadReq MSHR uncacheable cycles 924system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333304000 # number of ReadReq MSHR uncacheable cycles 925system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1888377500 # number of WriteReq MSHR uncacheable cycles 926system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1888377500 # number of WriteReq MSHR uncacheable cycles 927system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221681500 # number of overall MSHR uncacheable cycles 928system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221681500 # number of overall MSHR uncacheable cycles 929system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113200 # mshr miss rate for ReadReq accesses 930system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113200 # mshr miss rate for ReadReq accesses 931system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses 932system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses 933system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383490 # mshr miss rate for ReadExReq accesses 934system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383490 # mshr miss rate for ReadExReq accesses 935system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for demand accesses 936system.cpu.l2cache.demand_mshr_miss_rate::total 0.142012 # mshr miss rate for demand accesses 937system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for overall accesses 938system.cpu.l2cache.overall_mshr_miss_rate::total 0.142012 # mshr miss rate for overall accesses 939system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53036.735641 # average ReadReq mshr miss latency 940system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53036.735641 # average ReadReq mshr miss latency 941system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10030.352941 # average UpgradeReq mshr miss latency 942system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.352941 # average UpgradeReq mshr miss latency 943system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56606.724378 # average ReadExReq mshr miss latency 944system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56606.724378 # average ReadExReq mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency 946system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency 947system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency 948system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency 949system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 950system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 951system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 952system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 953system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 954system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 955system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 956system.cpu.dcache.tags.replacements 1395163 # number of replacements 957system.cpu.dcache.tags.tagsinuse 511.982303 # Cycle average of tags in use 958system.cpu.dcache.tags.total_refs 13764370 # Total number of references to valid blocks. 959system.cpu.dcache.tags.sampled_refs 1395675 # Sample count of references to valid blocks. 960system.cpu.dcache.tags.avg_refs 9.862160 # Average number of references to valid blocks. 961system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit. 962system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982303 # Average occupied blocks per requestor 963system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy 964system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy 965system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 966system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 967system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 968system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 969system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 970system.cpu.dcache.tags.tag_accesses 63622669 # Number of tag accesses 971system.cpu.dcache.tags.data_accesses 63622669 # Number of data accesses 972system.cpu.dcache.ReadReq_hits::cpu.inst 7806418 # number of ReadReq hits 973system.cpu.dcache.ReadReq_hits::total 7806418 # number of ReadReq hits 974system.cpu.dcache.WriteReq_hits::cpu.inst 5576177 # number of WriteReq hits 975system.cpu.dcache.WriteReq_hits::total 5576177 # number of WriteReq hits 976system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182756 # number of LoadLockedReq hits 977system.cpu.dcache.LoadLockedReq_hits::total 182756 # number of LoadLockedReq hits 978system.cpu.dcache.StoreCondReq_hits::cpu.inst 198986 # number of StoreCondReq hits 979system.cpu.dcache.StoreCondReq_hits::total 198986 # number of StoreCondReq hits 980system.cpu.dcache.demand_hits::cpu.inst 13382595 # number of demand (read+write) hits 981system.cpu.dcache.demand_hits::total 13382595 # number of demand (read+write) hits 982system.cpu.dcache.overall_hits::cpu.inst 13382595 # number of overall hits 983system.cpu.dcache.overall_hits::total 13382595 # number of overall hits 984system.cpu.dcache.ReadReq_misses::cpu.inst 1201460 # number of ReadReq misses 985system.cpu.dcache.ReadReq_misses::total 1201460 # number of ReadReq misses 986system.cpu.dcache.WriteReq_misses::cpu.inst 573699 # number of WriteReq misses 987system.cpu.dcache.WriteReq_misses::total 573699 # number of WriteReq misses 988system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17252 # number of LoadLockedReq misses 989system.cpu.dcache.LoadLockedReq_misses::total 17252 # number of LoadLockedReq misses 990system.cpu.dcache.demand_misses::cpu.inst 1775159 # number of demand (read+write) misses 991system.cpu.dcache.demand_misses::total 1775159 # number of demand (read+write) misses 992system.cpu.dcache.overall_misses::cpu.inst 1775159 # number of overall misses 993system.cpu.dcache.overall_misses::total 1775159 # number of overall misses 994system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31026314750 # number of ReadReq miss cycles 995system.cpu.dcache.ReadReq_miss_latency::total 31026314750 # number of ReadReq miss cycles 996system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20775588791 # number of WriteReq miss cycles 997system.cpu.dcache.WriteReq_miss_latency::total 20775588791 # number of WriteReq miss cycles 998system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 230892000 # number of LoadLockedReq miss cycles 999system.cpu.dcache.LoadLockedReq_miss_latency::total 230892000 # number of LoadLockedReq miss cycles 1000system.cpu.dcache.demand_miss_latency::cpu.inst 51801903541 # number of demand (read+write) miss cycles 1001system.cpu.dcache.demand_miss_latency::total 51801903541 # number of demand (read+write) miss cycles 1002system.cpu.dcache.overall_miss_latency::cpu.inst 51801903541 # number of overall miss cycles 1003system.cpu.dcache.overall_miss_latency::total 51801903541 # number of overall miss cycles 1004system.cpu.dcache.ReadReq_accesses::cpu.inst 9007878 # number of ReadReq accesses(hits+misses) 1005system.cpu.dcache.ReadReq_accesses::total 9007878 # number of ReadReq accesses(hits+misses) 1006system.cpu.dcache.WriteReq_accesses::cpu.inst 6149876 # number of WriteReq accesses(hits+misses) 1007system.cpu.dcache.WriteReq_accesses::total 6149876 # number of WriteReq accesses(hits+misses) 1008system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200008 # number of LoadLockedReq accesses(hits+misses) 1009system.cpu.dcache.LoadLockedReq_accesses::total 200008 # number of LoadLockedReq accesses(hits+misses) 1010system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198986 # number of StoreCondReq accesses(hits+misses) 1011system.cpu.dcache.StoreCondReq_accesses::total 198986 # number of StoreCondReq accesses(hits+misses) 1012system.cpu.dcache.demand_accesses::cpu.inst 15157754 # number of demand (read+write) accesses 1013system.cpu.dcache.demand_accesses::total 15157754 # number of demand (read+write) accesses 1014system.cpu.dcache.overall_accesses::cpu.inst 15157754 # number of overall (read+write) accesses 1015system.cpu.dcache.overall_accesses::total 15157754 # number of overall (read+write) accesses 1016system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133379 # miss rate for ReadReq accesses 1017system.cpu.dcache.ReadReq_miss_rate::total 0.133379 # miss rate for ReadReq accesses 1018system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093286 # miss rate for WriteReq accesses 1019system.cpu.dcache.WriteReq_miss_rate::total 0.093286 # miss rate for WriteReq accesses 1020system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086257 # miss rate for LoadLockedReq accesses 1021system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086257 # miss rate for LoadLockedReq accesses 1022system.cpu.dcache.demand_miss_rate::cpu.inst 0.117112 # miss rate for demand accesses 1023system.cpu.dcache.demand_miss_rate::total 0.117112 # miss rate for demand accesses 1024system.cpu.dcache.overall_miss_rate::cpu.inst 0.117112 # miss rate for overall accesses 1025system.cpu.dcache.overall_miss_rate::total 0.117112 # miss rate for overall accesses 1026system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25823.843282 # average ReadReq miss latency 1027system.cpu.dcache.ReadReq_avg_miss_latency::total 25823.843282 # average ReadReq miss latency 1028system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36213.395511 # average WriteReq miss latency 1029system.cpu.dcache.WriteReq_avg_miss_latency::total 36213.395511 # average WriteReq miss latency 1030system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13383.491769 # average LoadLockedReq miss latency 1031system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13383.491769 # average LoadLockedReq miss latency 1032system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency 1033system.cpu.dcache.demand_avg_miss_latency::total 29181.556999 # average overall miss latency 1034system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency 1035system.cpu.dcache.overall_avg_miss_latency::total 29181.556999 # average overall miss latency 1036system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1037system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1038system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1039system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1040system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1041system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1042system.cpu.dcache.fast_writes 0 # number of fast writes performed 1043system.cpu.dcache.cache_copies 0 # number of cache copies performed 1044system.cpu.dcache.writebacks::writebacks 838111 # number of writebacks 1045system.cpu.dcache.writebacks::total 838111 # number of writebacks 1046system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127232 # number of ReadReq MSHR hits 1047system.cpu.dcache.ReadReq_mshr_hits::total 127232 # number of ReadReq MSHR hits 1048system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269462 # number of WriteReq MSHR hits 1049system.cpu.dcache.WriteReq_mshr_hits::total 269462 # number of WriteReq MSHR hits 1050system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits 1051system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 1052system.cpu.dcache.demand_mshr_hits::cpu.inst 396694 # number of demand (read+write) MSHR hits 1053system.cpu.dcache.demand_mshr_hits::total 396694 # number of demand (read+write) MSHR hits 1054system.cpu.dcache.overall_mshr_hits::cpu.inst 396694 # number of overall MSHR hits 1055system.cpu.dcache.overall_mshr_hits::total 396694 # number of overall MSHR hits 1056system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074228 # number of ReadReq MSHR misses 1057system.cpu.dcache.ReadReq_mshr_misses::total 1074228 # number of ReadReq MSHR misses 1058system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304237 # number of WriteReq MSHR misses 1059system.cpu.dcache.WriteReq_mshr_misses::total 304237 # number of WriteReq MSHR misses 1060system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17249 # number of LoadLockedReq MSHR misses 1061system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses 1062system.cpu.dcache.demand_mshr_misses::cpu.inst 1378465 # number of demand (read+write) MSHR misses 1063system.cpu.dcache.demand_mshr_misses::total 1378465 # number of demand (read+write) MSHR misses 1064system.cpu.dcache.overall_mshr_misses::cpu.inst 1378465 # number of overall MSHR misses 1065system.cpu.dcache.overall_mshr_misses::total 1378465 # number of overall MSHR misses 1066system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26911701750 # number of ReadReq MSHR miss cycles 1067system.cpu.dcache.ReadReq_mshr_miss_latency::total 26911701750 # number of ReadReq MSHR miss cycles 1068system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10289625346 # number of WriteReq MSHR miss cycles 1069system.cpu.dcache.WriteReq_mshr_miss_latency::total 10289625346 # number of WriteReq MSHR miss cycles 1070system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196226500 # number of LoadLockedReq MSHR miss cycles 1071system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196226500 # number of LoadLockedReq MSHR miss cycles 1072system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37201327096 # number of demand (read+write) MSHR miss cycles 1073system.cpu.dcache.demand_mshr_miss_latency::total 37201327096 # number of demand (read+write) MSHR miss cycles 1074system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37201327096 # number of overall MSHR miss cycles 1075system.cpu.dcache.overall_mshr_miss_latency::total 37201327096 # number of overall MSHR miss cycles 1076system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423395500 # number of ReadReq MSHR uncacheable cycles 1077system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423395500 # number of ReadReq MSHR uncacheable cycles 1078system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2003794000 # number of WriteReq MSHR uncacheable cycles 1079system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2003794000 # number of WriteReq MSHR uncacheable cycles 1080system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3427189500 # number of overall MSHR uncacheable cycles 1081system.cpu.dcache.overall_mshr_uncacheable_latency::total 3427189500 # number of overall MSHR uncacheable cycles 1082system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119254 # mshr miss rate for ReadReq accesses 1083system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119254 # mshr miss rate for ReadReq accesses 1084system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049470 # mshr miss rate for WriteReq accesses 1085system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses 1086system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086242 # mshr miss rate for LoadLockedReq accesses 1087system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086242 # mshr miss rate for LoadLockedReq accesses 1088system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for demand accesses 1089system.cpu.dcache.demand_mshr_miss_rate::total 0.090941 # mshr miss rate for demand accesses 1090system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for overall accesses 1091system.cpu.dcache.overall_mshr_miss_rate::total 0.090941 # mshr miss rate for overall accesses 1092system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25052.132089 # average ReadReq mshr miss latency 1093system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25052.132089 # average ReadReq mshr miss latency 1094system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33821.084700 # average WriteReq mshr miss latency 1095system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33821.084700 # average WriteReq mshr miss latency 1096system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11376.108760 # average LoadLockedReq mshr miss latency 1097system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.108760 # average LoadLockedReq mshr miss latency 1098system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency 1099system.cpu.dcache.demand_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency 1100system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency 1101system.cpu.dcache.overall_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency 1102system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1103system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1104system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1105system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1106system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1107system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1108system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 939system.iocache.tags.replacements 41685 # number of replacements 940system.iocache.tags.tagsinuse 1.296059 # Cycle average of tags in use 941system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 942system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 943system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 944system.iocache.tags.warmup_cycle 1728026020000 # Cycle when the warmup percentage was hit. 945system.iocache.tags.occ_blocks::tsunami.ide 1.296059 # Average occupied blocks per requestor 946system.iocache.tags.occ_percent::tsunami.ide 0.081004 # Average percentage of cache occupancy 947system.iocache.tags.occ_percent::total 0.081004 # Average percentage of cache occupancy 948system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 949system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 950system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 951system.iocache.tags.tag_accesses 375525 # Number of tag accesses 952system.iocache.tags.data_accesses 375525 # Number of data accesses 953system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 954system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 955system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 956system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 957system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 958system.iocache.demand_misses::total 173 # number of demand (read+write) misses 959system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 960system.iocache.overall_misses::total 173 # number of overall misses 961system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 962system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 963system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635314907 # number of WriteInvalidateReq miss cycles 964system.iocache.WriteInvalidateReq_miss_latency::total 13635314907 # number of WriteInvalidateReq miss cycles 965system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 966system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 967system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 968system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles 969system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 970system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 971system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 972system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 973system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 974system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 975system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 976system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 977system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 978system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 979system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 980system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 981system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 982system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 983system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 984system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 985system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 986system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 987system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328150.628297 # average WriteInvalidateReq miss latency 988system.iocache.WriteInvalidateReq_avg_miss_latency::total 328150.628297 # average WriteInvalidateReq miss latency 989system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 990system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency 991system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 992system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency 993system.iocache.blocked_cycles::no_mshrs 206297 # number of cycles access was blocked 994system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 995system.iocache.blocked::no_mshrs 23564 # number of cycles access was blocked 996system.iocache.blocked::no_targets 0 # number of cycles access was blocked 997system.iocache.avg_blocked_cycles::no_mshrs 8.754753 # average number of cycles each access was blocked 998system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 999system.iocache.fast_writes 0 # number of fast writes performed 1000system.iocache.cache_copies 0 # number of cache copies performed 1001system.iocache.writebacks::writebacks 41512 # number of writebacks 1002system.iocache.writebacks::total 41512 # number of writebacks 1003system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1004system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1005system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1006system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 1007system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1008system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1009system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1010system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1011system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 1012system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 1013system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474610907 # number of WriteInvalidateReq MSHR miss cycles 1014system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474610907 # number of WriteInvalidateReq MSHR miss cycles 1015system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 1016system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 1017system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 1018system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 1019system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1020system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1021system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1022system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1023system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1024system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1025system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1026system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1027system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 1028system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency 1029system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276150.628297 # average WriteInvalidateReq mshr miss latency 1030system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276150.628297 # average WriteInvalidateReq mshr miss latency 1031system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 1032system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 1033system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 1034system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 1035system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1036system.membus.trans_dist::ReadReq 295796 # Transaction distribution 1037system.membus.trans_dist::ReadResp 295780 # Transaction distribution 1038system.membus.trans_dist::WriteReq 9619 # Transaction distribution 1039system.membus.trans_dist::WriteResp 9619 # Transaction distribution 1040system.membus.trans_dist::Writeback 118147 # Transaction distribution 1041system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1042system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 1043system.membus.trans_dist::UpgradeReq 155 # Transaction distribution 1044system.membus.trans_dist::UpgradeResp 155 # Transaction distribution 1045system.membus.trans_dist::ReadExReq 116517 # Transaction distribution 1046system.membus.trans_dist::ReadExResp 116517 # Transaction distribution 1047system.membus.trans_dist::BadAddressError 16 # Transaction distribution 1048system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) 1049system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887058 # Packet count per connected master and slave (bytes) 1050system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) 1051system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920188 # Packet count per connected master and slave (bytes) 1052system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1053system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) 1054system.membus.pkt_count::total 1044992 # Packet count per connected master and slave (bytes) 1055system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) 1056system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819584 # Cumulative packet size per connected master and slave (bytes) 1057system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30863900 # Cumulative packet size per connected master and slave (bytes) 1058system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1059system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) 1060system.membus.pkt_size::total 36180956 # Cumulative packet size per connected master and slave (bytes) 1061system.membus.snoops 433 # Total snoops (count) 1062system.membus.snoop_fanout::samples 565237 # Request fanout histogram 1063system.membus.snoop_fanout::mean 1 # Request fanout histogram 1064system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1065system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1066system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1067system.membus.snoop_fanout::1 565237 100.00% 100.00% # Request fanout histogram 1068system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1069system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1070system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1071system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1072system.membus.snoop_fanout::total 565237 # Request fanout histogram 1073system.membus.reqLayer0.occupancy 30298500 # Layer occupancy (ticks) 1074system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1075system.membus.reqLayer1.occupancy 1878232500 # Layer occupancy (ticks) 1076system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1077system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) 1078system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1079system.membus.respLayer1.occupancy 3792450097 # Layer occupancy (ticks) 1080system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1081system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) 1082system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1083system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1084system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1085system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1086system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1087system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1088system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1089system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1090system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1091system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1092system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1093system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1094system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1095system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1096system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1097system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1098system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1099system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1100system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1101system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1102system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1103system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1104system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1105system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1106system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1107system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1108system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1109system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1110system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1111system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1112system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1113system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 1109 1110---------- End Simulation Statistics ---------- | 1114 1115---------- End Simulation Statistics ---------- |