| stats.txt (10433:821cbe4a183b) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.883224 # Number of seconds simulated 4sim_ticks 1883224346500 # Number of ticks simulated 5final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.883224 # Number of seconds simulated 4sim_ticks 1883224346500 # Number of ticks simulated 5final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 293967 # Simulator instruction rate (inst/s) 8host_op_rate 293967 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9864607727 # Simulator tick rate (ticks/s) 10host_mem_usage 317632 # Number of bytes of host memory used 11host_seconds 190.91 # Real time elapsed on the host | 7host_inst_rate 279379 # Simulator instruction rate (inst/s) 8host_op_rate 279379 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9375076807 # Simulator tick rate (ticks/s) 10host_mem_usage 311380 # Number of bytes of host memory used 11host_seconds 200.88 # Real time elapsed on the host |
| 12sim_insts 56120453 # Number of instructions simulated 13sim_ops 56120453 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 25931648 # Number of bytes read from this memory 17system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25932608 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory --- 384 unchanged lines hidden (view full) --- 404system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 405system.iocache.blocked::no_targets 0 # number of cycles access was blocked 406system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 407system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 408system.iocache.fast_writes 41552 # number of fast writes performed 409system.iocache.cache_copies 0 # number of cache copies performed 410system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 411system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses | 12sim_insts 56120453 # Number of instructions simulated 13sim_ops 56120453 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 25931648 # Number of bytes read from this memory 17system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25932608 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory --- 384 unchanged lines hidden (view full) --- 404system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 405system.iocache.blocked::no_targets 0 # number of cycles access was blocked 406system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 407system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 408system.iocache.fast_writes 41552 # number of fast writes performed 409system.iocache.cache_copies 0 # number of cache copies performed 410system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 411system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses |
| 412system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 413system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses | |
| 414system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 415system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 416system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 417system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 418system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 419system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 420system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512658057 # number of WriteInvalidateReq MSHR miss cycles 421system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512658057 # number of WriteInvalidateReq MSHR miss cycles 422system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 423system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 424system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 425system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 426system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 427system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 412system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 413system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 414system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 415system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 416system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 417system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 418system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512658057 # number of WriteInvalidateReq MSHR miss cycles 419system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512658057 # number of WriteInvalidateReq MSHR miss cycles 420system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 421system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 422system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 423system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 424system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 425system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 428system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 429system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses | |
| 430system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 431system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 432system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 433system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 434system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 435system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency | 426system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 427system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 428system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 429system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 430system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 431system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency |
| 436system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60470.207379 # average WriteInvalidateReq mshr miss latency 437system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60470.207379 # average WriteInvalidateReq mshr miss latency | 432system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency 433system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 438system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 439system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 440system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 441system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 442system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 443system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 444system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 445system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 669 unchanged lines hidden --- | 434system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 435system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 436system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 437system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 438system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 439system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 440system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 441system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 669 unchanged lines hidden --- |