| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.883224 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.883224 # Number of seconds simulated |
| 4sim_ticks 1883223940000 # Number of ticks simulated 5final_tick 1883223940000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 1883224346500 # Number of ticks simulated 5final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 180615 # Simulator instruction rate (inst/s) 8host_op_rate 180615 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6060637883 # Simulator tick rate (ticks/s) 10host_mem_usage 316396 # Number of bytes of host memory used 11host_seconds 310.73 # Real time elapsed on the host 12sim_insts 56122642 # Number of instructions simulated 13sim_ops 56122642 # Number of ops (including micro ops) simulated | 7host_inst_rate 283997 # Simulator instruction rate (inst/s) 8host_op_rate 283997 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9530044697 # Simulator tick rate (ticks/s) 10host_mem_usage 369276 # Number of bytes of host memory used 11host_seconds 197.61 # Real time elapsed on the host 12sim_insts 56120453 # Number of instructions simulated 13sim_ops 56120453 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 25930944 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 25931648 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 17system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::total 25931904 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4902720 # Number of bytes written to this memory | 18system.physmem.bytes_read::total 25932608 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4903936 # Number of bytes written to this memory |
| 22system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory | 22system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory |
| 23system.physmem.bytes_written::total 7562048 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 405171 # Number of read requests responded to by this memory | 23system.physmem.bytes_written::total 7563264 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 405182 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 25system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::total 405186 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 76605 # Number of write requests responded to by this memory | 26system.physmem.num_reads::total 405197 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 76624 # Number of write requests responded to by this memory |
| 28system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory | 28system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory |
| 29system.physmem.num_writes::total 118157 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 13769443 # Total read bandwidth from this memory (bytes/s) | 29system.physmem.num_writes::total 118176 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 13769813 # Total read bandwidth from this memory (bytes/s) |
| 31system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s) | 31system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s) |
| 32system.physmem.bw_read::total 13769952 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::cpu.inst 558905 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::total 558905 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_write::writebacks 2603365 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_write::tsunami.ide 1412115 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4015480 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 2603365 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 13769443 # Total bandwidth to/from this memory (bytes/s) | 32system.physmem.bw_read::total 13770323 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::cpu.inst 559041 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::total 559041 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_write::writebacks 2604011 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_write::tsunami.ide 1412114 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4016125 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 2604011 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 13769813 # Total bandwidth to/from this memory (bytes/s) |
| 40system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s) | 40system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s) |
| 41system.physmem.bw_total::total 17785432 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.readReqs 405186 # Number of read requests accepted 43system.physmem.writeReqs 118157 # Number of write requests accepted 44system.physmem.readBursts 405186 # Number of DRAM read bursts, including those serviced by the write queue 45system.physmem.writeBursts 118157 # Number of DRAM write bursts, including those merged in the write queue 46system.physmem.bytesReadDRAM 25919424 # Total number of bytes read from DRAM 47system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue 48system.physmem.bytesWritten 7560064 # Total number of bytes written to DRAM 49system.physmem.bytesReadSys 25931904 # Total read bytes from the system interface side 50system.physmem.bytesWrittenSys 7562048 # Total written bytes from the system interface side 51system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue | 41system.physmem.bw_total::total 17786448 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.readReqs 405197 # Number of read requests accepted 43system.physmem.writeReqs 118176 # Number of write requests accepted 44system.physmem.readBursts 405197 # Number of DRAM read bursts, including those serviced by the write queue 45system.physmem.writeBursts 118176 # Number of DRAM write bursts, including those merged in the write queue 46system.physmem.bytesReadDRAM 25920704 # Total number of bytes read from DRAM 47system.physmem.bytesReadWrQ 11904 # Total number of bytes read from write queue 48system.physmem.bytesWritten 7562112 # Total number of bytes written to DRAM 49system.physmem.bytesReadSys 25932608 # Total read bytes from the system interface side 50system.physmem.bytesWrittenSys 7563264 # Total written bytes from the system interface side 51system.physmem.servicedByWrQ 186 # Number of DRAM read bursts serviced by the write queue |
| 52system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 52system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 53system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write 54system.physmem.perBankRdBursts::0 25480 # Per bank write bursts 55system.physmem.perBankRdBursts::1 25741 # Per bank write bursts 56system.physmem.perBankRdBursts::2 25855 # Per bank write bursts | 53system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write 54system.physmem.perBankRdBursts::0 25484 # Per bank write bursts 55system.physmem.perBankRdBursts::1 25740 # Per bank write bursts 56system.physmem.perBankRdBursts::2 25857 # Per bank write bursts |
| 57system.physmem.perBankRdBursts::3 25788 # Per bank write bursts | 57system.physmem.perBankRdBursts::3 25788 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::4 25233 # Per bank write bursts 59system.physmem.perBankRdBursts::5 24956 # Per bank write bursts 60system.physmem.perBankRdBursts::6 24811 # Per bank write bursts | 58system.physmem.perBankRdBursts::4 25237 # Per bank write bursts 59system.physmem.perBankRdBursts::5 24959 # Per bank write bursts 60system.physmem.perBankRdBursts::6 24814 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::7 24586 # Per bank write bursts 62system.physmem.perBankRdBursts::8 25127 # Per bank write bursts | 61system.physmem.perBankRdBursts::7 24586 # Per bank write bursts 62system.physmem.perBankRdBursts::8 25127 # Per bank write bursts |
| 63system.physmem.perBankRdBursts::9 25280 # Per bank write bursts 64system.physmem.perBankRdBursts::10 25532 # Per bank write bursts | 63system.physmem.perBankRdBursts::9 25284 # Per bank write bursts 64system.physmem.perBankRdBursts::10 25531 # Per bank write bursts |
| 65system.physmem.perBankRdBursts::11 24857 # Per bank write bursts | 65system.physmem.perBankRdBursts::11 24857 # Per bank write bursts |
| 66system.physmem.perBankRdBursts::12 24547 # Per bank write bursts 67system.physmem.perBankRdBursts::13 25588 # Per bank write bursts 68system.physmem.perBankRdBursts::14 25870 # Per bank write bursts | 66system.physmem.perBankRdBursts::12 24549 # Per bank write bursts 67system.physmem.perBankRdBursts::13 25592 # Per bank write bursts 68system.physmem.perBankRdBursts::14 25866 # Per bank write bursts |
| 69system.physmem.perBankRdBursts::15 25740 # Per bank write bursts 70system.physmem.perBankWrBursts::0 7812 # Per bank write bursts | 69system.physmem.perBankRdBursts::15 25740 # Per bank write bursts 70system.physmem.perBankWrBursts::0 7812 # Per bank write bursts |
| 71system.physmem.perBankWrBursts::1 7677 # Per bank write bursts | 71system.physmem.perBankWrBursts::1 7680 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::2 8067 # Per bank write bursts | 72system.physmem.perBankWrBursts::2 8067 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::3 7744 # Per bank write bursts 74system.physmem.perBankWrBursts::4 7318 # Per bank write bursts 75system.physmem.perBankWrBursts::5 6954 # Per bank write bursts 76system.physmem.perBankWrBursts::6 6788 # Per bank write bursts 77system.physmem.perBankWrBursts::7 6406 # Per bank write bursts 78system.physmem.perBankWrBursts::8 7235 # Per bank write bursts 79system.physmem.perBankWrBursts::9 6889 # Per bank write bursts 80system.physmem.perBankWrBursts::10 7393 # Per bank write bursts 81system.physmem.perBankWrBursts::11 6865 # Per bank write bursts | 73system.physmem.perBankWrBursts::3 7745 # Per bank write bursts 74system.physmem.perBankWrBursts::4 7320 # Per bank write bursts 75system.physmem.perBankWrBursts::5 6957 # Per bank write bursts 76system.physmem.perBankWrBursts::6 6792 # Per bank write bursts 77system.physmem.perBankWrBursts::7 6401 # Per bank write bursts 78system.physmem.perBankWrBursts::8 7236 # Per bank write bursts 79system.physmem.perBankWrBursts::9 6892 # Per bank write bursts 80system.physmem.perBankWrBursts::10 7391 # Per bank write bursts 81system.physmem.perBankWrBursts::11 6866 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::12 7045 # Per bank write bursts | 82system.physmem.perBankWrBursts::12 7045 # Per bank write bursts |
| 83system.physmem.perBankWrBursts::13 8007 # Per bank write bursts | 83system.physmem.perBankWrBursts::13 8010 # Per bank write bursts |
| 84system.physmem.perBankWrBursts::14 7989 # Per bank write bursts | 84system.physmem.perBankWrBursts::14 7989 # Per bank write bursts |
| 85system.physmem.perBankWrBursts::15 7937 # Per bank write bursts | 85system.physmem.perBankWrBursts::15 7955 # Per bank write bursts |
| 86system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 86system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 87system.physmem.numWrRetry 5 # Number of times write queue was full causing retry 88system.physmem.totGap 1883215178500 # Total gap between requests | 87system.physmem.numWrRetry 7 # Number of times write queue was full causing retry 88system.physmem.totGap 1883215617500 # Total gap between requests |
| 89system.physmem.readPktSize::0 0 # Read request sizes (log2) 90system.physmem.readPktSize::1 0 # Read request sizes (log2) 91system.physmem.readPktSize::2 0 # Read request sizes (log2) 92system.physmem.readPktSize::3 0 # Read request sizes (log2) 93system.physmem.readPktSize::4 0 # Read request sizes (log2) 94system.physmem.readPktSize::5 0 # Read request sizes (log2) | 89system.physmem.readPktSize::0 0 # Read request sizes (log2) 90system.physmem.readPktSize::1 0 # Read request sizes (log2) 91system.physmem.readPktSize::2 0 # Read request sizes (log2) 92system.physmem.readPktSize::3 0 # Read request sizes (log2) 93system.physmem.readPktSize::4 0 # Read request sizes (log2) 94system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 95system.physmem.readPktSize::6 405186 # Read request sizes (log2) | 95system.physmem.readPktSize::6 405197 # Read request sizes (log2) |
| 96system.physmem.writePktSize::0 0 # Write request sizes (log2) 97system.physmem.writePktSize::1 0 # Write request sizes (log2) 98system.physmem.writePktSize::2 0 # Write request sizes (log2) 99system.physmem.writePktSize::3 0 # Write request sizes (log2) 100system.physmem.writePktSize::4 0 # Write request sizes (log2) 101system.physmem.writePktSize::5 0 # Write request sizes (log2) | 96system.physmem.writePktSize::0 0 # Write request sizes (log2) 97system.physmem.writePktSize::1 0 # Write request sizes (log2) 98system.physmem.writePktSize::2 0 # Write request sizes (log2) 99system.physmem.writePktSize::3 0 # Write request sizes (log2) 100system.physmem.writePktSize::4 0 # Write request sizes (log2) 101system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 102system.physmem.writePktSize::6 118157 # Write request sizes (log2) 103system.physmem.rdQLenPdf::0 402670 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::1 2243 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see | 102system.physmem.writePktSize::6 118176 # Write request sizes (log2) 103system.physmem.rdQLenPdf::0 402689 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::1 2242 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 142system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 142system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 150system.physmem.wrQLenPdf::15 1541 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::16 2210 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::17 5693 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::18 5920 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::19 6144 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::20 6907 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::21 7208 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::23 8700 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::24 8681 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::25 8384 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::26 8515 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::27 7009 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::28 6582 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::29 5776 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::30 5533 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::31 5557 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::32 5513 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::33 225 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::37 158 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::39 112 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::40 118 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::41 140 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::43 148 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::44 178 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::45 193 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::46 184 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::48 173 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::51 123 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::54 108 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::55 101 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see 199system.physmem.bytesPerActivate::samples 62955 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::mean 531.800302 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::gmean 324.503879 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::stdev 415.177975 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::0-127 14434 22.93% 22.93% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::128-255 10626 16.88% 39.81% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::256-383 4984 7.92% 47.72% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::384-511 3035 4.82% 52.54% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::512-639 2479 3.94% 56.48% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::640-767 2063 3.28% 59.76% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::768-895 1365 2.17% 61.93% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::896-1023 1615 2.57% 64.49% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::1024-1151 22354 35.51% 100.00% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::total 62955 # Bytes accessed per row activation 213system.physmem.rdPerTurnAround::samples 5310 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::mean 76.265725 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::stdev 2898.384419 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::0-8191 5307 99.94% 99.94% # Reads before turning the bus around for writes | 150system.physmem.wrQLenPdf::15 1502 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::16 2155 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::18 5922 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::19 6116 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::21 7165 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::22 8341 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::24 8743 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::25 8450 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::26 8575 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::27 7104 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::28 6692 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::29 5817 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::30 5536 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::31 5545 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::32 5502 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::34 184 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::35 186 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::36 168 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::43 152 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::49 96 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::53 94 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::55 125 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see 199system.physmem.bytesPerActivate::samples 63140 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::mean 530.294837 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::gmean 322.585016 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::stdev 415.640457 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::0-127 14650 23.20% 23.20% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::128-255 10589 16.77% 39.97% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::256-383 5075 8.04% 48.01% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::384-511 3003 4.76% 52.77% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::512-639 2370 3.75% 56.52% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::640-767 2105 3.33% 59.85% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::768-895 1364 2.16% 62.01% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::896-1023 1607 2.55% 64.56% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::1024-1151 22377 35.44% 100.00% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::total 63140 # Bytes accessed per row activation 213system.physmem.rdPerTurnAround::samples 5316 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::mean 76.186983 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::stdev 2896.748549 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::0-8191 5313 99.94% 99.94% # Reads before turning the bus around for writes |
| 217system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 217system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 220system.physmem.rdPerTurnAround::total 5310 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 5310 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 22.245951 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 18.963647 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 20.434666 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16-19 4660 87.76% 87.76% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::20-23 16 0.30% 88.06% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::24-27 15 0.28% 88.34% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::28-31 227 4.27% 92.62% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-35 38 0.72% 93.33% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::36-39 5 0.09% 93.43% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::40-43 8 0.15% 93.58% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::44-47 6 0.11% 93.69% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::48-51 26 0.49% 94.18% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::52-55 4 0.08% 94.26% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::56-59 5 0.09% 94.35% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::64-67 14 0.26% 94.61% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::68-71 2 0.04% 94.65% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::72-75 5 0.09% 94.75% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::80-83 26 0.49% 95.24% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::84-87 9 0.17% 95.40% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::88-91 5 0.09% 95.50% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::92-95 6 0.11% 95.61% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::96-99 182 3.43% 99.04% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::100-103 6 0.11% 99.15% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::108-111 1 0.02% 99.17% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::112-115 2 0.04% 99.21% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::120-123 3 0.06% 99.27% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::128-131 6 0.11% 99.42% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::132-135 5 0.09% 99.51% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::136-139 4 0.08% 99.59% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::140-143 2 0.04% 99.62% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::144-147 7 0.13% 99.76% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::152-155 1 0.02% 99.77% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::160-163 5 0.09% 99.89% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::176-179 2 0.04% 99.92% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads | 220system.physmem.rdPerTurnAround::total 5316 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 5316 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 22.226862 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 18.933757 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 20.590348 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16-19 4662 87.70% 87.70% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::20-23 15 0.28% 87.98% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::24-27 21 0.40% 88.37% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::28-31 225 4.23% 92.61% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-35 46 0.87% 93.47% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::36-39 10 0.19% 93.66% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::40-43 7 0.13% 93.79% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::44-47 7 0.13% 93.92% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::48-51 19 0.36% 94.28% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::52-55 3 0.06% 94.34% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::56-59 2 0.04% 94.38% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::60-63 2 0.04% 94.41% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::64-67 12 0.23% 94.64% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::68-71 1 0.02% 94.66% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::72-75 6 0.11% 94.77% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::80-83 29 0.55% 95.32% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::84-87 14 0.26% 95.58% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::88-91 2 0.04% 95.62% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::92-95 12 0.23% 95.84% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::96-99 164 3.09% 98.93% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::100-103 5 0.09% 99.02% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::104-107 1 0.02% 99.04% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::112-115 2 0.04% 99.08% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::120-123 3 0.06% 99.13% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::124-127 1 0.02% 99.15% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::128-131 4 0.08% 99.23% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::132-135 3 0.06% 99.29% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::136-139 8 0.15% 99.44% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::140-143 6 0.11% 99.55% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::144-147 12 0.23% 99.77% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::148-151 1 0.02% 99.79% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::152-155 3 0.06% 99.85% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::164-167 1 0.02% 99.87% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::168-171 1 0.02% 99.89% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::176-179 3 0.06% 99.94% # Writes before turning the bus around for reads |
| 259system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads | 260system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads |
| 260system.physmem.wrPerTurnAround::total 5310 # Writes before turning the bus around for reads 261system.physmem.totQLat 2131293750 # Total ticks spent queuing 262system.physmem.totMemAccLat 9724875000 # Total ticks spent from burst creation until serviced by the DRAM 263system.physmem.totBusLat 2024955000 # Total ticks spent in databus transfers 264system.physmem.avgQLat 5262.57 # Average queueing delay per DRAM burst | 261system.physmem.wrPerTurnAround::total 5316 # Writes before turning the bus around for reads 262system.physmem.totQLat 2156220500 # Total ticks spent queuing 263system.physmem.totMemAccLat 9750176750 # Total ticks spent from burst creation until serviced by the DRAM 264system.physmem.totBusLat 2025055000 # Total ticks spent in databus transfers 265system.physmem.avgQLat 5323.86 # Average queueing delay per DRAM burst |
| 265system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 266system.physmem.avgMemAccLat 24012.57 # Average memory access latency per DRAM burst | 267system.physmem.avgMemAccLat 24073.86 # Average memory access latency per DRAM burst |
| 267system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s | 268system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s |
| 268system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s | 269system.physmem.avgWrBW 4.02 # Average achieved write bandwidth in MiByte/s |
| 269system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s 270system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s 271system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 272system.physmem.busUtil 0.14 # Data bus utilization in percentage 273system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 274system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 275system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 270system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 273system.physmem.busUtil 0.14 # Data bus utilization in percentage 274system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 276system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 276system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing 277system.physmem.readRowHits 364467 # Number of row buffer hits during reads 278system.physmem.writeRowHits 95695 # Number of row buffer hits during writes 279system.physmem.readRowHitRate 89.99 # Row buffer hit rate for reads 280system.physmem.writeRowHitRate 80.99 # Row buffer hit rate for writes 281system.physmem.avgGap 3598433.87 # Average gap between requests 282system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined 283system.physmem.memoryStateTime::IDLE 1774121817500 # Time in different power states | 277system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing 278system.physmem.readRowHits 364400 # Number of row buffer hits during reads 279system.physmem.writeRowHits 95629 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 89.97 # Row buffer hit rate for reads 281system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes 282system.physmem.avgGap 3598228.45 # Average gap between requests 283system.physmem.pageHitRate 87.93 # Row buffer hit rate, read and write combined 284system.physmem.memoryStateTime::IDLE 1774012993500 # Time in different power states |
| 284system.physmem.memoryStateTime::REF 62884900000 # Time in different power states 285system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 285system.physmem.memoryStateTime::REF 62884900000 # Time in different power states 286system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 286system.physmem.memoryStateTime::ACT 46214912500 # Time in different power states | 287system.physmem.memoryStateTime::ACT 46323736500 # Time in different power states |
| 287system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 288system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 288system.membus.throughput 17814330 # Throughput (bytes/s) 289system.membus.trans_dist::ReadReq 295751 # Transaction distribution 290system.membus.trans_dist::ReadResp 295735 # Transaction distribution | 289system.membus.trans_dist::ReadReq 295760 # Transaction distribution 290system.membus.trans_dist::ReadResp 295744 # Transaction distribution |
| 291system.membus.trans_dist::WriteReq 9618 # Transaction distribution 292system.membus.trans_dist::WriteResp 9618 # Transaction distribution | 291system.membus.trans_dist::WriteReq 9618 # Transaction distribution 292system.membus.trans_dist::WriteResp 9618 # Transaction distribution |
| 293system.membus.trans_dist::Writeback 76605 # Transaction distribution | 293system.membus.trans_dist::Writeback 76624 # Transaction distribution |
| 294system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 295system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution | 294system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 295system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution |
| 296system.membus.trans_dist::UpgradeReq 157 # Transaction distribution 297system.membus.trans_dist::UpgradeResp 157 # Transaction distribution 298system.membus.trans_dist::ReadExReq 116539 # Transaction distribution 299system.membus.trans_dist::ReadExResp 116539 # Transaction distribution | 296system.membus.trans_dist::UpgradeReq 154 # Transaction distribution 297system.membus.trans_dist::UpgradeResp 154 # Transaction distribution 298system.membus.trans_dist::ReadExReq 116541 # Transaction distribution 299system.membus.trans_dist::ReadExResp 116541 # Transaction distribution |
| 300system.membus.trans_dist::BadAddressError 16 # Transaction distribution 301system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes) | 300system.membus.trans_dist::BadAddressError 16 # Transaction distribution 301system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes) |
| 302system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887261 # Packet count per connected master and slave (bytes) | 302system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887296 # Packet count per connected master and slave (bytes) |
| 303system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) | 303system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) |
| 304system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920389 # Packet count per connected master and slave (bytes) | 304system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920424 # Packet count per connected master and slave (bytes) |
| 305system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) | 305system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) |
| 307system.membus.pkt_count::total 1003681 # Packet count per connected master and slave (bytes) 308system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes) 309system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30833664 # Cumulative packet size per connected master and slave (bytes) 310system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30877972 # Cumulative packet size per connected master and slave (bytes) 311system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size::total 33538260 # Cumulative packet size per connected master and slave (bytes) 314system.membus.data_through_bus 33538260 # Total data (bytes) 315system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) 316system.membus.reqLayer0.occupancy 29840000 # Layer occupancy (ticks) | 307system.membus.pkt_count::total 1003716 # Packet count per connected master and slave (bytes) 308system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes) 309system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30835584 # Cumulative packet size per connected master and slave (bytes) 310system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30879892 # Cumulative packet size per connected master and slave (bytes) 311system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 312system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 313system.membus.pkt_size::total 33540180 # Cumulative packet size per connected master and slave (bytes) 314system.membus.snoops 158 # Total snoops (count) 315system.membus.snoop_fanout::samples 523708 # Request fanout histogram 316system.membus.snoop_fanout::mean 1 # Request fanout histogram 317system.membus.snoop_fanout::stdev 0 # Request fanout histogram 318system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 319system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 320system.membus.snoop_fanout::1 523708 100.00% 100.00% # Request fanout histogram 321system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 322system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 323system.membus.snoop_fanout::min_value 1 # Request fanout histogram 324system.membus.snoop_fanout::max_value 1 # Request fanout histogram 325system.membus.snoop_fanout::total 523708 # Request fanout histogram 326system.membus.reqLayer0.occupancy 30927500 # Layer occupancy (ticks) |
| 317system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 327system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 318system.membus.reqLayer1.occupancy 1547069500 # Layer occupancy (ticks) | 328system.membus.reqLayer1.occupancy 1547261750 # Layer occupancy (ticks) |
| 319system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 329system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 320system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks) | 330system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) |
| 321system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 331system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 322system.membus.respLayer1.occupancy 3825068843 # Layer occupancy (ticks) | 332system.membus.respLayer1.occupancy 3825161596 # Layer occupancy (ticks) |
| 323system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 333system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 324system.membus.respLayer2.occupancy 43112000 # Layer occupancy (ticks) | 334system.membus.respLayer2.occupancy 43114249 # Layer occupancy (ticks) |
| 325system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 326system.iocache.tags.replacements 41685 # number of replacements | 335system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 336system.iocache.tags.replacements 41685 # number of replacements |
| 327system.iocache.tags.tagsinuse 1.288165 # Cycle average of tags in use | 337system.iocache.tags.tagsinuse 1.288180 # Cycle average of tags in use |
| 328system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 329system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 330system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 338system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 339system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 340system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 331system.iocache.tags.warmup_cycle 1728026235000 # Cycle when the warmup percentage was hit. 332system.iocache.tags.occ_blocks::tsunami.ide 1.288165 # Average occupied blocks per requestor 333system.iocache.tags.occ_percent::tsunami.ide 0.080510 # Average percentage of cache occupancy 334system.iocache.tags.occ_percent::total 0.080510 # Average percentage of cache occupancy | 341system.iocache.tags.warmup_cycle 1728025257000 # Cycle when the warmup percentage was hit. 342system.iocache.tags.occ_blocks::tsunami.ide 1.288180 # Average occupied blocks per requestor 343system.iocache.tags.occ_percent::tsunami.ide 0.080511 # Average percentage of cache occupancy 344system.iocache.tags.occ_percent::total 0.080511 # Average percentage of cache occupancy |
| 335system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 336system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 337system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 345system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 346system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 347system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 338system.iocache.tags.tag_accesses 375533 # Number of tag accesses 339system.iocache.tags.data_accesses 375533 # Number of data accesses | 348system.iocache.tags.tag_accesses 375525 # Number of tag accesses 349system.iocache.tags.data_accesses 375525 # Number of data accesses |
| 340system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 341system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 342system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 343system.iocache.ReadReq_misses::total 173 # number of ReadReq misses | 350system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 351system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 352system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 353system.iocache.ReadReq_misses::total 173 # number of ReadReq misses |
| 344system.iocache.WriteInvalidateReq_misses::tsunami.ide 1 # number of WriteInvalidateReq misses 345system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses | |
| 346system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 347system.iocache.demand_misses::total 173 # number of demand (read+write) misses 348system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 349system.iocache.overall_misses::total 173 # number of overall misses | 354system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 355system.iocache.demand_misses::total 173 # number of demand (read+write) misses 356system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 357system.iocache.overall_misses::total 173 # number of overall misses |
| 350system.iocache.ReadReq_miss_latency::tsunami.ide 21132383 # number of ReadReq miss cycles 351system.iocache.ReadReq_miss_latency::total 21132383 # number of ReadReq miss cycles 352system.iocache.demand_miss_latency::tsunami.ide 21132383 # number of demand (read+write) miss cycles 353system.iocache.demand_miss_latency::total 21132383 # number of demand (read+write) miss cycles 354system.iocache.overall_miss_latency::tsunami.ide 21132383 # number of overall miss cycles 355system.iocache.overall_miss_latency::total 21132383 # number of overall miss cycles | 358system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 359system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 360system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 361system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 362system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 363system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles |
| 356system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 357system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) | 364system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 365system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) |
| 358system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41553 # number of WriteInvalidateReq accesses(hits+misses) 359system.iocache.WriteInvalidateReq_accesses::total 41553 # number of WriteInvalidateReq accesses(hits+misses) | 366system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 367system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) |
| 360system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 361system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 362system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 363system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 364system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 365system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 368system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 369system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 370system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 371system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 372system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 373system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 366system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000024 # miss rate for WriteInvalidateReq accesses 367system.iocache.WriteInvalidateReq_miss_rate::total 0.000024 # miss rate for WriteInvalidateReq accesses | |
| 368system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 369system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 370system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 371system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 374system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 375system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 376system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 377system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 372system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122152.502890 # average ReadReq miss latency 373system.iocache.ReadReq_avg_miss_latency::total 122152.502890 # average ReadReq miss latency 374system.iocache.demand_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency 375system.iocache.demand_avg_miss_latency::total 122152.502890 # average overall miss latency 376system.iocache.overall_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency 377system.iocache.overall_avg_miss_latency::total 122152.502890 # average overall miss latency | 378system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 379system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 380system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 381system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency 382system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 383system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency |
| 378system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 379system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 380system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 381system.iocache.blocked::no_targets 0 # number of cycles access was blocked 382system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 383system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 384system.iocache.fast_writes 41552 # number of fast writes performed 385system.iocache.cache_copies 0 # number of cache copies performed 386system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 387system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 388system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 389system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 390system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 391system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 392system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 393system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses | 384system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 385system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 386system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 387system.iocache.blocked::no_targets 0 # number of cycles access was blocked 388system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 389system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 390system.iocache.fast_writes 41552 # number of fast writes performed 391system.iocache.cache_copies 0 # number of cache copies performed 392system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 393system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 394system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 395system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 396system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 397system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 398system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 399system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses |
| 394system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12135383 # number of ReadReq MSHR miss cycles 395system.iocache.ReadReq_mshr_miss_latency::total 12135383 # number of ReadReq MSHR miss cycles 396system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2514597305 # number of WriteInvalidateReq MSHR miss cycles 397system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2514597305 # number of WriteInvalidateReq MSHR miss cycles 398system.iocache.demand_mshr_miss_latency::tsunami.ide 12135383 # number of demand (read+write) MSHR miss cycles 399system.iocache.demand_mshr_miss_latency::total 12135383 # number of demand (read+write) MSHR miss cycles 400system.iocache.overall_mshr_miss_latency::tsunami.ide 12135383 # number of overall MSHR miss cycles 401system.iocache.overall_mshr_miss_latency::total 12135383 # number of overall MSHR miss cycles | 400system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 401system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 402system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512658057 # number of WriteInvalidateReq MSHR miss cycles 403system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512658057 # number of WriteInvalidateReq MSHR miss cycles 404system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 405system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 406system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 407system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles |
| 402system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 403system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 408system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 409system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 404system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999976 # mshr miss rate for WriteInvalidateReq accesses 405system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999976 # mshr miss rate for WriteInvalidateReq accesses | 410system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 411system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses |
| 406system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 407system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 408system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 409system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 412system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 413system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 414system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 415system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 410system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average ReadReq mshr miss latency 411system.iocache.ReadReq_avg_mshr_miss_latency::total 70146.722543 # average ReadReq mshr miss latency 412system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60516.877768 # average WriteInvalidateReq mshr miss latency 413system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60516.877768 # average WriteInvalidateReq mshr miss latency 414system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency 415system.iocache.demand_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency 416system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency 417system.iocache.overall_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency | 416system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 417system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency 418system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60470.207379 # average WriteInvalidateReq mshr miss latency 419system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60470.207379 # average WriteInvalidateReq mshr miss latency 420system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 421system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 422system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 423system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency |
| 418system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 419system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 420system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 421system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 422system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 423system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 424system.disk0.dma_write_txs 395 # Number of DMA write transactions. 425system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 426system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 427system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 428system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 429system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 430system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 424system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 425system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 426system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 427system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 428system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 429system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 430system.disk0.dma_write_txs 395 # Number of DMA write transactions. 431system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 432system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 433system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 434system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 435system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 436system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 431system.cpu.branchPred.lookups 14964215 # Number of BP lookups 432system.cpu.branchPred.condPredicted 12981470 # Number of conditional branches predicted 433system.cpu.branchPred.condIncorrect 376025 # Number of conditional branches incorrect 434system.cpu.branchPred.BTBLookups 10003487 # Number of BTB lookups 435system.cpu.branchPred.BTBHits 5188980 # Number of BTB hits | 437system.cpu.branchPred.lookups 14964931 # Number of BP lookups 438system.cpu.branchPred.condPredicted 12983118 # Number of conditional branches predicted 439system.cpu.branchPred.condIncorrect 374694 # Number of conditional branches incorrect 440system.cpu.branchPred.BTBLookups 9691016 # Number of BTB lookups 441system.cpu.branchPred.BTBHits 5184483 # Number of BTB hits |
| 436system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 442system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 437system.cpu.branchPred.BTBHitPct 51.871712 # BTB Hit Percentage 438system.cpu.branchPred.usedRAS 807651 # Number of times the RAS was used to get a target. 439system.cpu.branchPred.RASInCorrect 32040 # Number of incorrect RAS predictions. | 443system.cpu.branchPred.BTBHitPct 53.497827 # BTB Hit Percentage 444system.cpu.branchPred.usedRAS 807557 # Number of times the RAS was used to get a target. 445system.cpu.branchPred.RASInCorrect 32108 # Number of incorrect RAS predictions. |
| 440system.cpu_clk_domain.clock 500 # Clock period in ticks 441system.cpu.dtb.fetch_hits 0 # ITB hits 442system.cpu.dtb.fetch_misses 0 # ITB misses 443system.cpu.dtb.fetch_acv 0 # ITB acv 444system.cpu.dtb.fetch_accesses 0 # ITB accesses | 446system.cpu_clk_domain.clock 500 # Clock period in ticks 447system.cpu.dtb.fetch_hits 0 # ITB hits 448system.cpu.dtb.fetch_misses 0 # ITB misses 449system.cpu.dtb.fetch_acv 0 # ITB acv 450system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 445system.cpu.dtb.read_hits 9238395 # DTB read hits 446system.cpu.dtb.read_misses 17814 # DTB read misses | 451system.cpu.dtb.read_hits 9237824 # DTB read hits 452system.cpu.dtb.read_misses 17804 # DTB read misses |
| 447system.cpu.dtb.read_acv 211 # DTB read access violations | 453system.cpu.dtb.read_acv 211 # DTB read access violations |
| 448system.cpu.dtb.read_accesses 766068 # DTB read accesses 449system.cpu.dtb.write_hits 6385066 # DTB write hits 450system.cpu.dtb.write_misses 2311 # DTB write misses | 454system.cpu.dtb.read_accesses 766148 # DTB read accesses 455system.cpu.dtb.write_hits 6384867 # DTB write hits 456system.cpu.dtb.write_misses 2306 # DTB write misses |
| 451system.cpu.dtb.write_acv 159 # DTB write access violations | 457system.cpu.dtb.write_acv 159 # DTB write access violations |
| 452system.cpu.dtb.write_accesses 298441 # DTB write accesses 453system.cpu.dtb.data_hits 15623461 # DTB hits 454system.cpu.dtb.data_misses 20125 # DTB misses | 458system.cpu.dtb.write_accesses 298467 # DTB write accesses 459system.cpu.dtb.data_hits 15622691 # DTB hits 460system.cpu.dtb.data_misses 20110 # DTB misses |
| 455system.cpu.dtb.data_acv 370 # DTB access violations | 461system.cpu.dtb.data_acv 370 # DTB access violations |
| 456system.cpu.dtb.data_accesses 1064509 # DTB accesses 457system.cpu.itb.fetch_hits 4000795 # ITB hits 458system.cpu.itb.fetch_misses 6874 # ITB misses 459system.cpu.itb.fetch_acv 703 # ITB acv 460system.cpu.itb.fetch_accesses 4007669 # ITB accesses | 462system.cpu.dtb.data_accesses 1064615 # DTB accesses 463system.cpu.itb.fetch_hits 3999749 # ITB hits 464system.cpu.itb.fetch_misses 6851 # ITB misses 465system.cpu.itb.fetch_acv 647 # ITB acv 466system.cpu.itb.fetch_accesses 4006600 # ITB accesses |
| 461system.cpu.itb.read_hits 0 # DTB read hits 462system.cpu.itb.read_misses 0 # DTB read misses 463system.cpu.itb.read_acv 0 # DTB read access violations 464system.cpu.itb.read_accesses 0 # DTB read accesses 465system.cpu.itb.write_hits 0 # DTB write hits 466system.cpu.itb.write_misses 0 # DTB write misses 467system.cpu.itb.write_acv 0 # DTB write access violations 468system.cpu.itb.write_accesses 0 # DTB write accesses 469system.cpu.itb.data_hits 0 # DTB hits 470system.cpu.itb.data_misses 0 # DTB misses 471system.cpu.itb.data_acv 0 # DTB access violations 472system.cpu.itb.data_accesses 0 # DTB accesses | 467system.cpu.itb.read_hits 0 # DTB read hits 468system.cpu.itb.read_misses 0 # DTB read misses 469system.cpu.itb.read_acv 0 # DTB read access violations 470system.cpu.itb.read_accesses 0 # DTB read accesses 471system.cpu.itb.write_hits 0 # DTB write hits 472system.cpu.itb.write_misses 0 # DTB write misses 473system.cpu.itb.write_acv 0 # DTB write access violations 474system.cpu.itb.write_accesses 0 # DTB write accesses 475system.cpu.itb.data_hits 0 # DTB hits 476system.cpu.itb.data_misses 0 # DTB misses 477system.cpu.itb.data_acv 0 # DTB access violations 478system.cpu.itb.data_accesses 0 # DTB accesses |
| 473system.cpu.numCycles 176776474 # number of cpu cycles simulated | 479system.cpu.numCycles 174888375 # number of cpu cycles simulated |
| 474system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 475system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 480system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 481system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 476system.cpu.committedInsts 56122642 # Number of instructions committed 477system.cpu.committedOps 56122642 # Number of ops (including micro ops) committed 478system.cpu.discardedOps 2532635 # Number of ops (including micro ops) which were discarded before commit 479system.cpu.numFetchSuspends 5494 # Number of times Execute suspended instruction fetching 480system.cpu.quiesceCycles 3591582755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 481system.cpu.cpi 3.149825 # CPI: cycles per instruction 482system.cpu.ipc 0.317478 # IPC: instructions per cycle | 482system.cpu.committedInsts 56120453 # Number of instructions committed 483system.cpu.committedOps 56120453 # Number of ops (including micro ops) committed 484system.cpu.discardedOps 2530516 # Number of ops (including micro ops) which were discarded before commit 485system.cpu.numFetchSuspends 5527 # Number of times Execute suspended instruction fetching 486system.cpu.quiesceCycles 3591560318 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 487system.cpu.cpi 3.116304 # CPI: cycles per instruction 488system.cpu.ipc 0.320893 # IPC: instructions per cycle |
| 483system.cpu.kern.inst.arm 0 # number of arm instructions executed | 489system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 484system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed 485system.cpu.kern.inst.hwrei 211451 # number of hwrei instructions executed 486system.cpu.kern.ipl_count::0 74783 40.94% 40.94% # number of times we switched to this ipl | 490system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed 491system.cpu.kern.inst.hwrei 211459 # number of hwrei instructions executed 492system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl |
| 487system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl 488system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl | 493system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl 494system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl |
| 489system.cpu.kern.ipl_count::31 105851 57.95% 100.00% # number of times we switched to this ipl 490system.cpu.kern.ipl_count::total 182665 # number of times we switched to this ipl 491system.cpu.kern.ipl_good::0 73416 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 495system.cpu.kern.ipl_count::31 105855 57.95% 100.00% # number of times we switched to this ipl 496system.cpu.kern.ipl_count::total 182673 # number of times we switched to this ipl 497system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 492system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 493system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl | 498system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 499system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl |
| 494system.cpu.kern.ipl_good::31 73416 49.32% 100.00% # number of times we switched to this ipl from a different ipl 495system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl 496system.cpu.kern.ipl_ticks::0 1832860357500 97.33% 97.33% # number of cycles we spent at this ipl 497system.cpu.kern.ipl_ticks::21 80169000 0.00% 97.33% # number of cycles we spent at this ipl 498system.cpu.kern.ipl_ticks::22 672803000 0.04% 97.37% # number of cycles we spent at this ipl 499system.cpu.kern.ipl_ticks::31 49609630000 2.63% 100.00% # number of cycles we spent at this ipl 500system.cpu.kern.ipl_ticks::total 1883222959500 # number of cycles we spent at this ipl 501system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl | 500system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl 501system.cpu.kern.ipl_good::total 148871 # number of times we switched to this ipl from a different ipl 502system.cpu.kern.ipl_ticks::0 1832868777500 97.33% 97.33% # number of cycles we spent at this ipl 503system.cpu.kern.ipl_ticks::21 80360500 0.00% 97.33% # number of cycles we spent at this ipl 504system.cpu.kern.ipl_ticks::22 672864500 0.04% 97.37% # number of cycles we spent at this ipl 505system.cpu.kern.ipl_ticks::31 49601349000 2.63% 100.00% # number of cycles we spent at this ipl 506system.cpu.kern.ipl_ticks::total 1883223351500 # number of cycles we spent at this ipl 507system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl |
| 502system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 503system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 508system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 509system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 504system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl 505system.cpu.kern.ipl_used::total 0.814951 # fraction of swpipl calls that actually changed the ipl | 510system.cpu.kern.ipl_used::31 0.693590 # fraction of swpipl calls that actually changed the ipl 511system.cpu.kern.ipl_used::total 0.814959 # fraction of swpipl calls that actually changed the ipl |
| 506system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 507system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 508system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 509system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 510system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 511system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 512system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 513system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 536system.cpu.kern.syscall::total 326 # number of syscalls executed 537system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 538system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 539system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 540system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 541system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed 542system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 543system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 512system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 513system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 514system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 515system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 516system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 517system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 518system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 519system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 542system.cpu.kern.syscall::total 326 # number of syscalls executed 543system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 544system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 545system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 546system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 547system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed 548system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 549system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 544system.cpu.kern.callpal::swpipl 175508 91.23% 93.43% # number of callpals executed | 550system.cpu.kern.callpal::swpipl 175516 91.23% 93.43% # number of callpals executed |
| 545system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed 546system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 547system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 548system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 549system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 550system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed 551system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 552system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 551system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed 552system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 553system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 554system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 555system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 556system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed 557system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 558system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 553system.cpu.kern.callpal::total 192390 # number of callpals executed 554system.cpu.kern.mode_switch::kernel 5869 # number of protection mode switches | 559system.cpu.kern.callpal::total 192398 # number of callpals executed 560system.cpu.kern.mode_switch::kernel 5867 # number of protection mode switches |
| 555system.cpu.kern.mode_switch::user 1741 # number of protection mode switches | 561system.cpu.kern.mode_switch::user 1741 # number of protection mode switches |
| 556system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches | 562system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches |
| 557system.cpu.kern.mode_good::kernel 1910 558system.cpu.kern.mode_good::user 1741 559system.cpu.kern.mode_good::idle 169 | 563system.cpu.kern.mode_good::kernel 1910 564system.cpu.kern.mode_good::user 1741 565system.cpu.kern.mode_good::idle 169 |
| 560system.cpu.kern.mode_switch_good::kernel 0.325439 # fraction of useful protection mode switches | 566system.cpu.kern.mode_switch_good::kernel 0.325550 # fraction of useful protection mode switches |
| 561system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 567system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 562system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches | 568system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches |
| 563system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches | 569system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches |
| 564system.cpu.kern.mode_ticks::kernel 36245351000 1.92% 1.92% # number of ticks spent at the given mode 565system.cpu.kern.mode_ticks::user 4057630500 0.22% 2.14% # number of ticks spent at the given mode 566system.cpu.kern.mode_ticks::idle 1842919968000 97.86% 100.00% # number of ticks spent at the given mode | 570system.cpu.kern.mode_ticks::kernel 36222818500 1.92% 1.92% # number of ticks spent at the given mode 571system.cpu.kern.mode_ticks::user 4061127000 0.22% 2.14% # number of ticks spent at the given mode 572system.cpu.kern.mode_ticks::idle 1842939396000 97.86% 100.00% # number of ticks spent at the given mode |
| 567system.cpu.kern.swap_context 4175 # number of times the context was actually changed | 573system.cpu.kern.swap_context 4175 # number of times the context was actually changed |
| 568system.cpu.tickCycles 85798616 # Number of cycles that the object actually ticked 569system.cpu.idleCycles 90977858 # Total number of cycles that the object has spent stopped | 574system.cpu.tickCycles 83840328 # Number of cycles that the object actually ticked 575system.cpu.idleCycles 91048047 # Total number of cycles that the object has spent stopped |
| 570system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 571system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 572system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 573system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 574system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 575system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 576system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 577system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 593system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 594system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 595system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 596system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 597system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 598system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 599system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 600system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 576system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 577system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 578system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 579system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 580system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 581system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 582system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 583system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 599system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 600system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 601system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 602system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 603system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 604system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 605system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 606system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 601system.iobus.throughput 1436853 # Throughput (bytes/s) | |
| 602system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 603system.iobus.trans_dist::ReadResp 7103 # Transaction distribution | 607system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 608system.iobus.trans_dist::ReadResp 7103 # Transaction distribution |
| 604system.iobus.trans_dist::WriteReq 51169 # Transaction distribution | 609system.iobus.trans_dist::WriteReq 51170 # Transaction distribution |
| 605system.iobus.trans_dist::WriteResp 51170 # Transaction distribution | 610system.iobus.trans_dist::WriteResp 51170 # Transaction distribution |
| 606system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution | |
| 607system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes) 608system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 609system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 610system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 611system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 612system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 613system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 614system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 615system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 616system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 617system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 618system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 619system.iobus.pkt_count_system.bridge.master::total 33096 # Packet count per connected master and slave (bytes) 620system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 621system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 622system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes) | 611system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes) 612system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 613system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 614system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 615system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 616system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 617system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 618system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 619system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 620system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 621system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 622system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 623system.iobus.pkt_count_system.bridge.master::total 33096 # Packet count per connected master and slave (bytes) 624system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 625system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 626system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes) |
| 623system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.tot_pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.tot_pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.data_through_bus 2705916 # Total data (bytes) | 627system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes) 640system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 641system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 642system.iobus.pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes) |
| 640system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks) 641system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 642system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 643system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 644system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 645system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 646system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 647system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) --- 6 unchanged lines hidden (view full) --- 654system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 655system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 656system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 657system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 658system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 659system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 660system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 661system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 643system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks) 644system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 645system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 646system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 647system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 648system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 649system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 650system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) --- 6 unchanged lines hidden (view full) --- 657system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 658system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 659system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 660system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 662system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 663system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 664system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 662system.iobus.reqLayer29.occupancy 374409688 # Layer occupancy (ticks) | 665system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks) |
| 663system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 664system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 665system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 666system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks) 667system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 666system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 667system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 668system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 669system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks) 670system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 668system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks) | 671system.iobus.respLayer1.occupancy 42013751 # Layer occupancy (ticks) |
| 669system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 672system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 670system.cpu.icache.tags.replacements 1458007 # number of replacements 671system.cpu.icache.tags.tagsinuse 509.627041 # Cycle average of tags in use 672system.cpu.icache.tags.total_refs 18950160 # Total number of references to valid blocks. 673system.cpu.icache.tags.sampled_refs 1458518 # Sample count of references to valid blocks. 674system.cpu.icache.tags.avg_refs 12.992750 # Average number of references to valid blocks. 675system.cpu.icache.tags.warmup_cycle 31562091250 # Cycle when the warmup percentage was hit. 676system.cpu.icache.tags.occ_blocks::cpu.inst 509.627041 # Average occupied blocks per requestor | 673system.cpu.icache.tags.replacements 1457910 # number of replacements 674system.cpu.icache.tags.tagsinuse 509.626980 # Cycle average of tags in use 675system.cpu.icache.tags.total_refs 18940924 # Total number of references to valid blocks. 676system.cpu.icache.tags.sampled_refs 1458421 # Sample count of references to valid blocks. 677system.cpu.icache.tags.avg_refs 12.987281 # Average number of references to valid blocks. 678system.cpu.icache.tags.warmup_cycle 31560714250 # Cycle when the warmup percentage was hit. 679system.cpu.icache.tags.occ_blocks::cpu.inst 509.626980 # Average occupied blocks per requestor |
| 677system.cpu.icache.tags.occ_percent::cpu.inst 0.995365 # Average percentage of cache occupancy 678system.cpu.icache.tags.occ_percent::total 0.995365 # Average percentage of cache occupancy 679system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id | 680system.cpu.icache.tags.occ_percent::cpu.inst 0.995365 # Average percentage of cache occupancy 681system.cpu.icache.tags.occ_percent::total 0.995365 # Average percentage of cache occupancy 682system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id |
| 680system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 681system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 682system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id | 683system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 684system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 685system.cpu.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id |
| 683system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 686system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 684system.cpu.icache.tags.tag_accesses 21867553 # Number of tag accesses 685system.cpu.icache.tags.data_accesses 21867553 # Number of data accesses 686system.cpu.icache.ReadReq_hits::cpu.inst 18950163 # number of ReadReq hits 687system.cpu.icache.ReadReq_hits::total 18950163 # number of ReadReq hits 688system.cpu.icache.demand_hits::cpu.inst 18950163 # number of demand (read+write) hits 689system.cpu.icache.demand_hits::total 18950163 # number of demand (read+write) hits 690system.cpu.icache.overall_hits::cpu.inst 18950163 # number of overall hits 691system.cpu.icache.overall_hits::total 18950163 # number of overall hits 692system.cpu.icache.ReadReq_misses::cpu.inst 1458695 # number of ReadReq misses 693system.cpu.icache.ReadReq_misses::total 1458695 # number of ReadReq misses 694system.cpu.icache.demand_misses::cpu.inst 1458695 # number of demand (read+write) misses 695system.cpu.icache.demand_misses::total 1458695 # number of demand (read+write) misses 696system.cpu.icache.overall_misses::cpu.inst 1458695 # number of overall misses 697system.cpu.icache.overall_misses::total 1458695 # number of overall misses 698system.cpu.icache.ReadReq_miss_latency::cpu.inst 20021954296 # number of ReadReq miss cycles 699system.cpu.icache.ReadReq_miss_latency::total 20021954296 # number of ReadReq miss cycles 700system.cpu.icache.demand_miss_latency::cpu.inst 20021954296 # number of demand (read+write) miss cycles 701system.cpu.icache.demand_miss_latency::total 20021954296 # number of demand (read+write) miss cycles 702system.cpu.icache.overall_miss_latency::cpu.inst 20021954296 # number of overall miss cycles 703system.cpu.icache.overall_miss_latency::total 20021954296 # number of overall miss cycles 704system.cpu.icache.ReadReq_accesses::cpu.inst 20408858 # number of ReadReq accesses(hits+misses) 705system.cpu.icache.ReadReq_accesses::total 20408858 # number of ReadReq accesses(hits+misses) 706system.cpu.icache.demand_accesses::cpu.inst 20408858 # number of demand (read+write) accesses 707system.cpu.icache.demand_accesses::total 20408858 # number of demand (read+write) accesses 708system.cpu.icache.overall_accesses::cpu.inst 20408858 # number of overall (read+write) accesses 709system.cpu.icache.overall_accesses::total 20408858 # number of overall (read+write) accesses 710system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071474 # miss rate for ReadReq accesses 711system.cpu.icache.ReadReq_miss_rate::total 0.071474 # miss rate for ReadReq accesses 712system.cpu.icache.demand_miss_rate::cpu.inst 0.071474 # miss rate for demand accesses 713system.cpu.icache.demand_miss_rate::total 0.071474 # miss rate for demand accesses 714system.cpu.icache.overall_miss_rate::cpu.inst 0.071474 # miss rate for overall accesses 715system.cpu.icache.overall_miss_rate::total 0.071474 # miss rate for overall accesses 716system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.936057 # average ReadReq miss latency 717system.cpu.icache.ReadReq_avg_miss_latency::total 13725.936057 # average ReadReq miss latency 718system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency 719system.cpu.icache.demand_avg_miss_latency::total 13725.936057 # average overall miss latency 720system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency 721system.cpu.icache.overall_avg_miss_latency::total 13725.936057 # average overall miss latency | 687system.cpu.icache.tags.tag_accesses 21858119 # Number of tag accesses 688system.cpu.icache.tags.data_accesses 21858119 # Number of data accesses 689system.cpu.icache.ReadReq_hits::cpu.inst 18940927 # number of ReadReq hits 690system.cpu.icache.ReadReq_hits::total 18940927 # number of ReadReq hits 691system.cpu.icache.demand_hits::cpu.inst 18940927 # number of demand (read+write) hits 692system.cpu.icache.demand_hits::total 18940927 # number of demand (read+write) hits 693system.cpu.icache.overall_hits::cpu.inst 18940927 # number of overall hits 694system.cpu.icache.overall_hits::total 18940927 # number of overall hits 695system.cpu.icache.ReadReq_misses::cpu.inst 1458596 # number of ReadReq misses 696system.cpu.icache.ReadReq_misses::total 1458596 # number of ReadReq misses 697system.cpu.icache.demand_misses::cpu.inst 1458596 # number of demand (read+write) misses 698system.cpu.icache.demand_misses::total 1458596 # number of demand (read+write) misses 699system.cpu.icache.overall_misses::cpu.inst 1458596 # number of overall misses 700system.cpu.icache.overall_misses::total 1458596 # number of overall misses 701system.cpu.icache.ReadReq_miss_latency::cpu.inst 20022164568 # number of ReadReq miss cycles 702system.cpu.icache.ReadReq_miss_latency::total 20022164568 # number of ReadReq miss cycles 703system.cpu.icache.demand_miss_latency::cpu.inst 20022164568 # number of demand (read+write) miss cycles 704system.cpu.icache.demand_miss_latency::total 20022164568 # number of demand (read+write) miss cycles 705system.cpu.icache.overall_miss_latency::cpu.inst 20022164568 # number of overall miss cycles 706system.cpu.icache.overall_miss_latency::total 20022164568 # number of overall miss cycles 707system.cpu.icache.ReadReq_accesses::cpu.inst 20399523 # number of ReadReq accesses(hits+misses) 708system.cpu.icache.ReadReq_accesses::total 20399523 # number of ReadReq accesses(hits+misses) 709system.cpu.icache.demand_accesses::cpu.inst 20399523 # number of demand (read+write) accesses 710system.cpu.icache.demand_accesses::total 20399523 # number of demand (read+write) accesses 711system.cpu.icache.overall_accesses::cpu.inst 20399523 # number of overall (read+write) accesses 712system.cpu.icache.overall_accesses::total 20399523 # number of overall (read+write) accesses 713system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071501 # miss rate for ReadReq accesses 714system.cpu.icache.ReadReq_miss_rate::total 0.071501 # miss rate for ReadReq accesses 715system.cpu.icache.demand_miss_rate::cpu.inst 0.071501 # miss rate for demand accesses 716system.cpu.icache.demand_miss_rate::total 0.071501 # miss rate for demand accesses 717system.cpu.icache.overall_miss_rate::cpu.inst 0.071501 # miss rate for overall accesses 718system.cpu.icache.overall_miss_rate::total 0.071501 # miss rate for overall accesses 719system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.011844 # average ReadReq miss latency 720system.cpu.icache.ReadReq_avg_miss_latency::total 13727.011844 # average ReadReq miss latency 721system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency 722system.cpu.icache.demand_avg_miss_latency::total 13727.011844 # average overall miss latency 723system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency 724system.cpu.icache.overall_avg_miss_latency::total 13727.011844 # average overall miss latency |
| 722system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 723system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 724system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 725system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 726system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 727system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 728system.cpu.icache.fast_writes 0 # number of fast writes performed 729system.cpu.icache.cache_copies 0 # number of cache copies performed | 725system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 726system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 727system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 728system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 729system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 730system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 731system.cpu.icache.fast_writes 0 # number of fast writes performed 732system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 730system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458695 # number of ReadReq MSHR misses 731system.cpu.icache.ReadReq_mshr_misses::total 1458695 # number of ReadReq MSHR misses 732system.cpu.icache.demand_mshr_misses::cpu.inst 1458695 # number of demand (read+write) MSHR misses 733system.cpu.icache.demand_mshr_misses::total 1458695 # number of demand (read+write) MSHR misses 734system.cpu.icache.overall_mshr_misses::cpu.inst 1458695 # number of overall MSHR misses 735system.cpu.icache.overall_mshr_misses::total 1458695 # number of overall MSHR misses 736system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097209704 # number of ReadReq MSHR miss cycles 737system.cpu.icache.ReadReq_mshr_miss_latency::total 17097209704 # number of ReadReq MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097209704 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.demand_mshr_miss_latency::total 17097209704 # number of demand (read+write) MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097209704 # number of overall MSHR miss cycles 741system.cpu.icache.overall_mshr_miss_latency::total 17097209704 # number of overall MSHR miss cycles 742system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for ReadReq accesses 743system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071474 # mshr miss rate for ReadReq accesses 744system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for demand accesses 745system.cpu.icache.demand_mshr_miss_rate::total 0.071474 # mshr miss rate for demand accesses 746system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for overall accesses 747system.cpu.icache.overall_mshr_miss_rate::total 0.071474 # mshr miss rate for overall accesses 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11720.894158 # average ReadReq mshr miss latency 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11720.894158 # average ReadReq mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency | 733system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458596 # number of ReadReq MSHR misses 734system.cpu.icache.ReadReq_mshr_misses::total 1458596 # number of ReadReq MSHR misses 735system.cpu.icache.demand_mshr_misses::cpu.inst 1458596 # number of demand (read+write) MSHR misses 736system.cpu.icache.demand_mshr_misses::total 1458596 # number of demand (read+write) MSHR misses 737system.cpu.icache.overall_mshr_misses::cpu.inst 1458596 # number of overall MSHR misses 738system.cpu.icache.overall_mshr_misses::total 1458596 # number of overall MSHR misses 739system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097663432 # number of ReadReq MSHR miss cycles 740system.cpu.icache.ReadReq_mshr_miss_latency::total 17097663432 # number of ReadReq MSHR miss cycles 741system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097663432 # number of demand (read+write) MSHR miss cycles 742system.cpu.icache.demand_mshr_miss_latency::total 17097663432 # number of demand (read+write) MSHR miss cycles 743system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097663432 # number of overall MSHR miss cycles 744system.cpu.icache.overall_mshr_miss_latency::total 17097663432 # number of overall MSHR miss cycles 745system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for ReadReq accesses 746system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071501 # mshr miss rate for ReadReq accesses 747system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for demand accesses 748system.cpu.icache.demand_mshr_miss_rate::total 0.071501 # mshr miss rate for demand accesses 749system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for overall accesses 750system.cpu.icache.overall_mshr_miss_rate::total 0.071501 # mshr miss rate for overall accesses 751system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.000768 # average ReadReq mshr miss latency 752system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.000768 # average ReadReq mshr miss latency 753system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency 754system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency 755system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency 756system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency |
| 754system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 757system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 755system.cpu.toL2Bus.throughput 126942050 # Throughput (bytes/s) 756system.cpu.toL2Bus.trans_dist::ReadReq 2557486 # Transaction distribution 757system.cpu.toL2Bus.trans_dist::ReadResp 2557452 # Transaction distribution | 758system.cpu.toL2Bus.trans_dist::ReadReq 2557139 # Transaction distribution 759system.cpu.toL2Bus.trans_dist::ReadResp 2557106 # Transaction distribution |
| 758system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution 759system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution | 760system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution 761system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution |
| 760system.cpu.toL2Bus.trans_dist::Writeback 838282 # Transaction distribution 761system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41557 # Transaction distribution 762system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution 763system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution 764system.cpu.toL2Bus.trans_dist::ReadExReq 304264 # Transaction distribution 765system.cpu.toL2Bus.trans_dist::ReadExResp 304264 # Transaction distribution | 762system.cpu.toL2Bus.trans_dist::Writeback 838111 # Transaction distribution 763system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution 764system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution 765system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution 766system.cpu.toL2Bus.trans_dist::ReadExReq 304253 # Transaction distribution 767system.cpu.toL2Bus.trans_dist::ReadExResp 304253 # Transaction distribution |
| 766system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution | 768system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution |
| 767system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917328 # Packet count per connected master and slave (bytes) 768system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663485 # Packet count per connected master and slave (bytes) 769system.cpu.toL2Bus.pkt_count::total 6580813 # Packet count per connected master and slave (bytes) 770system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352512 # Cumulative packet size per connected master and slave (bytes) 771system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143044180 # Cumulative packet size per connected master and slave (bytes) 772system.cpu.toL2Bus.tot_pkt_size::total 236396692 # Cumulative packet size per connected master and slave (bytes) 773system.cpu.toL2Bus.data_through_bus 236386772 # Total data (bytes) 774system.cpu.toL2Bus.snoop_data_through_bus 2673536 # Total snoop data (bytes) 775system.cpu.toL2Bus.reqLayer0.occupancy 2697842997 # Layer occupancy (ticks) | 769system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917133 # Packet count per connected master and slave (bytes) 770system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662791 # Packet count per connected master and slave (bytes) 771system.cpu.toL2Bus.pkt_count::total 6579924 # Packet count per connected master and slave (bytes) 772system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93346368 # Cumulative packet size per connected master and slave (bytes) 773system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143016724 # Cumulative packet size per connected master and slave (bytes) 774system.cpu.toL2Bus.pkt_size::total 236363092 # Cumulative packet size per connected master and slave (bytes) 775system.cpu.toL2Bus.snoops 41947 # Total snoops (count) 776system.cpu.toL2Bus.snoop_fanout::samples 3734153 # Request fanout histogram 777system.cpu.toL2Bus.snoop_fanout::mean 1.011176 # Request fanout histogram 778system.cpu.toL2Bus.snoop_fanout::stdev 0.105123 # Request fanout histogram 779system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 780system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 781system.cpu.toL2Bus.snoop_fanout::1 3692421 98.88% 98.88% # Request fanout histogram 782system.cpu.toL2Bus.snoop_fanout::2 41732 1.12% 100.00% # Request fanout histogram 783system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 784system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 785system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 786system.cpu.toL2Bus.snoop_fanout::total 3734153 # Request fanout histogram 787system.cpu.toL2Bus.reqLayer0.occupancy 2697404999 # Layer occupancy (ticks) |
| 776system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 788system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 777system.cpu.toL2Bus.snoopLayer0.occupancy 232500 # Layer occupancy (ticks) | 789system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) |
| 778system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 790system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 779system.cpu.toL2Bus.respLayer0.occupancy 2191719796 # Layer occupancy (ticks) | 791system.cpu.toL2Bus.respLayer0.occupancy 2191548568 # Layer occupancy (ticks) |
| 780system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 792system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 781system.cpu.toL2Bus.respLayer1.occupancy 2194901157 # Layer occupancy (ticks) | 793system.cpu.toL2Bus.respLayer1.occupancy 2194491404 # Layer occupancy (ticks) |
| 782system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 794system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 783system.cpu.l2cache.tags.replacements 339412 # number of replacements 784system.cpu.l2cache.tags.tagsinuse 65326.749870 # Cycle average of tags in use 785system.cpu.l2cache.tags.total_refs 2981869 # Total number of references to valid blocks. 786system.cpu.l2cache.tags.sampled_refs 404575 # Sample count of references to valid blocks. 787system.cpu.l2cache.tags.avg_refs 7.370374 # Average number of references to valid blocks. | 795system.cpu.l2cache.tags.replacements 339424 # number of replacements 796system.cpu.l2cache.tags.tagsinuse 65327.181695 # Cycle average of tags in use 797system.cpu.l2cache.tags.total_refs 2981337 # Total number of references to valid blocks. 798system.cpu.l2cache.tags.sampled_refs 404586 # Sample count of references to valid blocks. 799system.cpu.l2cache.tags.avg_refs 7.368859 # Average number of references to valid blocks. |
| 788system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit. | 800system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit. |
| 789system.cpu.l2cache.tags.occ_blocks::writebacks 54484.622776 # Average occupied blocks per requestor 790system.cpu.l2cache.tags.occ_blocks::cpu.inst 10842.127094 # Average occupied blocks per requestor 791system.cpu.l2cache.tags.occ_percent::writebacks 0.831369 # Average percentage of cache occupancy 792system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165438 # Average percentage of cache occupancy 793system.cpu.l2cache.tags.occ_percent::total 0.996807 # Average percentage of cache occupancy 794system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id 795system.cpu.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 796system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1459 # Occupied blocks per task id | 801system.cpu.l2cache.tags.occ_blocks::writebacks 54492.967363 # Average occupied blocks per requestor 802system.cpu.l2cache.tags.occ_blocks::cpu.inst 10834.214332 # Average occupied blocks per requestor 803system.cpu.l2cache.tags.occ_percent::writebacks 0.831497 # Average percentage of cache occupancy 804system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165317 # Average percentage of cache occupancy 805system.cpu.l2cache.tags.occ_percent::total 0.996814 # Average percentage of cache occupancy 806system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 807system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 808system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1457 # Occupied blocks per task id |
| 797system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5166 # Occupied blocks per task id | 809system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5166 # Occupied blocks per task id |
| 798system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2777 # Occupied blocks per task id 799system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id 800system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 801system.cpu.l2cache.tags.tag_accesses 30252211 # Number of tag accesses 802system.cpu.l2cache.tags.data_accesses 30252211 # Number of data accesses 803system.cpu.l2cache.ReadReq_hits::cpu.inst 2261673 # number of ReadReq hits 804system.cpu.l2cache.ReadReq_hits::total 2261673 # number of ReadReq hits 805system.cpu.l2cache.Writeback_hits::writebacks 838282 # number of Writeback hits 806system.cpu.l2cache.Writeback_hits::total 838282 # number of Writeback hits | 810system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2781 # Occupied blocks per task id 811system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id 812system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id 813system.cpu.l2cache.tags.tag_accesses 30247978 # Number of tag accesses 814system.cpu.l2cache.tags.data_accesses 30247978 # Number of data accesses 815system.cpu.l2cache.ReadReq_hits::cpu.inst 2261320 # number of ReadReq hits 816system.cpu.l2cache.ReadReq_hits::total 2261320 # number of ReadReq hits 817system.cpu.l2cache.Writeback_hits::writebacks 838111 # number of Writeback hits 818system.cpu.l2cache.Writeback_hits::total 838111 # number of Writeback hits |
| 807system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits 808system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 819system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits 820system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 809system.cpu.l2cache.ReadExReq_hits::cpu.inst 187588 # number of ReadExReq hits 810system.cpu.l2cache.ReadExReq_hits::total 187588 # number of ReadExReq hits 811system.cpu.l2cache.demand_hits::cpu.inst 2449261 # number of demand (read+write) hits 812system.cpu.l2cache.demand_hits::total 2449261 # number of demand (read+write) hits 813system.cpu.l2cache.overall_hits::cpu.inst 2449261 # number of overall hits 814system.cpu.l2cache.overall_hits::total 2449261 # number of overall hits 815system.cpu.l2cache.ReadReq_misses::cpu.inst 288648 # number of ReadReq misses 816system.cpu.l2cache.ReadReq_misses::total 288648 # number of ReadReq misses 817system.cpu.l2cache.UpgradeReq_misses::cpu.inst 20 # number of UpgradeReq misses 818system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses 819system.cpu.l2cache.ReadExReq_misses::cpu.inst 116676 # number of ReadExReq misses 820system.cpu.l2cache.ReadExReq_misses::total 116676 # number of ReadExReq misses 821system.cpu.l2cache.demand_misses::cpu.inst 405324 # number of demand (read+write) misses 822system.cpu.l2cache.demand_misses::total 405324 # number of demand (read+write) misses 823system.cpu.l2cache.overall_misses::cpu.inst 405324 # number of overall misses 824system.cpu.l2cache.overall_misses::total 405324 # number of overall misses 825system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18909912500 # number of ReadReq miss cycles 826system.cpu.l2cache.ReadReq_miss_latency::total 18909912500 # number of ReadReq miss cycles | 821system.cpu.l2cache.ReadExReq_hits::cpu.inst 187575 # number of ReadExReq hits 822system.cpu.l2cache.ReadExReq_hits::total 187575 # number of ReadExReq hits 823system.cpu.l2cache.demand_hits::cpu.inst 2448895 # number of demand (read+write) hits 824system.cpu.l2cache.demand_hits::total 2448895 # number of demand (read+write) hits 825system.cpu.l2cache.overall_hits::cpu.inst 2448895 # number of overall hits 826system.cpu.l2cache.overall_hits::total 2448895 # number of overall hits 827system.cpu.l2cache.ReadReq_misses::cpu.inst 288657 # number of ReadReq misses 828system.cpu.l2cache.ReadReq_misses::total 288657 # number of ReadReq misses 829system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses 830system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses 831system.cpu.l2cache.ReadExReq_misses::cpu.inst 116678 # number of ReadExReq misses 832system.cpu.l2cache.ReadExReq_misses::total 116678 # number of ReadExReq misses 833system.cpu.l2cache.demand_misses::cpu.inst 405335 # number of demand (read+write) misses 834system.cpu.l2cache.demand_misses::total 405335 # number of demand (read+write) misses 835system.cpu.l2cache.overall_misses::cpu.inst 405335 # number of overall misses 836system.cpu.l2cache.overall_misses::total 405335 # number of overall misses 837system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18918279000 # number of ReadReq miss cycles 838system.cpu.l2cache.ReadReq_miss_latency::total 18918279000 # number of ReadReq miss cycles |
| 827system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 115495 # number of UpgradeReq miss cycles 828system.cpu.l2cache.UpgradeReq_miss_latency::total 115495 # number of UpgradeReq miss cycles | 839system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 115495 # number of UpgradeReq miss cycles 840system.cpu.l2cache.UpgradeReq_miss_latency::total 115495 # number of UpgradeReq miss cycles |
| 829system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8088441363 # number of ReadExReq miss cycles 830system.cpu.l2cache.ReadExReq_miss_latency::total 8088441363 # number of ReadExReq miss cycles 831system.cpu.l2cache.demand_miss_latency::cpu.inst 26998353863 # number of demand (read+write) miss cycles 832system.cpu.l2cache.demand_miss_latency::total 26998353863 # number of demand (read+write) miss cycles 833system.cpu.l2cache.overall_miss_latency::cpu.inst 26998353863 # number of overall miss cycles 834system.cpu.l2cache.overall_miss_latency::total 26998353863 # number of overall miss cycles 835system.cpu.l2cache.ReadReq_accesses::cpu.inst 2550321 # number of ReadReq accesses(hits+misses) 836system.cpu.l2cache.ReadReq_accesses::total 2550321 # number of ReadReq accesses(hits+misses) 837system.cpu.l2cache.Writeback_accesses::writebacks 838282 # number of Writeback accesses(hits+misses) 838system.cpu.l2cache.Writeback_accesses::total 838282 # number of Writeback accesses(hits+misses) 839system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 24 # number of UpgradeReq accesses(hits+misses) 840system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses) 841system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304264 # number of ReadExReq accesses(hits+misses) 842system.cpu.l2cache.ReadExReq_accesses::total 304264 # number of ReadExReq accesses(hits+misses) 843system.cpu.l2cache.demand_accesses::cpu.inst 2854585 # number of demand (read+write) accesses 844system.cpu.l2cache.demand_accesses::total 2854585 # number of demand (read+write) accesses 845system.cpu.l2cache.overall_accesses::cpu.inst 2854585 # number of overall (read+write) accesses 846system.cpu.l2cache.overall_accesses::total 2854585 # number of overall (read+write) accesses 847system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113181 # miss rate for ReadReq accesses 848system.cpu.l2cache.ReadReq_miss_rate::total 0.113181 # miss rate for ReadReq accesses 849system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.833333 # miss rate for UpgradeReq accesses 850system.cpu.l2cache.UpgradeReq_miss_rate::total 0.833333 # miss rate for UpgradeReq accesses 851system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383470 # miss rate for ReadExReq accesses 852system.cpu.l2cache.ReadExReq_miss_rate::total 0.383470 # miss rate for ReadExReq accesses 853system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141991 # miss rate for demand accesses 854system.cpu.l2cache.demand_miss_rate::total 0.141991 # miss rate for demand accesses 855system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141991 # miss rate for overall accesses 856system.cpu.l2cache.overall_miss_rate::total 0.141991 # miss rate for overall accesses 857system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65512.016366 # average ReadReq miss latency 858system.cpu.l2cache.ReadReq_avg_miss_latency::total 65512.016366 # average ReadReq miss latency 859system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 5774.750000 # average UpgradeReq miss latency 860system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5774.750000 # average UpgradeReq miss latency 861system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69323.951481 # average ReadExReq miss latency 862system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69323.951481 # average ReadExReq miss latency 863system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66609.314679 # average overall miss latency 864system.cpu.l2cache.demand_avg_miss_latency::total 66609.314679 # average overall miss latency 865system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66609.314679 # average overall miss latency 866system.cpu.l2cache.overall_avg_miss_latency::total 66609.314679 # average overall miss latency | 841system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8105432113 # number of ReadExReq miss cycles 842system.cpu.l2cache.ReadExReq_miss_latency::total 8105432113 # number of ReadExReq miss cycles 843system.cpu.l2cache.demand_miss_latency::cpu.inst 27023711113 # number of demand (read+write) miss cycles 844system.cpu.l2cache.demand_miss_latency::total 27023711113 # number of demand (read+write) miss cycles 845system.cpu.l2cache.overall_miss_latency::cpu.inst 27023711113 # number of overall miss cycles 846system.cpu.l2cache.overall_miss_latency::total 27023711113 # number of overall miss cycles 847system.cpu.l2cache.ReadReq_accesses::cpu.inst 2549977 # number of ReadReq accesses(hits+misses) 848system.cpu.l2cache.ReadReq_accesses::total 2549977 # number of ReadReq accesses(hits+misses) 849system.cpu.l2cache.Writeback_accesses::writebacks 838111 # number of Writeback accesses(hits+misses) 850system.cpu.l2cache.Writeback_accesses::total 838111 # number of Writeback accesses(hits+misses) 851system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses) 852system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) 853system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304253 # number of ReadExReq accesses(hits+misses) 854system.cpu.l2cache.ReadExReq_accesses::total 304253 # number of ReadExReq accesses(hits+misses) 855system.cpu.l2cache.demand_accesses::cpu.inst 2854230 # number of demand (read+write) accesses 856system.cpu.l2cache.demand_accesses::total 2854230 # number of demand (read+write) accesses 857system.cpu.l2cache.overall_accesses::cpu.inst 2854230 # number of overall (read+write) accesses 858system.cpu.l2cache.overall_accesses::total 2854230 # number of overall (read+write) accesses 859system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113200 # miss rate for ReadReq accesses 860system.cpu.l2cache.ReadReq_miss_rate::total 0.113200 # miss rate for ReadReq accesses 861system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses 862system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses 863system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383490 # miss rate for ReadExReq accesses 864system.cpu.l2cache.ReadExReq_miss_rate::total 0.383490 # miss rate for ReadExReq accesses 865system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142012 # miss rate for demand accesses 866system.cpu.l2cache.demand_miss_rate::total 0.142012 # miss rate for demand accesses 867system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142012 # miss rate for overall accesses 868system.cpu.l2cache.overall_miss_rate::total 0.142012 # miss rate for overall accesses 869system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65538.958002 # average ReadReq miss latency 870system.cpu.l2cache.ReadReq_avg_miss_latency::total 65538.958002 # average ReadReq miss latency 871system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 6793.823529 # average UpgradeReq miss latency 872system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6793.823529 # average UpgradeReq miss latency 873system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69468.384040 # average ReadExReq miss latency 874system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69468.384040 # average ReadExReq miss latency 875system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency 876system.cpu.l2cache.demand_avg_miss_latency::total 66670.065780 # average overall miss latency 877system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency 878system.cpu.l2cache.overall_avg_miss_latency::total 66670.065780 # average overall miss latency |
| 867system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 868system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 869system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 870system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 871system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 872system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 873system.cpu.l2cache.fast_writes 0 # number of fast writes performed 874system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 879system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 880system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 881system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 882system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 883system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 884system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 885system.cpu.l2cache.fast_writes 0 # number of fast writes performed 886system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 875system.cpu.l2cache.writebacks::writebacks 76605 # number of writebacks 876system.cpu.l2cache.writebacks::total 76605 # number of writebacks 877system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288648 # number of ReadReq MSHR misses 878system.cpu.l2cache.ReadReq_mshr_misses::total 288648 # number of ReadReq MSHR misses 879system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 20 # number of UpgradeReq MSHR misses 880system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses 881system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116676 # number of ReadExReq MSHR misses 882system.cpu.l2cache.ReadExReq_mshr_misses::total 116676 # number of ReadExReq MSHR misses 883system.cpu.l2cache.demand_mshr_misses::cpu.inst 405324 # number of demand (read+write) MSHR misses 884system.cpu.l2cache.demand_mshr_misses::total 405324 # number of demand (read+write) MSHR misses 885system.cpu.l2cache.overall_mshr_misses::cpu.inst 405324 # number of overall MSHR misses 886system.cpu.l2cache.overall_mshr_misses::total 405324 # number of overall MSHR misses 887system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15301161000 # number of ReadReq MSHR miss cycles 888system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15301161000 # number of ReadReq MSHR miss cycles 889system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 201018 # number of UpgradeReq MSHR miss cycles 890system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 201018 # number of UpgradeReq MSHR miss cycles 891system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6587763637 # number of ReadExReq MSHR miss cycles 892system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6587763637 # number of ReadExReq MSHR miss cycles 893system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21888924637 # number of demand (read+write) MSHR miss cycles 894system.cpu.l2cache.demand_mshr_miss_latency::total 21888924637 # number of demand (read+write) MSHR miss cycles 895system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21888924637 # number of overall MSHR miss cycles 896system.cpu.l2cache.overall_mshr_miss_latency::total 21888924637 # number of overall MSHR miss cycles 897system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333222000 # number of ReadReq MSHR uncacheable cycles 898system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333222000 # number of ReadReq MSHR uncacheable cycles 899system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887374000 # number of WriteReq MSHR uncacheable cycles 900system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887374000 # number of WriteReq MSHR uncacheable cycles 901system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3220596000 # number of overall MSHR uncacheable cycles 902system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3220596000 # number of overall MSHR uncacheable cycles 903system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113181 # mshr miss rate for ReadReq accesses 904system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113181 # mshr miss rate for ReadReq accesses 905system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.833333 # mshr miss rate for UpgradeReq accesses 906system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses 907system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383470 # mshr miss rate for ReadExReq accesses 908system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383470 # mshr miss rate for ReadExReq accesses 909system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141991 # mshr miss rate for demand accesses 910system.cpu.l2cache.demand_mshr_miss_rate::total 0.141991 # mshr miss rate for demand accesses 911system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141991 # mshr miss rate for overall accesses 912system.cpu.l2cache.overall_mshr_miss_rate::total 0.141991 # mshr miss rate for overall accesses 913system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53009.759292 # average ReadReq mshr miss latency 914system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53009.759292 # average ReadReq mshr miss latency 915system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10050.900000 # average UpgradeReq mshr miss latency 916system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10050.900000 # average UpgradeReq mshr miss latency 917system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56462.028498 # average ReadExReq mshr miss latency 918system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56462.028498 # average ReadExReq mshr miss latency 919system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54003.524679 # average overall mshr miss latency 920system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54003.524679 # average overall mshr miss latency 921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54003.524679 # average overall mshr miss latency 922system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54003.524679 # average overall mshr miss latency | 887system.cpu.l2cache.writebacks::writebacks 76624 # number of writebacks 888system.cpu.l2cache.writebacks::total 76624 # number of writebacks 889system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288657 # number of ReadReq MSHR misses 890system.cpu.l2cache.ReadReq_mshr_misses::total 288657 # number of ReadReq MSHR misses 891system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses 892system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses 893system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116678 # number of ReadExReq MSHR misses 894system.cpu.l2cache.ReadExReq_mshr_misses::total 116678 # number of ReadExReq MSHR misses 895system.cpu.l2cache.demand_mshr_misses::cpu.inst 405335 # number of demand (read+write) MSHR misses 896system.cpu.l2cache.demand_mshr_misses::total 405335 # number of demand (read+write) MSHR misses 897system.cpu.l2cache.overall_mshr_misses::cpu.inst 405335 # number of overall MSHR misses 898system.cpu.l2cache.overall_mshr_misses::total 405335 # number of overall MSHR misses 899system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15309425000 # number of ReadReq MSHR miss cycles 900system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15309425000 # number of ReadReq MSHR miss cycles 901system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 170516 # number of UpgradeReq MSHR miss cycles 902system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 170516 # number of UpgradeReq MSHR miss cycles 903system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6604759387 # number of ReadExReq MSHR miss cycles 904system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6604759387 # number of ReadExReq MSHR miss cycles 905system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21914184387 # number of demand (read+write) MSHR miss cycles 906system.cpu.l2cache.demand_mshr_miss_latency::total 21914184387 # number of demand (read+write) MSHR miss cycles 907system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21914184387 # number of overall MSHR miss cycles 908system.cpu.l2cache.overall_mshr_miss_latency::total 21914184387 # number of overall MSHR miss cycles 909system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333304000 # number of ReadReq MSHR uncacheable cycles 910system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333304000 # number of ReadReq MSHR uncacheable cycles 911system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1888377500 # number of WriteReq MSHR uncacheable cycles 912system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1888377500 # number of WriteReq MSHR uncacheable cycles 913system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221681500 # number of overall MSHR uncacheable cycles 914system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221681500 # number of overall MSHR uncacheable cycles 915system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113200 # mshr miss rate for ReadReq accesses 916system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113200 # mshr miss rate for ReadReq accesses 917system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses 918system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses 919system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383490 # mshr miss rate for ReadExReq accesses 920system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383490 # mshr miss rate for ReadExReq accesses 921system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for demand accesses 922system.cpu.l2cache.demand_mshr_miss_rate::total 0.142012 # mshr miss rate for demand accesses 923system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for overall accesses 924system.cpu.l2cache.overall_mshr_miss_rate::total 0.142012 # mshr miss rate for overall accesses 925system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53036.735641 # average ReadReq mshr miss latency 926system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53036.735641 # average ReadReq mshr miss latency 927system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10030.352941 # average UpgradeReq mshr miss latency 928system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.352941 # average UpgradeReq mshr miss latency 929system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56606.724378 # average ReadExReq mshr miss latency 930system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56606.724378 # average ReadExReq mshr miss latency 931system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency 932system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency 933system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency 934system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency |
| 923system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 924system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 925system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 926system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 927system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 928system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 929system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 935system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 936system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 937system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 938system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 939system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 940system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 941system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 930system.cpu.dcache.tags.replacements 1395422 # number of replacements | 942system.cpu.dcache.tags.replacements 1395163 # number of replacements |
| 931system.cpu.dcache.tags.tagsinuse 511.982303 # Cycle average of tags in use | 943system.cpu.dcache.tags.tagsinuse 511.982303 # Cycle average of tags in use |
| 932system.cpu.dcache.tags.total_refs 13764943 # Total number of references to valid blocks. 933system.cpu.dcache.tags.sampled_refs 1395934 # Sample count of references to valid blocks. 934system.cpu.dcache.tags.avg_refs 9.860741 # Average number of references to valid blocks. | 944system.cpu.dcache.tags.total_refs 13764370 # Total number of references to valid blocks. 945system.cpu.dcache.tags.sampled_refs 1395675 # Sample count of references to valid blocks. 946system.cpu.dcache.tags.avg_refs 9.862160 # Average number of references to valid blocks. |
| 935system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit. 936system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982303 # Average occupied blocks per requestor 937system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy 938system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy 939system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 947system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit. 948system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982303 # Average occupied blocks per requestor 949system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy 950system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy 951system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 940system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id 941system.cpu.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id | 952system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 953system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id |
| 942system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 943system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 954system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 955system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 944system.cpu.dcache.tags.tag_accesses 63626016 # Number of tag accesses 945system.cpu.dcache.tags.data_accesses 63626016 # Number of data accesses 946system.cpu.dcache.ReadReq_hits::cpu.inst 7806784 # number of ReadReq hits 947system.cpu.dcache.ReadReq_hits::total 7806784 # number of ReadReq hits 948system.cpu.dcache.WriteReq_hits::cpu.inst 5576432 # number of WriteReq hits 949system.cpu.dcache.WriteReq_hits::total 5576432 # number of WriteReq hits 950system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182707 # number of LoadLockedReq hits 951system.cpu.dcache.LoadLockedReq_hits::total 182707 # number of LoadLockedReq hits 952system.cpu.dcache.StoreCondReq_hits::cpu.inst 198983 # number of StoreCondReq hits 953system.cpu.dcache.StoreCondReq_hits::total 198983 # number of StoreCondReq hits 954system.cpu.dcache.demand_hits::cpu.inst 13383216 # number of demand (read+write) hits 955system.cpu.dcache.demand_hits::total 13383216 # number of demand (read+write) hits 956system.cpu.dcache.overall_hits::cpu.inst 13383216 # number of overall hits 957system.cpu.dcache.overall_hits::total 13383216 # number of overall hits 958system.cpu.dcache.ReadReq_misses::cpu.inst 1201616 # number of ReadReq misses 959system.cpu.dcache.ReadReq_misses::total 1201616 # number of ReadReq misses | 956system.cpu.dcache.tags.tag_accesses 63622669 # Number of tag accesses 957system.cpu.dcache.tags.data_accesses 63622669 # Number of data accesses 958system.cpu.dcache.ReadReq_hits::cpu.inst 7806418 # number of ReadReq hits 959system.cpu.dcache.ReadReq_hits::total 7806418 # number of ReadReq hits 960system.cpu.dcache.WriteReq_hits::cpu.inst 5576177 # number of WriteReq hits 961system.cpu.dcache.WriteReq_hits::total 5576177 # number of WriteReq hits 962system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182756 # number of LoadLockedReq hits 963system.cpu.dcache.LoadLockedReq_hits::total 182756 # number of LoadLockedReq hits 964system.cpu.dcache.StoreCondReq_hits::cpu.inst 198986 # number of StoreCondReq hits 965system.cpu.dcache.StoreCondReq_hits::total 198986 # number of StoreCondReq hits 966system.cpu.dcache.demand_hits::cpu.inst 13382595 # number of demand (read+write) hits 967system.cpu.dcache.demand_hits::total 13382595 # number of demand (read+write) hits 968system.cpu.dcache.overall_hits::cpu.inst 13382595 # number of overall hits 969system.cpu.dcache.overall_hits::total 13382595 # number of overall hits 970system.cpu.dcache.ReadReq_misses::cpu.inst 1201460 # number of ReadReq misses 971system.cpu.dcache.ReadReq_misses::total 1201460 # number of ReadReq misses |
| 960system.cpu.dcache.WriteReq_misses::cpu.inst 573699 # number of WriteReq misses 961system.cpu.dcache.WriteReq_misses::total 573699 # number of WriteReq misses | 972system.cpu.dcache.WriteReq_misses::cpu.inst 573699 # number of WriteReq misses 973system.cpu.dcache.WriteReq_misses::total 573699 # number of WriteReq misses |
| 962system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17299 # number of LoadLockedReq misses 963system.cpu.dcache.LoadLockedReq_misses::total 17299 # number of LoadLockedReq misses 964system.cpu.dcache.demand_misses::cpu.inst 1775315 # number of demand (read+write) misses 965system.cpu.dcache.demand_misses::total 1775315 # number of demand (read+write) misses 966system.cpu.dcache.overall_misses::cpu.inst 1775315 # number of overall misses 967system.cpu.dcache.overall_misses::total 1775315 # number of overall misses 968system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31018318500 # number of ReadReq miss cycles 969system.cpu.dcache.ReadReq_miss_latency::total 31018318500 # number of ReadReq miss cycles 970system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20748316044 # number of WriteReq miss cycles 971system.cpu.dcache.WriteReq_miss_latency::total 20748316044 # number of WriteReq miss cycles 972system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231689250 # number of LoadLockedReq miss cycles 973system.cpu.dcache.LoadLockedReq_miss_latency::total 231689250 # number of LoadLockedReq miss cycles 974system.cpu.dcache.demand_miss_latency::cpu.inst 51766634544 # number of demand (read+write) miss cycles 975system.cpu.dcache.demand_miss_latency::total 51766634544 # number of demand (read+write) miss cycles 976system.cpu.dcache.overall_miss_latency::cpu.inst 51766634544 # number of overall miss cycles 977system.cpu.dcache.overall_miss_latency::total 51766634544 # number of overall miss cycles 978system.cpu.dcache.ReadReq_accesses::cpu.inst 9008400 # number of ReadReq accesses(hits+misses) 979system.cpu.dcache.ReadReq_accesses::total 9008400 # number of ReadReq accesses(hits+misses) 980system.cpu.dcache.WriteReq_accesses::cpu.inst 6150131 # number of WriteReq accesses(hits+misses) 981system.cpu.dcache.WriteReq_accesses::total 6150131 # number of WriteReq accesses(hits+misses) 982system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200006 # number of LoadLockedReq accesses(hits+misses) 983system.cpu.dcache.LoadLockedReq_accesses::total 200006 # number of LoadLockedReq accesses(hits+misses) 984system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198983 # number of StoreCondReq accesses(hits+misses) 985system.cpu.dcache.StoreCondReq_accesses::total 198983 # number of StoreCondReq accesses(hits+misses) 986system.cpu.dcache.demand_accesses::cpu.inst 15158531 # number of demand (read+write) accesses 987system.cpu.dcache.demand_accesses::total 15158531 # number of demand (read+write) accesses 988system.cpu.dcache.overall_accesses::cpu.inst 15158531 # number of overall (read+write) accesses 989system.cpu.dcache.overall_accesses::total 15158531 # number of overall (read+write) accesses 990system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133388 # miss rate for ReadReq accesses 991system.cpu.dcache.ReadReq_miss_rate::total 0.133388 # miss rate for ReadReq accesses 992system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093282 # miss rate for WriteReq accesses 993system.cpu.dcache.WriteReq_miss_rate::total 0.093282 # miss rate for WriteReq accesses 994system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086492 # miss rate for LoadLockedReq accesses 995system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086492 # miss rate for LoadLockedReq accesses 996system.cpu.dcache.demand_miss_rate::cpu.inst 0.117117 # miss rate for demand accesses 997system.cpu.dcache.demand_miss_rate::total 0.117117 # miss rate for demand accesses 998system.cpu.dcache.overall_miss_rate::cpu.inst 0.117117 # miss rate for overall accesses 999system.cpu.dcache.overall_miss_rate::total 0.117117 # miss rate for overall accesses 1000system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25813.836117 # average ReadReq miss latency 1001system.cpu.dcache.ReadReq_avg_miss_latency::total 25813.836117 # average ReadReq miss latency 1002system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36165.857085 # average WriteReq miss latency 1003system.cpu.dcache.WriteReq_avg_miss_latency::total 36165.857085 # average WriteReq miss latency 1004system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13393.216371 # average LoadLockedReq miss latency 1005system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13393.216371 # average LoadLockedReq miss latency 1006system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency 1007system.cpu.dcache.demand_avg_miss_latency::total 29159.126433 # average overall miss latency 1008system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency 1009system.cpu.dcache.overall_avg_miss_latency::total 29159.126433 # average overall miss latency | 974system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17252 # number of LoadLockedReq misses 975system.cpu.dcache.LoadLockedReq_misses::total 17252 # number of LoadLockedReq misses 976system.cpu.dcache.demand_misses::cpu.inst 1775159 # number of demand (read+write) misses 977system.cpu.dcache.demand_misses::total 1775159 # number of demand (read+write) misses 978system.cpu.dcache.overall_misses::cpu.inst 1775159 # number of overall misses 979system.cpu.dcache.overall_misses::total 1775159 # number of overall misses 980system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31026314750 # number of ReadReq miss cycles 981system.cpu.dcache.ReadReq_miss_latency::total 31026314750 # number of ReadReq miss cycles 982system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20775588791 # number of WriteReq miss cycles 983system.cpu.dcache.WriteReq_miss_latency::total 20775588791 # number of WriteReq miss cycles 984system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 230892000 # number of LoadLockedReq miss cycles 985system.cpu.dcache.LoadLockedReq_miss_latency::total 230892000 # number of LoadLockedReq miss cycles 986system.cpu.dcache.demand_miss_latency::cpu.inst 51801903541 # number of demand (read+write) miss cycles 987system.cpu.dcache.demand_miss_latency::total 51801903541 # number of demand (read+write) miss cycles 988system.cpu.dcache.overall_miss_latency::cpu.inst 51801903541 # number of overall miss cycles 989system.cpu.dcache.overall_miss_latency::total 51801903541 # number of overall miss cycles 990system.cpu.dcache.ReadReq_accesses::cpu.inst 9007878 # number of ReadReq accesses(hits+misses) 991system.cpu.dcache.ReadReq_accesses::total 9007878 # number of ReadReq accesses(hits+misses) 992system.cpu.dcache.WriteReq_accesses::cpu.inst 6149876 # number of WriteReq accesses(hits+misses) 993system.cpu.dcache.WriteReq_accesses::total 6149876 # number of WriteReq accesses(hits+misses) 994system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200008 # number of LoadLockedReq accesses(hits+misses) 995system.cpu.dcache.LoadLockedReq_accesses::total 200008 # number of LoadLockedReq accesses(hits+misses) 996system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198986 # number of StoreCondReq accesses(hits+misses) 997system.cpu.dcache.StoreCondReq_accesses::total 198986 # number of StoreCondReq accesses(hits+misses) 998system.cpu.dcache.demand_accesses::cpu.inst 15157754 # number of demand (read+write) accesses 999system.cpu.dcache.demand_accesses::total 15157754 # number of demand (read+write) accesses 1000system.cpu.dcache.overall_accesses::cpu.inst 15157754 # number of overall (read+write) accesses 1001system.cpu.dcache.overall_accesses::total 15157754 # number of overall (read+write) accesses 1002system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133379 # miss rate for ReadReq accesses 1003system.cpu.dcache.ReadReq_miss_rate::total 0.133379 # miss rate for ReadReq accesses 1004system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093286 # miss rate for WriteReq accesses 1005system.cpu.dcache.WriteReq_miss_rate::total 0.093286 # miss rate for WriteReq accesses 1006system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086257 # miss rate for LoadLockedReq accesses 1007system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086257 # miss rate for LoadLockedReq accesses 1008system.cpu.dcache.demand_miss_rate::cpu.inst 0.117112 # miss rate for demand accesses 1009system.cpu.dcache.demand_miss_rate::total 0.117112 # miss rate for demand accesses 1010system.cpu.dcache.overall_miss_rate::cpu.inst 0.117112 # miss rate for overall accesses 1011system.cpu.dcache.overall_miss_rate::total 0.117112 # miss rate for overall accesses 1012system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25823.843282 # average ReadReq miss latency 1013system.cpu.dcache.ReadReq_avg_miss_latency::total 25823.843282 # average ReadReq miss latency 1014system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36213.395511 # average WriteReq miss latency 1015system.cpu.dcache.WriteReq_avg_miss_latency::total 36213.395511 # average WriteReq miss latency 1016system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13383.491769 # average LoadLockedReq miss latency 1017system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13383.491769 # average LoadLockedReq miss latency 1018system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency 1019system.cpu.dcache.demand_avg_miss_latency::total 29181.556999 # average overall miss latency 1020system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency 1021system.cpu.dcache.overall_avg_miss_latency::total 29181.556999 # average overall miss latency |
| 1010system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1011system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1012system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1013system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1014system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1015system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1016system.cpu.dcache.fast_writes 0 # number of fast writes performed 1017system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1022system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1023system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1024system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1025system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1026system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1027system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1028system.cpu.dcache.fast_writes 0 # number of fast writes performed 1029system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1018system.cpu.dcache.writebacks::writebacks 838282 # number of writebacks 1019system.cpu.dcache.writebacks::total 838282 # number of writebacks 1020system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127187 # number of ReadReq MSHR hits 1021system.cpu.dcache.ReadReq_mshr_hits::total 127187 # number of ReadReq MSHR hits 1022system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269448 # number of WriteReq MSHR hits 1023system.cpu.dcache.WriteReq_mshr_hits::total 269448 # number of WriteReq MSHR hits | 1030system.cpu.dcache.writebacks::writebacks 838111 # number of writebacks 1031system.cpu.dcache.writebacks::total 838111 # number of writebacks 1032system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127232 # number of ReadReq MSHR hits 1033system.cpu.dcache.ReadReq_mshr_hits::total 127232 # number of ReadReq MSHR hits 1034system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269462 # number of WriteReq MSHR hits 1035system.cpu.dcache.WriteReq_mshr_hits::total 269462 # number of WriteReq MSHR hits |
| 1024system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits 1025system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits | 1036system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits 1037system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits |
| 1026system.cpu.dcache.demand_mshr_hits::cpu.inst 396635 # number of demand (read+write) MSHR hits 1027system.cpu.dcache.demand_mshr_hits::total 396635 # number of demand (read+write) MSHR hits 1028system.cpu.dcache.overall_mshr_hits::cpu.inst 396635 # number of overall MSHR hits 1029system.cpu.dcache.overall_mshr_hits::total 396635 # number of overall MSHR hits 1030system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074429 # number of ReadReq MSHR misses 1031system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses 1032system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304251 # number of WriteReq MSHR misses 1033system.cpu.dcache.WriteReq_mshr_misses::total 304251 # number of WriteReq MSHR misses 1034system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17296 # number of LoadLockedReq MSHR misses 1035system.cpu.dcache.LoadLockedReq_mshr_misses::total 17296 # number of LoadLockedReq MSHR misses 1036system.cpu.dcache.demand_mshr_misses::cpu.inst 1378680 # number of demand (read+write) MSHR misses 1037system.cpu.dcache.demand_mshr_misses::total 1378680 # number of demand (read+write) MSHR misses 1038system.cpu.dcache.overall_mshr_misses::cpu.inst 1378680 # number of overall MSHR misses 1039system.cpu.dcache.overall_mshr_misses::total 1378680 # number of overall MSHR misses 1040system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26906996250 # number of ReadReq MSHR miss cycles 1041system.cpu.dcache.ReadReq_mshr_miss_latency::total 26906996250 # number of ReadReq MSHR miss cycles 1042system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10272860843 # number of WriteReq MSHR miss cycles 1043system.cpu.dcache.WriteReq_mshr_miss_latency::total 10272860843 # number of WriteReq MSHR miss cycles 1044system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196930250 # number of LoadLockedReq MSHR miss cycles 1045system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196930250 # number of LoadLockedReq MSHR miss cycles 1046system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179857093 # number of demand (read+write) MSHR miss cycles 1047system.cpu.dcache.demand_mshr_miss_latency::total 37179857093 # number of demand (read+write) MSHR miss cycles 1048system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179857093 # number of overall MSHR miss cycles 1049system.cpu.dcache.overall_mshr_miss_latency::total 37179857093 # number of overall MSHR miss cycles 1050system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423313500 # number of ReadReq MSHR uncacheable cycles 1051system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423313500 # number of ReadReq MSHR uncacheable cycles 1052system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002790500 # number of WriteReq MSHR uncacheable cycles 1053system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002790500 # number of WriteReq MSHR uncacheable cycles 1054system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426104000 # number of overall MSHR uncacheable cycles 1055system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426104000 # number of overall MSHR uncacheable cycles 1056system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119270 # mshr miss rate for ReadReq accesses 1057system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119270 # mshr miss rate for ReadReq accesses 1058system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049471 # mshr miss rate for WriteReq accesses 1059system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses 1060system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086477 # mshr miss rate for LoadLockedReq accesses 1061system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086477 # mshr miss rate for LoadLockedReq accesses 1062system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for demand accesses 1063system.cpu.dcache.demand_mshr_miss_rate::total 0.090951 # mshr miss rate for demand accesses 1064system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for overall accesses 1065system.cpu.dcache.overall_mshr_miss_rate::total 0.090951 # mshr miss rate for overall accesses 1066system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25043.065898 # average ReadReq mshr miss latency 1067system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.065898 # average ReadReq mshr miss latency 1068system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33764.427538 # average WriteReq mshr miss latency 1069system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33764.427538 # average WriteReq mshr miss latency 1070system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11385.884019 # average LoadLockedReq mshr miss latency 1071system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11385.884019 # average LoadLockedReq mshr miss latency 1072system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency 1073system.cpu.dcache.demand_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency 1074system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency 1075system.cpu.dcache.overall_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency | 1038system.cpu.dcache.demand_mshr_hits::cpu.inst 396694 # number of demand (read+write) MSHR hits 1039system.cpu.dcache.demand_mshr_hits::total 396694 # number of demand (read+write) MSHR hits 1040system.cpu.dcache.overall_mshr_hits::cpu.inst 396694 # number of overall MSHR hits 1041system.cpu.dcache.overall_mshr_hits::total 396694 # number of overall MSHR hits 1042system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074228 # number of ReadReq MSHR misses 1043system.cpu.dcache.ReadReq_mshr_misses::total 1074228 # number of ReadReq MSHR misses 1044system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304237 # number of WriteReq MSHR misses 1045system.cpu.dcache.WriteReq_mshr_misses::total 304237 # number of WriteReq MSHR misses 1046system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17249 # number of LoadLockedReq MSHR misses 1047system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses 1048system.cpu.dcache.demand_mshr_misses::cpu.inst 1378465 # number of demand (read+write) MSHR misses 1049system.cpu.dcache.demand_mshr_misses::total 1378465 # number of demand (read+write) MSHR misses 1050system.cpu.dcache.overall_mshr_misses::cpu.inst 1378465 # number of overall MSHR misses 1051system.cpu.dcache.overall_mshr_misses::total 1378465 # number of overall MSHR misses 1052system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26911701750 # number of ReadReq MSHR miss cycles 1053system.cpu.dcache.ReadReq_mshr_miss_latency::total 26911701750 # number of ReadReq MSHR miss cycles 1054system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10289625346 # number of WriteReq MSHR miss cycles 1055system.cpu.dcache.WriteReq_mshr_miss_latency::total 10289625346 # number of WriteReq MSHR miss cycles 1056system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196226500 # number of LoadLockedReq MSHR miss cycles 1057system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196226500 # number of LoadLockedReq MSHR miss cycles 1058system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37201327096 # number of demand (read+write) MSHR miss cycles 1059system.cpu.dcache.demand_mshr_miss_latency::total 37201327096 # number of demand (read+write) MSHR miss cycles 1060system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37201327096 # number of overall MSHR miss cycles 1061system.cpu.dcache.overall_mshr_miss_latency::total 37201327096 # number of overall MSHR miss cycles 1062system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423395500 # number of ReadReq MSHR uncacheable cycles 1063system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423395500 # number of ReadReq MSHR uncacheable cycles 1064system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2003794000 # number of WriteReq MSHR uncacheable cycles 1065system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2003794000 # number of WriteReq MSHR uncacheable cycles 1066system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3427189500 # number of overall MSHR uncacheable cycles 1067system.cpu.dcache.overall_mshr_uncacheable_latency::total 3427189500 # number of overall MSHR uncacheable cycles 1068system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119254 # mshr miss rate for ReadReq accesses 1069system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119254 # mshr miss rate for ReadReq accesses 1070system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049470 # mshr miss rate for WriteReq accesses 1071system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses 1072system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086242 # mshr miss rate for LoadLockedReq accesses 1073system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086242 # mshr miss rate for LoadLockedReq accesses 1074system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for demand accesses 1075system.cpu.dcache.demand_mshr_miss_rate::total 0.090941 # mshr miss rate for demand accesses 1076system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for overall accesses 1077system.cpu.dcache.overall_mshr_miss_rate::total 0.090941 # mshr miss rate for overall accesses 1078system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25052.132089 # average ReadReq mshr miss latency 1079system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25052.132089 # average ReadReq mshr miss latency 1080system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33821.084700 # average WriteReq mshr miss latency 1081system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33821.084700 # average WriteReq mshr miss latency 1082system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11376.108760 # average LoadLockedReq mshr miss latency 1083system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.108760 # average LoadLockedReq mshr miss latency 1084system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency 1085system.cpu.dcache.demand_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency 1086system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency 1087system.cpu.dcache.overall_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency |
| 1076system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1077system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1078system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1079system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1080system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1081system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1082system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1083 1084---------- End Simulation Statistics ---------- | 1088system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1089system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1090system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1091system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1092system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1093system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1094system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1095 1096---------- End Simulation Statistics ---------- |