| stats.txt (10260:384d554cea8c) | stats.txt (10261:dc198e224a85) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3final_tick 1884223823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 4host_inst_rate 205086 # Simulator instruction rate (inst/s) 5host_mem_usage 329500 # Number of bytes of host memory used 6host_op_rate 205086 # Simulator op (including micro ops) rate (op/s) 7host_seconds 273.72 # Real time elapsed on the host 8host_tick_rate 6883774376 # Simulator tick rate (ticks/s) | 3sim_seconds 1.884209 # Number of seconds simulated 4sim_ticks 1884208734500 # Number of ticks simulated 5final_tick 1884208734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 9sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 10sim_insts 56136190 # Number of instructions simulated 11sim_ops 56136190 # Number of ops (including micro ops) simulated 12sim_seconds 1.884224 # Number of seconds simulated 13sim_ticks 1884223823500 # Number of ticks simulated | 7host_inst_rate 147223 # Simulator instruction rate (inst/s) 8host_op_rate 147223 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4942377286 # Simulator tick rate (ticks/s) 10host_mem_usage 320260 # Number of bytes of host memory used 11host_seconds 381.24 # Real time elapsed on the host 12sim_insts 56126572 # Number of instructions simulated 13sim_ops 56126572 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts |
| 14system.clk_domain.clock 1000 # Clock period in ticks | 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 25914048 # Number of bytes read from this memory 17system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28566400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 7560448 # Number of bytes written to this memory 22system.physmem.bytes_written::total 7560448 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 404907 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 446350 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 118132 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 118132 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 13753279 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::tsunami.ide 1407674 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 15160953 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 558749 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 558749 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 4012532 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 4012532 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 4012532 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 13753279 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::tsunami.ide 1407674 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 19173485 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 446350 # Number of read requests accepted 40system.physmem.writeReqs 118132 # Number of write requests accepted 41system.physmem.readBursts 446350 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 118132 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 28559040 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue 45system.physmem.bytesWritten 7558400 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 28566400 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 7560448 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 28089 # Per bank write bursts 52system.physmem.perBankRdBursts::1 28219 # Per bank write bursts 53system.physmem.perBankRdBursts::2 28571 # Per bank write bursts 54system.physmem.perBankRdBursts::3 28273 # Per bank write bursts 55system.physmem.perBankRdBursts::4 27775 # Per bank write bursts 56system.physmem.perBankRdBursts::5 27529 # Per bank write bursts 57system.physmem.perBankRdBursts::6 27274 # Per bank write bursts 58system.physmem.perBankRdBursts::7 26987 # Per bank write bursts 59system.physmem.perBankRdBursts::8 27827 # Per bank write bursts 60system.physmem.perBankRdBursts::9 27514 # Per bank write bursts 61system.physmem.perBankRdBursts::10 28065 # Per bank write bursts 62system.physmem.perBankRdBursts::11 27430 # Per bank write bursts 63system.physmem.perBankRdBursts::12 27510 # Per bank write bursts 64system.physmem.perBankRdBursts::13 28401 # Per bank write bursts 65system.physmem.perBankRdBursts::14 28311 # Per bank write bursts 66system.physmem.perBankRdBursts::15 28460 # Per bank write bursts 67system.physmem.perBankWrBursts::0 7814 # Per bank write bursts 68system.physmem.perBankWrBursts::1 7677 # Per bank write bursts 69system.physmem.perBankWrBursts::2 8054 # Per bank write bursts 70system.physmem.perBankWrBursts::3 7732 # Per bank write bursts 71system.physmem.perBankWrBursts::4 7319 # Per bank write bursts 72system.physmem.perBankWrBursts::5 6955 # Per bank write bursts 73system.physmem.perBankWrBursts::6 6788 # Per bank write bursts 74system.physmem.perBankWrBursts::7 6406 # Per bank write bursts 75system.physmem.perBankWrBursts::8 7235 # Per bank write bursts 76system.physmem.perBankWrBursts::9 6877 # Per bank write bursts 77system.physmem.perBankWrBursts::10 7390 # Per bank write bursts 78system.physmem.perBankWrBursts::11 6865 # Per bank write bursts 79system.physmem.perBankWrBursts::12 7046 # Per bank write bursts 80system.physmem.perBankWrBursts::13 8008 # Per bank write bursts 81system.physmem.perBankWrBursts::14 7991 # Per bank write bursts 82system.physmem.perBankWrBursts::15 7943 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 8 # Number of times write queue was full causing retry 85system.physmem.totGap 1884200137500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 446350 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 118132 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 402858 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 3909 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 2828 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 1301 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 2032 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 4354 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 3963 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 2519 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 2152 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 2122 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 2100 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 1643 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 1621 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 1890 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 1850 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 2123 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 1201 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 877 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 1024 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 1062 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4664 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 4781 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4804 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 4807 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 4824 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 4947 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5088 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5171 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5379 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5611 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5560 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5729 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5781 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5895 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5861 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5917 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 907 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 921 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 954 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 875 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 945 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 993 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 1067 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 976 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 1137 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 1161 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 1136 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 1209 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 1384 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 1615 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 1837 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 2004 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 1906 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 1810 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 1674 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 1668 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 1785 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 1617 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 827 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 369 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 27 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 65499 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 551.419716 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 340.219574 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 417.619626 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 14326 21.87% 21.87% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 10638 16.24% 38.11% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 5049 7.71% 45.82% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 3016 4.60% 50.43% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2484 3.79% 54.22% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 2116 3.23% 57.45% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1384 2.11% 59.56% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1595 2.44% 62.00% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 24891 38.00% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 65499 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 6964 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 64.074383 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 16.502018 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 2530.928651 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-8191 6961 99.96% 99.96% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 6964 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 6964 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.958644 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.733261 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 3.741198 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 5665 81.35% 81.35% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 36 0.52% 81.86% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 854 12.26% 94.13% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 55 0.79% 94.92% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 10 0.14% 95.06% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::21 13 0.19% 95.25% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::22 23 0.33% 95.58% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::23 94 1.35% 96.93% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::24 12 0.17% 97.10% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::25 41 0.59% 97.69% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::26 13 0.19% 97.87% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::27 17 0.24% 98.12% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28 13 0.19% 98.31% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::29 12 0.17% 98.48% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::30 3 0.04% 98.52% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::31 21 0.30% 98.82% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32 7 0.10% 98.92% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::33 2 0.03% 98.95% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::34 2 0.03% 98.98% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::35 1 0.01% 98.99% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::36 2 0.03% 99.02% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::37 3 0.04% 99.07% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::38 3 0.04% 99.11% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::39 2 0.03% 99.14% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::40 8 0.11% 99.25% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::41 7 0.10% 99.35% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::43 3 0.04% 99.40% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::44 1 0.01% 99.41% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::45 1 0.01% 99.43% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::46 1 0.01% 99.44% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::47 7 0.10% 99.54% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::48 2 0.03% 99.57% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::49 1 0.01% 99.58% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::50 1 0.01% 99.60% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::51 1 0.01% 99.61% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::52 4 0.06% 99.67% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::54 1 0.01% 99.68% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::56 9 0.13% 99.81% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::57 8 0.11% 99.93% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::58 4 0.06% 99.99% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::59 1 0.01% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 6964 # Writes before turning the bus around for reads 265system.physmem.totQLat 7297586750 # Total ticks spent queuing 266system.physmem.totMemAccLat 15664493000 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 2231175000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 16353.69 # Average queueing delay per DRAM burst 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 270system.physmem.avgMemAccLat 35103.69 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 15.16 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.15 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 22.97 # Average write queue length when enqueuing 281system.physmem.readRowHits 402726 # Number of row buffer hits during reads 282system.physmem.writeRowHits 96110 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 90.25 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 81.36 # Row buffer hit rate for writes 285system.physmem.avgGap 3337927.76 # Average gap between requests 286system.physmem.pageHitRate 88.39 # Row buffer hit rate, read and write combined 287system.physmem.memoryStateTime::IDLE 1774702818500 # Time in different power states 288system.physmem.memoryStateTime::REF 62917660000 # Time in different power states 289system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 290system.physmem.memoryStateTime::ACT 46582219000 # Time in different power states 291system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 292system.membus.throughput 19215856 # Throughput (bytes/s) 293system.membus.trans_dist::ReadReq 295757 # Transaction distribution 294system.membus.trans_dist::ReadResp 295741 # Transaction distribution 295system.membus.trans_dist::WriteReq 9619 # Transaction distribution 296system.membus.trans_dist::WriteResp 9619 # Transaction distribution 297system.membus.trans_dist::Writeback 118132 # Transaction distribution 298system.membus.trans_dist::UpgradeReq 156 # Transaction distribution 299system.membus.trans_dist::UpgradeResp 156 # Transaction distribution 300system.membus.trans_dist::ReadExReq 158094 # Transaction distribution 301system.membus.trans_dist::ReadExResp 158094 # Transaction distribution 302system.membus.trans_dist::BadAddressError 16 # Transaction distribution 303system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) 304system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887017 # Packet count per connected master and slave (bytes) 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920147 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) 308system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count::total 1044827 # Packet count per connected master and slave (bytes) 310system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30817728 # Cumulative packet size per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30862044 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) 315system.membus.tot_pkt_size::total 36171164 # Cumulative packet size per connected master and slave (bytes) 316system.membus.data_through_bus 36171164 # Total data (bytes) 317system.membus.snoop_data_through_bus 35520 # Total snoop data (bytes) 318system.membus.reqLayer0.occupancy 29834000 # Layer occupancy (ticks) 319system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 320system.membus.reqLayer1.occupancy 1588295250 # Layer occupancy (ticks) 321system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 322system.membus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) 323system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 324system.membus.respLayer1.occupancy 3825084824 # Layer occupancy (ticks) 325system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 326system.membus.respLayer2.occupancy 376625999 # Layer occupancy (ticks) 327system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 328system.iocache.tags.replacements 41685 # number of replacements 329system.iocache.tags.tagsinuse 1.295855 # Cycle average of tags in use 330system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 331system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 332system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 333system.iocache.tags.warmup_cycle 1728026399000 # Cycle when the warmup percentage was hit. 334system.iocache.tags.occ_blocks::tsunami.ide 1.295855 # Average occupied blocks per requestor 335system.iocache.tags.occ_percent::tsunami.ide 0.080991 # Average percentage of cache occupancy 336system.iocache.tags.occ_percent::total 0.080991 # Average percentage of cache occupancy 337system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 338system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 339system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 340system.iocache.tags.tag_accesses 375525 # Number of tag accesses 341system.iocache.tags.data_accesses 375525 # Number of data accesses 342system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 343system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 344system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 345system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 346system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 347system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 348system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 349system.iocache.overall_misses::total 41725 # number of overall misses 350system.iocache.ReadReq_miss_latency::tsunami.ide 21134133 # number of ReadReq miss cycles 351system.iocache.ReadReq_miss_latency::total 21134133 # number of ReadReq miss cycles 352system.iocache.WriteReq_miss_latency::tsunami.ide 12414876231 # number of WriteReq miss cycles 353system.iocache.WriteReq_miss_latency::total 12414876231 # number of WriteReq miss cycles 354system.iocache.demand_miss_latency::tsunami.ide 12436010364 # number of demand (read+write) miss cycles 355system.iocache.demand_miss_latency::total 12436010364 # number of demand (read+write) miss cycles 356system.iocache.overall_miss_latency::tsunami.ide 12436010364 # number of overall miss cycles 357system.iocache.overall_miss_latency::total 12436010364 # number of overall miss cycles 358system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 359system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 360system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 361system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 362system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 363system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 364system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 365system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 366system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 367system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 368system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 369system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 370system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 371system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 372system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 373system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 374system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122162.618497 # average ReadReq miss latency 375system.iocache.ReadReq_avg_miss_latency::total 122162.618497 # average ReadReq miss latency 376system.iocache.WriteReq_avg_miss_latency::tsunami.ide 298779.270095 # average WriteReq miss latency 377system.iocache.WriteReq_avg_miss_latency::total 298779.270095 # average WriteReq miss latency 378system.iocache.demand_avg_miss_latency::tsunami.ide 298046.982960 # average overall miss latency 379system.iocache.demand_avg_miss_latency::total 298046.982960 # average overall miss latency 380system.iocache.overall_avg_miss_latency::tsunami.ide 298046.982960 # average overall miss latency 381system.iocache.overall_avg_miss_latency::total 298046.982960 # average overall miss latency 382system.iocache.blocked_cycles::no_mshrs 364154 # number of cycles access was blocked 383system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 384system.iocache.blocked::no_mshrs 28275 # number of cycles access was blocked 385system.iocache.blocked::no_targets 0 # number of cycles access was blocked 386system.iocache.avg_blocked_cycles::no_mshrs 12.879010 # average number of cycles each access was blocked 387system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 388system.iocache.fast_writes 0 # number of fast writes performed 389system.iocache.cache_copies 0 # number of cache copies performed 390system.iocache.writebacks::writebacks 41512 # number of writebacks 391system.iocache.writebacks::total 41512 # number of writebacks 392system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 393system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 394system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 395system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 396system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 397system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 398system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 399system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 400system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137133 # number of ReadReq MSHR miss cycles 401system.iocache.ReadReq_mshr_miss_latency::total 12137133 # number of ReadReq MSHR miss cycles 402system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10251971233 # number of WriteReq MSHR miss cycles 403system.iocache.WriteReq_mshr_miss_latency::total 10251971233 # number of WriteReq MSHR miss cycles 404system.iocache.demand_mshr_miss_latency::tsunami.ide 10264108366 # number of demand (read+write) MSHR miss cycles 405system.iocache.demand_mshr_miss_latency::total 10264108366 # number of demand (read+write) MSHR miss cycles 406system.iocache.overall_mshr_miss_latency::tsunami.ide 10264108366 # number of overall MSHR miss cycles 407system.iocache.overall_mshr_miss_latency::total 10264108366 # number of overall MSHR miss cycles 408system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 409system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 410system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 411system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 412system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 413system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 414system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 415system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 416system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70156.838150 # average ReadReq mshr miss latency 417system.iocache.ReadReq_avg_mshr_miss_latency::total 70156.838150 # average ReadReq mshr miss latency 418system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246726.300371 # average WriteReq mshr miss latency 419system.iocache.WriteReq_avg_mshr_miss_latency::total 246726.300371 # average WriteReq mshr miss latency 420system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 245994.208892 # average overall mshr miss latency 421system.iocache.demand_avg_mshr_miss_latency::total 245994.208892 # average overall mshr miss latency 422system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 245994.208892 # average overall mshr miss latency 423system.iocache.overall_avg_mshr_miss_latency::total 245994.208892 # average overall mshr miss latency 424system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 425system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 426system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 427system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 428system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 429system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 430system.disk0.dma_write_txs 395 # Number of DMA write transactions. 431system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 432system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 433system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 434system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 435system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 436system.disk2.dma_write_txs 1 # Number of DMA write transactions. 437system.cpu.branchPred.lookups 14968340 # Number of BP lookups 438system.cpu.branchPred.condPredicted 12984271 # Number of conditional branches predicted 439system.cpu.branchPred.condIncorrect 377638 # Number of conditional branches incorrect 440system.cpu.branchPred.BTBLookups 10101234 # Number of BTB lookups 441system.cpu.branchPred.BTBHits 5190890 # Number of BTB hits |
|
| 15system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 442system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 16system.cpu.branchPred.BTBHitPct 52.670853 # BTB Hit Percentage 17system.cpu.branchPred.BTBHits 5198600 # Number of BTB hits 18system.cpu.branchPred.BTBLookups 9869975 # Number of BTB lookups 19system.cpu.branchPred.RASInCorrect 32078 # Number of incorrect RAS predictions. 20system.cpu.branchPred.condIncorrect 374087 # Number of conditional branches incorrect 21system.cpu.branchPred.condPredicted 13023618 # Number of conditional branches predicted 22system.cpu.branchPred.lookups 15007194 # Number of BP lookups 23system.cpu.branchPred.usedRAS 808258 # Number of times the RAS was used to get a target. 24system.cpu.committedInsts 56136190 # Number of instructions committed 25system.cpu.committedOps 56136190 # Number of ops (including micro ops) committed 26system.cpu.cpi 3.109494 # CPI: cycles per instruction 27system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200029 # number of LoadLockedReq accesses(hits+misses) 28system.cpu.dcache.LoadLockedReq_accesses::total 200029 # number of LoadLockedReq accesses(hits+misses) 29system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13395.968165 # average LoadLockedReq miss latency 30system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13395.968165 # average LoadLockedReq miss latency 31system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11388.427222 # average LoadLockedReq mshr miss latency 32system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11388.427222 # average LoadLockedReq mshr miss latency 33system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182878 # number of LoadLockedReq hits 34system.cpu.dcache.LoadLockedReq_hits::total 182878 # number of LoadLockedReq hits 35system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 229754250 # number of LoadLockedReq miss cycles 36system.cpu.dcache.LoadLockedReq_miss_latency::total 229754250 # number of LoadLockedReq miss cycles 37system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.085743 # miss rate for LoadLockedReq accesses 38system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085743 # miss rate for LoadLockedReq accesses 39system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17151 # number of LoadLockedReq misses 40system.cpu.dcache.LoadLockedReq_misses::total 17151 # number of LoadLockedReq misses 41system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits 42system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 43system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 195288750 # number of LoadLockedReq MSHR miss cycles 44system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195288750 # number of LoadLockedReq MSHR miss cycles 45system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.085728 # mshr miss rate for LoadLockedReq accesses 46system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085728 # mshr miss rate for LoadLockedReq accesses 47system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17148 # number of LoadLockedReq MSHR misses 48system.cpu.dcache.LoadLockedReq_mshr_misses::total 17148 # number of LoadLockedReq MSHR misses 49system.cpu.dcache.ReadReq_accesses::cpu.inst 9013279 # number of ReadReq accesses(hits+misses) 50system.cpu.dcache.ReadReq_accesses::total 9013279 # number of ReadReq accesses(hits+misses) 51system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25759.364421 # average ReadReq miss latency 52system.cpu.dcache.ReadReq_avg_miss_latency::total 25759.364421 # average ReadReq miss latency 53system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25018.369561 # average ReadReq mshr miss latency 54system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25018.369561 # average ReadReq mshr miss latency 55system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 56system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 57system.cpu.dcache.ReadReq_hits::cpu.inst 7812296 # number of ReadReq hits 58system.cpu.dcache.ReadReq_hits::total 7812296 # number of ReadReq hits 59system.cpu.dcache.ReadReq_miss_latency::cpu.inst 30936558760 # number of ReadReq miss cycles 60system.cpu.dcache.ReadReq_miss_latency::total 30936558760 # number of ReadReq miss cycles 61system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133246 # miss rate for ReadReq accesses 62system.cpu.dcache.ReadReq_miss_rate::total 0.133246 # miss rate for ReadReq accesses 63system.cpu.dcache.ReadReq_misses::cpu.inst 1200983 # number of ReadReq misses 64system.cpu.dcache.ReadReq_misses::total 1200983 # number of ReadReq misses 65system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127128 # number of ReadReq MSHR hits 66system.cpu.dcache.ReadReq_mshr_hits::total 127128 # number of ReadReq MSHR hits 67system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26866101245 # number of ReadReq MSHR miss cycles 68system.cpu.dcache.ReadReq_mshr_miss_latency::total 26866101245 # number of ReadReq MSHR miss cycles 69system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119141 # mshr miss rate for ReadReq accesses 70system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119141 # mshr miss rate for ReadReq accesses 71system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1073855 # number of ReadReq MSHR misses 72system.cpu.dcache.ReadReq_mshr_misses::total 1073855 # number of ReadReq MSHR misses 73system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423421000 # number of ReadReq MSHR uncacheable cycles 74system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423421000 # number of ReadReq MSHR uncacheable cycles 75system.cpu.dcache.StoreCondReq_accesses::cpu.inst 199007 # number of StoreCondReq accesses(hits+misses) 76system.cpu.dcache.StoreCondReq_accesses::total 199007 # number of StoreCondReq accesses(hits+misses) 77system.cpu.dcache.StoreCondReq_hits::cpu.inst 199007 # number of StoreCondReq hits 78system.cpu.dcache.StoreCondReq_hits::total 199007 # number of StoreCondReq hits 79system.cpu.dcache.WriteReq_accesses::cpu.inst 6151468 # number of WriteReq accesses(hits+misses) 80system.cpu.dcache.WriteReq_accesses::total 6151468 # number of WriteReq accesses(hits+misses) 81system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36155.340979 # average WriteReq miss latency 82system.cpu.dcache.WriteReq_avg_miss_latency::total 36155.340979 # average WriteReq miss latency 83system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33789.156794 # average WriteReq mshr miss latency 84system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33789.156794 # average WriteReq mshr miss latency 85system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 86system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 87system.cpu.dcache.WriteReq_hits::cpu.inst 5578034 # number of WriteReq hits 88system.cpu.dcache.WriteReq_hits::total 5578034 # number of WriteReq hits 89system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20732701799 # number of WriteReq miss cycles 90system.cpu.dcache.WriteReq_miss_latency::total 20732701799 # number of WriteReq miss cycles 91system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093219 # miss rate for WriteReq accesses 92system.cpu.dcache.WriteReq_miss_rate::total 0.093219 # miss rate for WriteReq accesses 93system.cpu.dcache.WriteReq_misses::cpu.inst 573434 # number of WriteReq misses 94system.cpu.dcache.WriteReq_misses::total 573434 # number of WriteReq misses 95system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269372 # number of WriteReq MSHR hits 96system.cpu.dcache.WriteReq_mshr_hits::total 269372 # number of WriteReq MSHR hits 97system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10273998593 # number of WriteReq MSHR miss cycles 98system.cpu.dcache.WriteReq_mshr_miss_latency::total 10273998593 # number of WriteReq MSHR miss cycles 99system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049429 # mshr miss rate for WriteReq accesses 100system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049429 # mshr miss rate for WriteReq accesses 101system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304062 # number of WriteReq MSHR misses 102system.cpu.dcache.WriteReq_mshr_misses::total 304062 # number of WriteReq MSHR misses 103system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002985000 # number of WriteReq MSHR uncacheable cycles 104system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002985000 # number of WriteReq MSHR uncacheable cycles 105system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 106system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 107system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 108system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 109system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 110system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 111system.cpu.dcache.cache_copies 0 # number of cache copies performed 112system.cpu.dcache.demand_accesses::cpu.inst 15164747 # number of demand (read+write) accesses 113system.cpu.dcache.demand_accesses::total 15164747 # number of demand (read+write) accesses 114system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29119.006727 # average overall miss latency 115system.cpu.dcache.demand_avg_miss_latency::total 29119.006727 # average overall miss latency 116system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26953.800438 # average overall mshr miss latency 117system.cpu.dcache.demand_avg_mshr_miss_latency::total 26953.800438 # average overall mshr miss latency 118system.cpu.dcache.demand_hits::cpu.inst 13390330 # number of demand (read+write) hits 119system.cpu.dcache.demand_hits::total 13390330 # number of demand (read+write) hits 120system.cpu.dcache.demand_miss_latency::cpu.inst 51669260559 # number of demand (read+write) miss cycles 121system.cpu.dcache.demand_miss_latency::total 51669260559 # number of demand (read+write) miss cycles 122system.cpu.dcache.demand_miss_rate::cpu.inst 0.117009 # miss rate for demand accesses 123system.cpu.dcache.demand_miss_rate::total 0.117009 # miss rate for demand accesses 124system.cpu.dcache.demand_misses::cpu.inst 1774417 # number of demand (read+write) misses 125system.cpu.dcache.demand_misses::total 1774417 # number of demand (read+write) misses 126system.cpu.dcache.demand_mshr_hits::cpu.inst 396500 # number of demand (read+write) MSHR hits 127system.cpu.dcache.demand_mshr_hits::total 396500 # number of demand (read+write) MSHR hits 128system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37140099838 # number of demand (read+write) MSHR miss cycles 129system.cpu.dcache.demand_mshr_miss_latency::total 37140099838 # number of demand (read+write) MSHR miss cycles 130system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090863 # mshr miss rate for demand accesses 131system.cpu.dcache.demand_mshr_miss_rate::total 0.090863 # mshr miss rate for demand accesses 132system.cpu.dcache.demand_mshr_misses::cpu.inst 1377917 # number of demand (read+write) MSHR misses 133system.cpu.dcache.demand_mshr_misses::total 1377917 # number of demand (read+write) MSHR misses 134system.cpu.dcache.fast_writes 0 # number of fast writes performed 135system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 136system.cpu.dcache.overall_accesses::cpu.inst 15164747 # number of overall (read+write) accesses 137system.cpu.dcache.overall_accesses::total 15164747 # number of overall (read+write) accesses 138system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29119.006727 # average overall miss latency 139system.cpu.dcache.overall_avg_miss_latency::total 29119.006727 # average overall miss latency 140system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26953.800438 # average overall mshr miss latency 141system.cpu.dcache.overall_avg_mshr_miss_latency::total 26953.800438 # average overall mshr miss latency 142system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 143system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 144system.cpu.dcache.overall_hits::cpu.inst 13390330 # number of overall hits 145system.cpu.dcache.overall_hits::total 13390330 # number of overall hits 146system.cpu.dcache.overall_miss_latency::cpu.inst 51669260559 # number of overall miss cycles 147system.cpu.dcache.overall_miss_latency::total 51669260559 # number of overall miss cycles 148system.cpu.dcache.overall_miss_rate::cpu.inst 0.117009 # miss rate for overall accesses 149system.cpu.dcache.overall_miss_rate::total 0.117009 # miss rate for overall accesses 150system.cpu.dcache.overall_misses::cpu.inst 1774417 # number of overall misses 151system.cpu.dcache.overall_misses::total 1774417 # number of overall misses 152system.cpu.dcache.overall_mshr_hits::cpu.inst 396500 # number of overall MSHR hits 153system.cpu.dcache.overall_mshr_hits::total 396500 # number of overall MSHR hits 154system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37140099838 # number of overall MSHR miss cycles 155system.cpu.dcache.overall_mshr_miss_latency::total 37140099838 # number of overall MSHR miss cycles 156system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090863 # mshr miss rate for overall accesses 157system.cpu.dcache.overall_mshr_miss_rate::total 0.090863 # mshr miss rate for overall accesses 158system.cpu.dcache.overall_mshr_misses::cpu.inst 1377917 # number of overall MSHR misses 159system.cpu.dcache.overall_mshr_misses::total 1377917 # number of overall MSHR misses 160system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426406000 # number of overall MSHR uncacheable cycles 161system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426406000 # number of overall MSHR uncacheable cycles 162system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 163system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 164system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 165system.cpu.dcache.tags.avg_refs 9.872403 # Average number of references to valid blocks. 166system.cpu.dcache.tags.data_accesses 63650159 # Number of data accesses 167system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982305 # Average occupied blocks per requestor 168system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy 169system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy 170system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 171system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 172system.cpu.dcache.tags.replacements 1394513 # number of replacements 173system.cpu.dcache.tags.sampled_refs 1395025 # Sample count of references to valid blocks. 174system.cpu.dcache.tags.tag_accesses 63650159 # Number of tag accesses 175system.cpu.dcache.tags.tagsinuse 511.982305 # Cycle average of tags in use 176system.cpu.dcache.tags.total_refs 13772249 # Total number of references to valid blocks. 177system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit. 178system.cpu.dcache.writebacks::writebacks 837448 # number of writebacks 179system.cpu.dcache.writebacks::total 837448 # number of writebacks 180system.cpu.discardedOps 2565798 # Number of ops (including micro ops) which were discarded before commit 181system.cpu.dtb.data_accesses 1069353 # DTB accesses 182system.cpu.dtb.data_acv 370 # DTB access violations 183system.cpu.dtb.data_hits 15629370 # DTB hits 184system.cpu.dtb.data_misses 21396 # DTB misses 185system.cpu.dtb.fetch_accesses 0 # ITB accesses 186system.cpu.dtb.fetch_acv 0 # ITB acv | 443system.cpu.branchPred.BTBHitPct 51.388672 # BTB Hit Percentage 444system.cpu.branchPred.usedRAS 808188 # Number of times the RAS was used to get a target. 445system.cpu.branchPred.RASInCorrect 32062 # Number of incorrect RAS predictions. 446system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 187system.cpu.dtb.fetch_hits 0 # ITB hits 188system.cpu.dtb.fetch_misses 0 # ITB misses | 447system.cpu.dtb.fetch_hits 0 # ITB hits 448system.cpu.dtb.fetch_misses 0 # ITB misses |
| 189system.cpu.dtb.read_accesses 770885 # DTB read accesses | 449system.cpu.dtb.fetch_acv 0 # ITB acv 450system.cpu.dtb.fetch_accesses 0 # ITB accesses 451system.cpu.dtb.read_hits 9240282 # DTB read hits 452system.cpu.dtb.read_misses 17901 # DTB read misses |
| 190system.cpu.dtb.read_acv 211 # DTB read access violations | 453system.cpu.dtb.read_acv 211 # DTB read access violations |
| 191system.cpu.dtb.read_hits 9243246 # DTB read hits 192system.cpu.dtb.read_misses 19107 # DTB read misses 193system.cpu.dtb.write_accesses 298468 # DTB write accesses | 454system.cpu.dtb.read_accesses 766280 # DTB read accesses 455system.cpu.dtb.write_hits 6385567 # DTB write hits 456system.cpu.dtb.write_misses 2310 # DTB write misses |
| 194system.cpu.dtb.write_acv 159 # DTB write access violations | 457system.cpu.dtb.write_acv 159 # DTB write access violations |
| 195system.cpu.dtb.write_hits 6386124 # DTB write hits 196system.cpu.dtb.write_misses 2289 # DTB write misses 197system.cpu.icache.ReadReq_accesses::cpu.inst 20425038 # number of ReadReq accesses(hits+misses) 198system.cpu.icache.ReadReq_accesses::total 20425038 # number of ReadReq accesses(hits+misses) 199system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.021807 # average ReadReq miss latency 200system.cpu.icache.ReadReq_avg_miss_latency::total 13727.021807 # average ReadReq miss latency 201system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.006480 # average ReadReq mshr miss latency 202system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.006480 # average ReadReq mshr miss latency 203system.cpu.icache.ReadReq_hits::cpu.inst 18964885 # number of ReadReq hits 204system.cpu.icache.ReadReq_hits::total 18964885 # number of ReadReq hits 205system.cpu.icache.ReadReq_miss_latency::cpu.inst 20043552072 # number of ReadReq miss cycles 206system.cpu.icache.ReadReq_miss_latency::total 20043552072 # number of ReadReq miss cycles 207system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071488 # miss rate for ReadReq accesses 208system.cpu.icache.ReadReq_miss_rate::total 0.071488 # miss rate for ReadReq accesses 209system.cpu.icache.ReadReq_misses::cpu.inst 1460153 # number of ReadReq misses 210system.cpu.icache.ReadReq_misses::total 1460153 # number of ReadReq misses 211system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17115922928 # number of ReadReq MSHR miss cycles 212system.cpu.icache.ReadReq_mshr_miss_latency::total 17115922928 # number of ReadReq MSHR miss cycles 213system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071488 # mshr miss rate for ReadReq accesses 214system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071488 # mshr miss rate for ReadReq accesses 215system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1460153 # number of ReadReq MSHR misses 216system.cpu.icache.ReadReq_mshr_misses::total 1460153 # number of ReadReq MSHR misses 217system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 218system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 219system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 220system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 221system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 222system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 223system.cpu.icache.cache_copies 0 # number of cache copies performed 224system.cpu.icache.demand_accesses::cpu.inst 20425038 # number of demand (read+write) accesses 225system.cpu.icache.demand_accesses::total 20425038 # number of demand (read+write) accesses 226system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.021807 # average overall miss latency 227system.cpu.icache.demand_avg_miss_latency::total 13727.021807 # average overall miss latency 228system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.006480 # average overall mshr miss latency 229system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.006480 # average overall mshr miss latency 230system.cpu.icache.demand_hits::cpu.inst 18964885 # number of demand (read+write) hits 231system.cpu.icache.demand_hits::total 18964885 # number of demand (read+write) hits 232system.cpu.icache.demand_miss_latency::cpu.inst 20043552072 # number of demand (read+write) miss cycles 233system.cpu.icache.demand_miss_latency::total 20043552072 # number of demand (read+write) miss cycles 234system.cpu.icache.demand_miss_rate::cpu.inst 0.071488 # miss rate for demand accesses 235system.cpu.icache.demand_miss_rate::total 0.071488 # miss rate for demand accesses 236system.cpu.icache.demand_misses::cpu.inst 1460153 # number of demand (read+write) misses 237system.cpu.icache.demand_misses::total 1460153 # number of demand (read+write) misses 238system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17115922928 # number of demand (read+write) MSHR miss cycles 239system.cpu.icache.demand_mshr_miss_latency::total 17115922928 # number of demand (read+write) MSHR miss cycles 240system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071488 # mshr miss rate for demand accesses 241system.cpu.icache.demand_mshr_miss_rate::total 0.071488 # mshr miss rate for demand accesses 242system.cpu.icache.demand_mshr_misses::cpu.inst 1460153 # number of demand (read+write) MSHR misses 243system.cpu.icache.demand_mshr_misses::total 1460153 # number of demand (read+write) MSHR misses 244system.cpu.icache.fast_writes 0 # number of fast writes performed 245system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 246system.cpu.icache.overall_accesses::cpu.inst 20425038 # number of overall (read+write) accesses 247system.cpu.icache.overall_accesses::total 20425038 # number of overall (read+write) accesses 248system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.021807 # average overall miss latency 249system.cpu.icache.overall_avg_miss_latency::total 13727.021807 # average overall miss latency 250system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.006480 # average overall mshr miss latency 251system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.006480 # average overall mshr miss latency 252system.cpu.icache.overall_hits::cpu.inst 18964885 # number of overall hits 253system.cpu.icache.overall_hits::total 18964885 # number of overall hits 254system.cpu.icache.overall_miss_latency::cpu.inst 20043552072 # number of overall miss cycles 255system.cpu.icache.overall_miss_latency::total 20043552072 # number of overall miss cycles 256system.cpu.icache.overall_miss_rate::cpu.inst 0.071488 # miss rate for overall accesses 257system.cpu.icache.overall_miss_rate::total 0.071488 # miss rate for overall accesses 258system.cpu.icache.overall_misses::cpu.inst 1460153 # number of overall misses 259system.cpu.icache.overall_misses::total 1460153 # number of overall misses 260system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17115922928 # number of overall MSHR miss cycles 261system.cpu.icache.overall_mshr_miss_latency::total 17115922928 # number of overall MSHR miss cycles 262system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071488 # mshr miss rate for overall accesses 263system.cpu.icache.overall_mshr_miss_rate::total 0.071488 # mshr miss rate for overall accesses 264system.cpu.icache.overall_mshr_misses::cpu.inst 1460153 # number of overall MSHR misses 265system.cpu.icache.overall_mshr_misses::total 1460153 # number of overall MSHR misses 266system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 267system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 268system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id 269system.cpu.icache.tags.avg_refs 12.989850 # Average number of references to valid blocks. 270system.cpu.icache.tags.data_accesses 21885191 # Number of data accesses 271system.cpu.icache.tags.occ_blocks::cpu.inst 509.631985 # Average occupied blocks per requestor 272system.cpu.icache.tags.occ_percent::cpu.inst 0.995375 # Average percentage of cache occupancy 273system.cpu.icache.tags.occ_percent::total 0.995375 # Average percentage of cache occupancy 274system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 275system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 276system.cpu.icache.tags.replacements 1459466 # number of replacements 277system.cpu.icache.tags.sampled_refs 1459977 # Sample count of references to valid blocks. 278system.cpu.icache.tags.tag_accesses 21885191 # Number of tag accesses 279system.cpu.icache.tags.tagsinuse 509.631985 # Cycle average of tags in use 280system.cpu.icache.tags.total_refs 18964882 # Total number of references to valid blocks. 281system.cpu.icache.tags.warmup_cycle 31504045250 # Cycle when the warmup percentage was hit. 282system.cpu.idleCycles 90671171 # Total number of cycles that the CPU has spent unscheduled due to idling 283system.cpu.ipc 0.321596 # IPC: instructions per cycle 284system.cpu.itb.data_accesses 0 # DTB accesses 285system.cpu.itb.data_acv 0 # DTB access violations 286system.cpu.itb.data_hits 0 # DTB hits 287system.cpu.itb.data_misses 0 # DTB misses 288system.cpu.itb.fetch_accesses 4018394 # ITB accesses 289system.cpu.itb.fetch_acv 700 # ITB acv 290system.cpu.itb.fetch_hits 4011544 # ITB hits 291system.cpu.itb.fetch_misses 6850 # ITB misses 292system.cpu.itb.read_accesses 0 # DTB read accesses 293system.cpu.itb.read_acv 0 # DTB read access violations | 458system.cpu.dtb.write_accesses 298488 # DTB write accesses 459system.cpu.dtb.data_hits 15625849 # DTB hits 460system.cpu.dtb.data_misses 20211 # DTB misses 461system.cpu.dtb.data_acv 370 # DTB access violations 462system.cpu.dtb.data_accesses 1064768 # DTB accesses 463system.cpu.itb.fetch_hits 4001359 # ITB hits 464system.cpu.itb.fetch_misses 6809 # ITB misses 465system.cpu.itb.fetch_acv 657 # ITB acv 466system.cpu.itb.fetch_accesses 4008168 # ITB accesses |
| 294system.cpu.itb.read_hits 0 # DTB read hits 295system.cpu.itb.read_misses 0 # DTB read misses | 467system.cpu.itb.read_hits 0 # DTB read hits 468system.cpu.itb.read_misses 0 # DTB read misses |
| 296system.cpu.itb.write_accesses 0 # DTB write accesses 297system.cpu.itb.write_acv 0 # DTB write access violations | 469system.cpu.itb.read_acv 0 # DTB read access violations 470system.cpu.itb.read_accesses 0 # DTB read accesses |
| 298system.cpu.itb.write_hits 0 # DTB write hits 299system.cpu.itb.write_misses 0 # DTB write misses | 471system.cpu.itb.write_hits 0 # DTB write hits 472system.cpu.itb.write_misses 0 # DTB write misses |
| 300system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 301system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 302system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 303system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 304system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed 305system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 306system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 307system.cpu.kern.callpal::swpipl 175531 91.22% 93.43% # number of callpals executed 308system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed 309system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 310system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 311system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 312system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 313system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed 314system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 315system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 316system.cpu.kern.callpal::total 192418 # number of callpals executed | 473system.cpu.itb.write_acv 0 # DTB write access violations 474system.cpu.itb.write_accesses 0 # DTB write accesses 475system.cpu.itb.data_hits 0 # DTB hits 476system.cpu.itb.data_misses 0 # DTB misses 477system.cpu.itb.data_acv 0 # DTB access violations 478system.cpu.itb.data_accesses 0 # DTB accesses 479system.cpu.numCycles 176815826 # number of cpu cycles simulated 480system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 481system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 482system.cpu.committedInsts 56126572 # Number of instructions committed 483system.cpu.committedOps 56126572 # Number of ops (including micro ops) committed 484system.cpu.discardedOps 2538059 # Number of ops (including micro ops) which were discarded before commit 485system.cpu.numFetchSuspends 5497 # Number of times Execute suspended instruction fetching 486system.cpu.quiesceCycles 3593513250 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 487system.cpu.cpi 3.150305 # CPI: cycles per instruction 488system.cpu.ipc 0.317430 # IPC: instructions per cycle |
| 317system.cpu.kern.inst.arm 0 # number of arm instructions executed | 489system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 318system.cpu.kern.inst.hwrei 211480 # number of hwrei instructions executed 319system.cpu.kern.inst.quiesce 6384 # number of quiesce instructions executed 320system.cpu.kern.ipl_count::0 74792 40.94% 40.94% # number of times we switched to this ipl | 490system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed 491system.cpu.kern.inst.hwrei 211465 # number of hwrei instructions executed 492system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl |
| 321system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl 322system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl | 493system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl 494system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl |
| 323system.cpu.kern.ipl_count::31 105866 57.95% 100.00% # number of times we switched to this ipl 324system.cpu.kern.ipl_count::total 182690 # number of times we switched to this ipl 325system.cpu.kern.ipl_good::0 73425 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 495system.cpu.kern.ipl_count::31 105856 57.95% 100.00% # number of times we switched to this ipl 496system.cpu.kern.ipl_count::total 182675 # number of times we switched to this ipl 497system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 326system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 327system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl | 498system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 499system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl |
| 328system.cpu.kern.ipl_good::31 73425 49.32% 100.00% # number of times we switched to this ipl from a different ipl 329system.cpu.kern.ipl_good::total 148882 # number of times we switched to this ipl from a different ipl 330system.cpu.kern.ipl_ticks::0 1833909486500 97.33% 97.33% # number of cycles we spent at this ipl 331system.cpu.kern.ipl_ticks::21 80399500 0.00% 97.33% # number of cycles we spent at this ipl 332system.cpu.kern.ipl_ticks::22 673524500 0.04% 97.37% # number of cycles we spent at this ipl 333system.cpu.kern.ipl_ticks::31 49559388000 2.63% 100.00% # number of cycles we spent at this ipl 334system.cpu.kern.ipl_ticks::total 1884222798500 # number of cycles we spent at this ipl 335system.cpu.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl | 500system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl 501system.cpu.kern.ipl_good::total 148872 # number of times we switched to this ipl from a different ipl 502system.cpu.kern.ipl_ticks::0 1833844528000 97.33% 97.33% # number of cycles we spent at this ipl 503system.cpu.kern.ipl_ticks::21 80077500 0.00% 97.33% # number of cycles we spent at this ipl 504system.cpu.kern.ipl_ticks::22 673181000 0.04% 97.37% # number of cycles we spent at this ipl 505system.cpu.kern.ipl_ticks::31 49609971000 2.63% 100.00% # number of cycles we spent at this ipl 506system.cpu.kern.ipl_ticks::total 1884207757500 # number of cycles we spent at this ipl 507system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl |
| 336system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 337system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 508system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 509system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 338system.cpu.kern.ipl_used::31 0.693565 # fraction of swpipl calls that actually changed the ipl 339system.cpu.kern.ipl_used::total 0.814943 # fraction of swpipl calls that actually changed the ipl 340system.cpu.kern.mode_good::kernel 1910 341system.cpu.kern.mode_good::user 1740 342system.cpu.kern.mode_good::idle 170 343system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches 344system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 345system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches 346system.cpu.kern.mode_switch_good::kernel 0.325217 # fraction of useful protection mode switches 347system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 348system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches 349system.cpu.kern.mode_switch_good::total 0.393449 # fraction of useful protection mode switches 350system.cpu.kern.mode_ticks::kernel 36228247000 1.92% 1.92% # number of ticks spent at the given mode 351system.cpu.kern.mode_ticks::user 4082723500 0.22% 2.14% # number of ticks spent at the given mode 352system.cpu.kern.mode_ticks::idle 1843911818000 97.86% 100.00% # number of ticks spent at the given mode 353system.cpu.kern.swap_context 4178 # number of times the context was actually changed | 510system.cpu.kern.ipl_used::31 0.693584 # fraction of swpipl calls that actually changed the ipl 511system.cpu.kern.ipl_used::total 0.814956 # fraction of swpipl calls that actually changed the ipl |
| 354system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 355system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 356system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 357system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 358system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 359system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 360system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 361system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 377system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 378system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 379system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 380system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 381system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 382system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 383system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 384system.cpu.kern.syscall::total 326 # number of syscalls executed | 512system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 513system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 514system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 515system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 516system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 517system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 518system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 519system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 535system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 536system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 537system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 538system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 539system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 540system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 541system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 542system.cpu.kern.syscall::total 326 # number of syscalls executed |
| 385system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304079 # number of ReadExReq accesses(hits+misses) 386system.cpu.l2cache.ReadExReq_accesses::total 304079 # number of ReadExReq accesses(hits+misses) 387system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69348.639186 # average ReadExReq miss latency 388system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69348.639186 # average ReadExReq miss latency 389system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56485.106925 # average ReadExReq mshr miss latency 390system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56485.106925 # average ReadExReq mshr miss latency 391system.cpu.l2cache.ReadExReq_hits::cpu.inst 187390 # number of ReadExReq hits 392system.cpu.l2cache.ReadExReq_hits::total 187390 # number of ReadExReq hits 393system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8092223358 # number of ReadExReq miss cycles 394system.cpu.l2cache.ReadExReq_miss_latency::total 8092223358 # number of ReadExReq miss cycles 395system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383746 # miss rate for ReadExReq accesses 396system.cpu.l2cache.ReadExReq_miss_rate::total 0.383746 # miss rate for ReadExReq accesses 397system.cpu.l2cache.ReadExReq_misses::cpu.inst 116689 # number of ReadExReq misses 398system.cpu.l2cache.ReadExReq_misses::total 116689 # number of ReadExReq misses 399system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6591190642 # number of ReadExReq MSHR miss cycles 400system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6591190642 # number of ReadExReq MSHR miss cycles 401system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383746 # mshr miss rate for ReadExReq accesses 402system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383746 # mshr miss rate for ReadExReq accesses 403system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116689 # number of ReadExReq MSHR misses 404system.cpu.l2cache.ReadExReq_mshr_misses::total 116689 # number of ReadExReq MSHR misses 405system.cpu.l2cache.ReadReq_accesses::cpu.inst 2551058 # number of ReadReq accesses(hits+misses) 406system.cpu.l2cache.ReadReq_accesses::total 2551058 # number of ReadReq accesses(hits+misses) 407system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65542.886814 # average ReadReq miss latency 408system.cpu.l2cache.ReadReq_avg_miss_latency::total 65542.886814 # average ReadReq miss latency 409system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53041.655311 # average ReadReq mshr miss latency 410system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.655311 # average ReadReq mshr miss latency 411system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 412system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 413system.cpu.l2cache.ReadReq_hits::cpu.inst 2262409 # number of ReadReq hits 414system.cpu.l2cache.ReadReq_hits::total 2262409 # number of ReadReq hits 415system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18918888736 # number of ReadReq miss cycles 416system.cpu.l2cache.ReadReq_miss_latency::total 18918888736 # number of ReadReq miss cycles 417system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113149 # miss rate for ReadReq accesses 418system.cpu.l2cache.ReadReq_miss_rate::total 0.113149 # miss rate for ReadReq accesses 419system.cpu.l2cache.ReadReq_misses::cpu.inst 288649 # number of ReadReq misses 420system.cpu.l2cache.ReadReq_misses::total 288649 # number of ReadReq misses 421system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15310420764 # number of ReadReq MSHR miss cycles 422system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15310420764 # number of ReadReq MSHR miss cycles 423system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113149 # mshr miss rate for ReadReq accesses 424system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113149 # mshr miss rate for ReadReq accesses 425system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288649 # number of ReadReq MSHR misses 426system.cpu.l2cache.ReadReq_mshr_misses::total 288649 # number of ReadReq MSHR misses 427system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333330000 # number of ReadReq MSHR uncacheable cycles 428system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333330000 # number of ReadReq MSHR uncacheable cycles 429system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses) 430system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) 431system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 12646.882353 # average UpgradeReq miss latency 432system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12646.882353 # average UpgradeReq miss latency 433system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15971.411765 # average UpgradeReq mshr miss latency 434system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15971.411765 # average UpgradeReq mshr miss latency 435system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits 436system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 437system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 214997 # number of UpgradeReq miss cycles 438system.cpu.l2cache.UpgradeReq_miss_latency::total 214997 # number of UpgradeReq miss cycles 439system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses 440system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses 441system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses 442system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses 443system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 271514 # number of UpgradeReq MSHR miss cycles 444system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271514 # number of UpgradeReq MSHR miss cycles 445system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses 446system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses 447system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses 448system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses 449system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 450system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 451system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887556500 # number of WriteReq MSHR uncacheable cycles 452system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887556500 # number of WriteReq MSHR uncacheable cycles 453system.cpu.l2cache.Writeback_accesses::writebacks 837448 # number of Writeback accesses(hits+misses) 454system.cpu.l2cache.Writeback_accesses::total 837448 # number of Writeback accesses(hits+misses) 455system.cpu.l2cache.Writeback_hits::writebacks 837448 # number of Writeback hits 456system.cpu.l2cache.Writeback_hits::total 837448 # number of Writeback hits 457system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 458system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 459system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 460system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 461system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.cpu.l2cache.cache_copies 0 # number of cache copies performed 464system.cpu.l2cache.demand_accesses::cpu.inst 2855137 # number of demand (read+write) accesses 465system.cpu.l2cache.demand_accesses::total 2855137 # number of demand (read+write) accesses 466system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66638.489591 # average overall miss latency 467system.cpu.l2cache.demand_avg_miss_latency::total 66638.489591 # average overall miss latency 468system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54032.958681 # average overall mshr miss latency 469system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54032.958681 # average overall mshr miss latency 470system.cpu.l2cache.demand_hits::cpu.inst 2449799 # number of demand (read+write) hits 471system.cpu.l2cache.demand_hits::total 2449799 # number of demand (read+write) hits 472system.cpu.l2cache.demand_miss_latency::cpu.inst 27011112094 # number of demand (read+write) miss cycles 473system.cpu.l2cache.demand_miss_latency::total 27011112094 # number of demand (read+write) miss cycles 474system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141968 # miss rate for demand accesses 475system.cpu.l2cache.demand_miss_rate::total 0.141968 # miss rate for demand accesses 476system.cpu.l2cache.demand_misses::cpu.inst 405338 # number of demand (read+write) misses 477system.cpu.l2cache.demand_misses::total 405338 # number of demand (read+write) misses 478system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21901611406 # number of demand (read+write) MSHR miss cycles 479system.cpu.l2cache.demand_mshr_miss_latency::total 21901611406 # number of demand (read+write) MSHR miss cycles 480system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141968 # mshr miss rate for demand accesses 481system.cpu.l2cache.demand_mshr_miss_rate::total 0.141968 # mshr miss rate for demand accesses 482system.cpu.l2cache.demand_mshr_misses::cpu.inst 405338 # number of demand (read+write) MSHR misses 483system.cpu.l2cache.demand_mshr_misses::total 405338 # number of demand (read+write) MSHR misses 484system.cpu.l2cache.fast_writes 0 # number of fast writes performed 485system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 486system.cpu.l2cache.overall_accesses::cpu.inst 2855137 # number of overall (read+write) accesses 487system.cpu.l2cache.overall_accesses::total 2855137 # number of overall (read+write) accesses 488system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66638.489591 # average overall miss latency 489system.cpu.l2cache.overall_avg_miss_latency::total 66638.489591 # average overall miss latency 490system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54032.958681 # average overall mshr miss latency 491system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54032.958681 # average overall mshr miss latency 492system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 493system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 494system.cpu.l2cache.overall_hits::cpu.inst 2449799 # number of overall hits 495system.cpu.l2cache.overall_hits::total 2449799 # number of overall hits 496system.cpu.l2cache.overall_miss_latency::cpu.inst 27011112094 # number of overall miss cycles 497system.cpu.l2cache.overall_miss_latency::total 27011112094 # number of overall miss cycles 498system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141968 # miss rate for overall accesses 499system.cpu.l2cache.overall_miss_rate::total 0.141968 # miss rate for overall accesses 500system.cpu.l2cache.overall_misses::cpu.inst 405338 # number of overall misses 501system.cpu.l2cache.overall_misses::total 405338 # number of overall misses 502system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21901611406 # number of overall MSHR miss cycles 503system.cpu.l2cache.overall_mshr_miss_latency::total 21901611406 # number of overall MSHR miss cycles 504system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141968 # mshr miss rate for overall accesses 505system.cpu.l2cache.overall_mshr_miss_rate::total 0.141968 # mshr miss rate for overall accesses 506system.cpu.l2cache.overall_mshr_misses::cpu.inst 405338 # number of overall MSHR misses 507system.cpu.l2cache.overall_mshr_misses::total 405338 # number of overall MSHR misses 508system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3220886500 # number of overall MSHR uncacheable cycles 509system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3220886500 # number of overall MSHR uncacheable cycles 510system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 511system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1457 # Occupied blocks per task id 512system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5165 # Occupied blocks per task id 513system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2777 # Occupied blocks per task id 514system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55533 # Occupied blocks per task id 515system.cpu.l2cache.tags.avg_refs 7.369819 # Average number of references to valid blocks. 516system.cpu.l2cache.tags.data_accesses 30249758 # Number of data accesses 517system.cpu.l2cache.tags.occ_blocks::writebacks 54473.589189 # Average occupied blocks per requestor 518system.cpu.l2cache.tags.occ_blocks::cpu.inst 10850.670788 # Average occupied blocks per requestor 519system.cpu.l2cache.tags.occ_percent::writebacks 0.831201 # Average percentage of cache occupancy 520system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165568 # Average percentage of cache occupancy 521system.cpu.l2cache.tags.occ_percent::total 0.996769 # Average percentage of cache occupancy 522system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 523system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id 524system.cpu.l2cache.tags.replacements 339425 # number of replacements 525system.cpu.l2cache.tags.sampled_refs 404587 # Sample count of references to valid blocks. 526system.cpu.l2cache.tags.tag_accesses 30249758 # Number of tag accesses 527system.cpu.l2cache.tags.tagsinuse 65324.259976 # Cycle average of tags in use 528system.cpu.l2cache.tags.total_refs 2981733 # Total number of references to valid blocks. 529system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit. 530system.cpu.l2cache.writebacks::writebacks 76620 # number of writebacks 531system.cpu.l2cache.writebacks::total 76620 # number of writebacks 532system.cpu.numCycles 174555159 # number of cpu cycles simulated 533system.cpu.numFetchSuspends 5529 # Number of times Execute suspended instruction fetching 534system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 535system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 536system.cpu.quiesceCycles 3593892488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 537system.cpu.tickCycles 83883988 # Number of cycles that the CPU actually ticked 538system.cpu.toL2Bus.data_through_bus 236368668 # Total data (bytes) 539system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2920246 # Packet count per connected master and slave (bytes) 540system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3660834 # Packet count per connected master and slave (bytes) 541system.cpu.toL2Bus.pkt_count::total 6581080 # Packet count per connected master and slave (bytes) 542system.cpu.toL2Bus.reqLayer0.occupancy 2696865499 # Layer occupancy (ticks) 543system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 544system.cpu.toL2Bus.respLayer0.occupancy 2193891072 # Layer occupancy (ticks) 545system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 546system.cpu.toL2Bus.respLayer1.occupancy 2193491412 # Layer occupancy (ticks) 547system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 548system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) 549system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 550system.cpu.toL2Bus.snoop_data_through_bus 13952 # Total snoop data (bytes) 551system.cpu.toL2Bus.throughput 125453578 # Throughput (bytes/s) 552system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93445952 # Cumulative packet size per connected master and slave (bytes) 553system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142932828 # Cumulative packet size per connected master and slave (bytes) 554system.cpu.toL2Bus.tot_pkt_size::total 236378780 # Cumulative packet size per connected master and slave (bytes) 555system.cpu.toL2Bus.trans_dist::ReadReq 2558221 # Transaction distribution 556system.cpu.toL2Bus.trans_dist::ReadResp 2558187 # Transaction distribution 557system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution 558system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution 559system.cpu.toL2Bus.trans_dist::Writeback 837448 # Transaction distribution 560system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution 561system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution 562system.cpu.toL2Bus.trans_dist::ReadExReq 345631 # Transaction distribution 563system.cpu.toL2Bus.trans_dist::ReadExResp 304081 # Transaction distribution 564system.cpu.toL2Bus.trans_dist::BadAddressError 17 # Transaction distribution 565system.cpu_clk_domain.clock 500 # Clock period in ticks 566system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 567system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 568system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 569system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 570system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 571system.disk0.dma_write_txs 395 # Number of DMA write transactions. 572system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 573system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 574system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 575system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 576system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 577system.disk2.dma_write_txs 1 # Number of DMA write transactions. 578system.iobus.data_through_bus 2705924 # Total data (bytes) | 543system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 544system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 545system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 546system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 547system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed 548system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 549system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed 550system.cpu.kern.callpal::swpipl 175516 91.22% 93.43% # number of callpals executed 551system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed 552system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 553system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 554system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 555system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 556system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed 557system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 558system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 559system.cpu.kern.callpal::total 192403 # number of callpals executed 560system.cpu.kern.mode_switch::kernel 5869 # number of protection mode switches 561system.cpu.kern.mode_switch::user 1735 # number of protection mode switches 562system.cpu.kern.mode_switch::idle 2100 # number of protection mode switches 563system.cpu.kern.mode_good::kernel 1905 564system.cpu.kern.mode_good::user 1735 565system.cpu.kern.mode_good::idle 170 566system.cpu.kern.mode_switch_good::kernel 0.324587 # fraction of useful protection mode switches 567system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 568system.cpu.kern.mode_switch_good::idle 0.080952 # fraction of useful protection mode switches 569system.cpu.kern.mode_switch_good::total 0.392622 # fraction of useful protection mode switches 570system.cpu.kern.mode_ticks::kernel 36214076000 1.92% 1.92% # number of ticks spent at the given mode 571system.cpu.kern.mode_ticks::user 4058025000 0.22% 2.14% # number of ticks spent at the given mode 572system.cpu.kern.mode_ticks::idle 1843935646500 97.86% 100.00% # number of ticks spent at the given mode 573system.cpu.kern.swap_context 4178 # number of times the context was actually changed 574system.cpu.tickCycles 85802593 # Number of cycles that the object actually ticked 575system.cpu.idleCycles 91013233 # Total number of cycles that the object has spent stopped 576system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 577system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 578system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 579system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 580system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 581system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 582system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 583system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 584system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 585system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 586system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 587system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 588system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 589system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 590system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 591system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 592system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 593system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 594system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 595system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 596system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 597system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 598system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 599system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 600system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 601system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 602system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 603system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 604system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 605system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 606system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 607system.iobus.throughput 1436106 # Throughput (bytes/s) 608system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 609system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 610system.iobus.trans_dist::WriteReq 51171 # Transaction distribution 611system.iobus.trans_dist::WriteResp 51171 # Transaction distribution |
| 579system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes) 580system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 581system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 582system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 583system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 584system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 585system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 586system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 587system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 588system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 589system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 590system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 591system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes) 592system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 593system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 594system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes) | 612system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes) 613system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 614system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 615system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 616system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 617system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 618system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 619system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 620system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 621system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 622system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 623system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 624system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes) 625system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 626system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 627system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes) |
| 628system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 640system.iobus.tot_pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes) 641system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 642system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 643system.iobus.tot_pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes) 644system.iobus.data_through_bus 2705924 # Total data (bytes) |
|
| 595system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks) 596system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 597system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 598system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 599system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 600system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 645system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks) 646system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 647system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 648system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 649system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 650system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 651system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 652system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) |
|
| 601system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 602system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 603system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 604system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 605system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 606system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 607system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 608system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 609system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 610system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 611system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 612system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 613system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 614system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 653system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 654system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 655system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 656system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 657system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 658system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 659system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 660system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 662system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 663system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 664system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 665system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 666system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 615system.iobus.reqLayer29.occupancy 380176812 # Layer occupancy (ticks) | 667system.iobus.reqLayer29.occupancy 380105365 # Layer occupancy (ticks) |
| 616system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 617system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 618system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | 668system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 669system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 670system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) |
| 619system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 620system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) | |
| 621system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) 622system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 671system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) 672system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 623system.iobus.respLayer1.occupancy 43191500 # Layer occupancy (ticks) | 673system.iobus.respLayer1.occupancy 43180001 # Layer occupancy (ticks) |
| 624system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 674system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 625system.iobus.throughput 1436095 # Throughput (bytes/s) 626system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.tot_pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 640system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 641system.iobus.tot_pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes) 642system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 643system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 644system.iobus.trans_dist::WriteReq 51171 # Transaction distribution 645system.iobus.trans_dist::WriteResp 51171 # Transaction distribution 646system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 647system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 648system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency 649system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency 650system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency 651system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency 652system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles 653system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles 654system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 655system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 656system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 657system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 658system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles 659system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles 660system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 661system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 662system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 663system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 664system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 665system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 666system.iocache.WriteReq_avg_miss_latency::tsunami.ide 301458.532177 # average WriteReq miss latency 667system.iocache.WriteReq_avg_miss_latency::total 301458.532177 # average WriteReq miss latency 668system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 249403.998099 # average WriteReq mshr miss latency 669system.iocache.WriteReq_avg_mshr_miss_latency::total 249403.998099 # average WriteReq mshr miss latency 670system.iocache.WriteReq_miss_latency::tsunami.ide 12526204929 # number of WriteReq miss cycles 671system.iocache.WriteReq_miss_latency::total 12526204929 # number of WriteReq miss cycles 672system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 673system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 674system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 675system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 676system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10363234929 # number of WriteReq MSHR miss cycles 677system.iocache.WriteReq_mshr_miss_latency::total 10363234929 # number of WriteReq MSHR miss cycles 678system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 679system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 680system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 681system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 682system.iocache.avg_blocked_cycles::no_mshrs 12.981557 # average number of cycles each access was blocked 683system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 684system.iocache.blocked::no_mshrs 28683 # number of cycles access was blocked 685system.iocache.blocked::no_targets 0 # number of cycles access was blocked 686system.iocache.blocked_cycles::no_mshrs 372350 # number of cycles access was blocked 687system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 688system.iocache.cache_copies 0 # number of cache copies performed 689system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 690system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 691system.iocache.demand_avg_miss_latency::tsunami.ide 300715.142289 # average overall miss latency 692system.iocache.demand_avg_miss_latency::total 300715.142289 # average overall miss latency 693system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248660.810354 # average overall mshr miss latency 694system.iocache.demand_avg_mshr_miss_latency::total 248660.810354 # average overall mshr miss latency 695system.iocache.demand_miss_latency::tsunami.ide 12547339312 # number of demand (read+write) miss cycles 696system.iocache.demand_miss_latency::total 12547339312 # number of demand (read+write) miss cycles 697system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 698system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 699system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 700system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 701system.iocache.demand_mshr_miss_latency::tsunami.ide 10375372312 # number of demand (read+write) MSHR miss cycles 702system.iocache.demand_mshr_miss_latency::total 10375372312 # number of demand (read+write) MSHR miss cycles 703system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 704system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 705system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 706system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 707system.iocache.fast_writes 0 # number of fast writes performed 708system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 709system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 710system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 711system.iocache.overall_avg_miss_latency::tsunami.ide 300715.142289 # average overall miss latency 712system.iocache.overall_avg_miss_latency::total 300715.142289 # average overall miss latency 713system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248660.810354 # average overall mshr miss latency 714system.iocache.overall_avg_mshr_miss_latency::total 248660.810354 # average overall mshr miss latency 715system.iocache.overall_miss_latency::tsunami.ide 12547339312 # number of overall miss cycles 716system.iocache.overall_miss_latency::total 12547339312 # number of overall miss cycles 717system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 718system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 719system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 720system.iocache.overall_misses::total 41725 # number of overall misses 721system.iocache.overall_mshr_miss_latency::tsunami.ide 10375372312 # number of overall MSHR miss cycles 722system.iocache.overall_mshr_miss_latency::total 10375372312 # number of overall MSHR miss cycles 723system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 724system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 725system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 726system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 727system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 728system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 729system.iocache.tags.data_accesses 375525 # Number of data accesses 730system.iocache.tags.occ_blocks::tsunami.ide 1.296002 # Average occupied blocks per requestor 731system.iocache.tags.occ_percent::tsunami.ide 0.081000 # Average percentage of cache occupancy 732system.iocache.tags.occ_percent::total 0.081000 # Average percentage of cache occupancy 733system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 734system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 735system.iocache.tags.replacements 41685 # number of replacements 736system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 737system.iocache.tags.tag_accesses 375525 # Number of tag accesses 738system.iocache.tags.tagsinuse 1.296002 # Cycle average of tags in use 739system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 740system.iocache.tags.warmup_cycle 1728023406000 # Cycle when the warmup percentage was hit. 741system.iocache.writebacks::writebacks 41512 # number of writebacks 742system.iocache.writebacks::total 41512 # number of writebacks 743system.membus.data_through_bus 36171420 # Total data (bytes) 744system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) 745system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887021 # Packet count per connected master and slave (bytes) 746system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 34 # Packet count per connected master and slave (bytes) 747system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920153 # Packet count per connected master and slave (bytes) 748system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) 749system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) 750system.membus.pkt_count::total 1044833 # Packet count per connected master and slave (bytes) 751system.membus.reqLayer0.occupancy 29924500 # Layer occupancy (ticks) 752system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 753system.membus.reqLayer1.occupancy 1588463750 # Layer occupancy (ticks) 754system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 755system.membus.reqLayer2.occupancy 21000 # Layer occupancy (ticks) 756system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 757system.membus.respLayer1.occupancy 3825251579 # Layer occupancy (ticks) 758system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 759system.membus.respLayer2.occupancy 376658500 # Layer occupancy (ticks) 760system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 761system.membus.snoop_data_through_bus 35520 # Total snoop data (bytes) 762system.membus.throughput 19215838 # Throughput (bytes/s) 763system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) 764system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30817984 # Cumulative packet size per connected master and slave (bytes) 765system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30862300 # Cumulative packet size per connected master and slave (bytes) 766system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) 767system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) 768system.membus.tot_pkt_size::total 36171420 # Cumulative packet size per connected master and slave (bytes) 769system.membus.trans_dist::ReadReq 295752 # Transaction distribution 770system.membus.trans_dist::ReadResp 295735 # Transaction distribution 771system.membus.trans_dist::WriteReq 9619 # Transaction distribution 772system.membus.trans_dist::WriteResp 9619 # Transaction distribution 773system.membus.trans_dist::Writeback 118132 # Transaction distribution 774system.membus.trans_dist::UpgradeReq 154 # Transaction distribution 775system.membus.trans_dist::UpgradeResp 154 # Transaction distribution 776system.membus.trans_dist::ReadExReq 158104 # Transaction distribution 777system.membus.trans_dist::ReadExResp 158104 # Transaction distribution 778system.membus.trans_dist::BadAddressError 17 # Transaction distribution 779system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 780system.physmem.avgGap 3337930.50 # Average gap between requests 781system.physmem.avgMemAccLat 35387.14 # Average memory access latency per DRAM burst 782system.physmem.avgQLat 16637.14 # Average queueing delay per DRAM burst 783system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s 784system.physmem.avgRdBWSys 15.16 # Average system read bandwidth in MiByte/s 785system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 786system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s 787system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s 788system.physmem.avgWrQLen 25.04 # Average write queue length when enqueuing 789system.physmem.busUtil 0.15 # Data bus utilization in percentage 790system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 791system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 792system.physmem.bw_inst_read::cpu.inst 558643 # Instruction read bandwidth from this memory (bytes/s) 793system.physmem.bw_inst_read::total 558643 # Instruction read bandwidth from this memory (bytes/s) 794system.physmem.bw_read::cpu.inst 13753305 # Total read bandwidth from this memory (bytes/s) 795system.physmem.bw_read::tsunami.ide 1407663 # Total read bandwidth from this memory (bytes/s) 796system.physmem.bw_read::total 15160967 # Total read bandwidth from this memory (bytes/s) 797system.physmem.bw_total::writebacks 4012500 # Total bandwidth to/from this memory (bytes/s) 798system.physmem.bw_total::cpu.inst 13753305 # Total bandwidth to/from this memory (bytes/s) 799system.physmem.bw_total::tsunami.ide 1407663 # Total bandwidth to/from this memory (bytes/s) 800system.physmem.bw_total::total 19173467 # Total bandwidth to/from this memory (bytes/s) 801system.physmem.bw_write::writebacks 4012500 # Write bandwidth from this memory (bytes/s) 802system.physmem.bw_write::total 4012500 # Write bandwidth from this memory (bytes/s) 803system.physmem.bytesPerActivate::samples 65544 # Bytes accessed per row activation 804system.physmem.bytesPerActivate::mean 551.049921 # Bytes accessed per row activation 805system.physmem.bytesPerActivate::gmean 339.619427 # Bytes accessed per row activation 806system.physmem.bytesPerActivate::stdev 417.892498 # Bytes accessed per row activation 807system.physmem.bytesPerActivate::0-127 14350 21.89% 21.89% # Bytes accessed per row activation 808system.physmem.bytesPerActivate::128-255 10693 16.31% 38.21% # Bytes accessed per row activation 809system.physmem.bytesPerActivate::256-383 5022 7.66% 45.87% # Bytes accessed per row activation 810system.physmem.bytesPerActivate::384-511 3000 4.58% 50.45% # Bytes accessed per row activation 811system.physmem.bytesPerActivate::512-639 2439 3.72% 54.17% # Bytes accessed per row activation 812system.physmem.bytesPerActivate::640-767 2123 3.24% 57.41% # Bytes accessed per row activation 813system.physmem.bytesPerActivate::768-895 1392 2.12% 59.53% # Bytes accessed per row activation 814system.physmem.bytesPerActivate::896-1023 1695 2.59% 62.12% # Bytes accessed per row activation 815system.physmem.bytesPerActivate::1024-1151 24830 37.88% 100.00% # Bytes accessed per row activation 816system.physmem.bytesPerActivate::total 65544 # Bytes accessed per row activation 817system.physmem.bytesReadDRAM 28559488 # Total number of bytes read from DRAM 818system.physmem.bytesReadSys 28566656 # Total read bytes from the system interface side 819system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue 820system.physmem.bytesWritten 7558528 # Total number of bytes written to DRAM 821system.physmem.bytesWrittenSys 7560448 # Total written bytes from the system interface side 822system.physmem.bytes_inst_read::cpu.inst 1052608 # Number of instructions bytes read from this memory 823system.physmem.bytes_inst_read::total 1052608 # Number of instructions bytes read from this memory 824system.physmem.bytes_read::cpu.inst 25914304 # Number of bytes read from this memory 825system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 826system.physmem.bytes_read::total 28566656 # Number of bytes read from this memory 827system.physmem.bytes_written::writebacks 7560448 # Number of bytes written to this memory 828system.physmem.bytes_written::total 7560448 # Number of bytes written to this memory 829system.physmem.memoryStateTime::IDLE 1774858406250 # Time in different power states 830system.physmem.memoryStateTime::REF 62918180000 # Time in different power states 831system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 832system.physmem.memoryStateTime::ACT 46441683750 # Time in different power states 833system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 834system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 835system.physmem.neitherReadNorWriteReqs 152 # Number of requests that are neither read nor write 836system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 837system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 838system.physmem.num_reads::cpu.inst 404911 # Number of read requests responded to by this memory 839system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory 840system.physmem.num_reads::total 446354 # Number of read requests responded to by this memory 841system.physmem.num_writes::writebacks 118132 # Number of write requests responded to by this memory 842system.physmem.num_writes::total 118132 # Number of write requests responded to by this memory 843system.physmem.pageHitRate 88.38 # Row buffer hit rate, read and write combined 844system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 845system.physmem.perBankRdBursts::0 28089 # Per bank write bursts 846system.physmem.perBankRdBursts::1 28214 # Per bank write bursts 847system.physmem.perBankRdBursts::2 28576 # Per bank write bursts 848system.physmem.perBankRdBursts::3 28273 # Per bank write bursts 849system.physmem.perBankRdBursts::4 27773 # Per bank write bursts 850system.physmem.perBankRdBursts::5 27528 # Per bank write bursts 851system.physmem.perBankRdBursts::6 27276 # Per bank write bursts 852system.physmem.perBankRdBursts::7 26988 # Per bank write bursts 853system.physmem.perBankRdBursts::8 27824 # Per bank write bursts 854system.physmem.perBankRdBursts::9 27526 # Per bank write bursts 855system.physmem.perBankRdBursts::10 28068 # Per bank write bursts 856system.physmem.perBankRdBursts::11 27422 # Per bank write bursts 857system.physmem.perBankRdBursts::12 27509 # Per bank write bursts 858system.physmem.perBankRdBursts::13 28403 # Per bank write bursts 859system.physmem.perBankRdBursts::14 28310 # Per bank write bursts 860system.physmem.perBankRdBursts::15 28463 # Per bank write bursts 861system.physmem.perBankWrBursts::0 7815 # Per bank write bursts 862system.physmem.perBankWrBursts::1 7669 # Per bank write bursts 863system.physmem.perBankWrBursts::2 8056 # Per bank write bursts 864system.physmem.perBankWrBursts::3 7732 # Per bank write bursts 865system.physmem.perBankWrBursts::4 7316 # Per bank write bursts 866system.physmem.perBankWrBursts::5 6956 # Per bank write bursts 867system.physmem.perBankWrBursts::6 6791 # Per bank write bursts 868system.physmem.perBankWrBursts::7 6409 # Per bank write bursts 869system.physmem.perBankWrBursts::8 7232 # Per bank write bursts 870system.physmem.perBankWrBursts::9 6875 # Per bank write bursts 871system.physmem.perBankWrBursts::10 7393 # Per bank write bursts 872system.physmem.perBankWrBursts::11 6865 # Per bank write bursts 873system.physmem.perBankWrBursts::12 7044 # Per bank write bursts 874system.physmem.perBankWrBursts::13 8010 # Per bank write bursts 875system.physmem.perBankWrBursts::14 7992 # Per bank write bursts 876system.physmem.perBankWrBursts::15 7947 # Per bank write bursts 877system.physmem.rdPerTurnAround::samples 6969 # Reads before turning the bus around for writes 878system.physmem.rdPerTurnAround::mean 64.029703 # Reads before turning the bus around for writes 879system.physmem.rdPerTurnAround::gmean 16.504435 # Reads before turning the bus around for writes 880system.physmem.rdPerTurnAround::stdev 2530.006276 # Reads before turning the bus around for writes 881system.physmem.rdPerTurnAround::0-8191 6966 99.96% 99.96% # Reads before turning the bus around for writes 882system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 883system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 884system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes 885system.physmem.rdPerTurnAround::total 6969 # Reads before turning the bus around for writes 886system.physmem.rdQLenPdf::0 402867 # What read queue length does an incoming req see 887system.physmem.rdQLenPdf::1 3807 # What read queue length does an incoming req see 888system.physmem.rdQLenPdf::2 2662 # What read queue length does an incoming req see 889system.physmem.rdQLenPdf::3 1230 # What read queue length does an incoming req see 890system.physmem.rdQLenPdf::4 1958 # What read queue length does an incoming req see 891system.physmem.rdQLenPdf::5 4351 # What read queue length does an incoming req see 892system.physmem.rdQLenPdf::6 3967 # What read queue length does an incoming req see 893system.physmem.rdQLenPdf::7 4001 # What read queue length does an incoming req see 894system.physmem.rdQLenPdf::8 2558 # What read queue length does an incoming req see 895system.physmem.rdQLenPdf::9 2209 # What read queue length does an incoming req see 896system.physmem.rdQLenPdf::10 2170 # What read queue length does an incoming req see 897system.physmem.rdQLenPdf::11 2129 # What read queue length does an incoming req see 898system.physmem.rdQLenPdf::12 1643 # What read queue length does an incoming req see 899system.physmem.rdQLenPdf::13 1639 # What read queue length does an incoming req see 900system.physmem.rdQLenPdf::14 1928 # What read queue length does an incoming req see 901system.physmem.rdQLenPdf::15 1884 # What read queue length does an incoming req see 902system.physmem.rdQLenPdf::16 2114 # What read queue length does an incoming req see 903system.physmem.rdQLenPdf::17 1233 # What read queue length does an incoming req see 904system.physmem.rdQLenPdf::18 977 # What read queue length does an incoming req see 905system.physmem.rdQLenPdf::19 904 # What read queue length does an incoming req see 906system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see 907system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 908system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 909system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 910system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 911system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 912system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 913system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 914system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 915system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 916system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 917system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 918system.physmem.readBursts 446354 # Number of DRAM read bursts, including those serviced by the write queue 919system.physmem.readPktSize::0 0 # Read request sizes (log2) 920system.physmem.readPktSize::1 0 # Read request sizes (log2) 921system.physmem.readPktSize::2 0 # Read request sizes (log2) 922system.physmem.readPktSize::3 0 # Read request sizes (log2) 923system.physmem.readPktSize::4 0 # Read request sizes (log2) 924system.physmem.readPktSize::5 0 # Read request sizes (log2) 925system.physmem.readPktSize::6 446354 # Read request sizes (log2) 926system.physmem.readReqs 446354 # Number of read requests accepted 927system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads 928system.physmem.readRowHits 402699 # Number of row buffer hits during reads 929system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue 930system.physmem.totBusLat 2231210000 # Total ticks spent in databus transfers 931system.physmem.totGap 1884215033500 # Total gap between requests 932system.physmem.totMemAccLat 15791226000 # Total ticks spent from burst creation until serviced by the DRAM 933system.physmem.totQLat 7424188500 # Total ticks spent queuing 934system.physmem.wrPerTurnAround::samples 6969 # Writes before turning the bus around for reads 935system.physmem.wrPerTurnAround::mean 16.946764 # Writes before turning the bus around for reads 936system.physmem.wrPerTurnAround::gmean 16.727841 # Writes before turning the bus around for reads 937system.physmem.wrPerTurnAround::stdev 3.644099 # Writes before turning the bus around for reads 938system.physmem.wrPerTurnAround::16 5693 81.69% 81.69% # Writes before turning the bus around for reads 939system.physmem.wrPerTurnAround::17 31 0.44% 82.14% # Writes before turning the bus around for reads 940system.physmem.wrPerTurnAround::18 825 11.84% 93.97% # Writes before turning the bus around for reads 941system.physmem.wrPerTurnAround::19 64 0.92% 94.89% # Writes before turning the bus around for reads 942system.physmem.wrPerTurnAround::20 11 0.16% 95.05% # Writes before turning the bus around for reads 943system.physmem.wrPerTurnAround::21 13 0.19% 95.24% # Writes before turning the bus around for reads 944system.physmem.wrPerTurnAround::22 18 0.26% 95.49% # Writes before turning the bus around for reads 945system.physmem.wrPerTurnAround::23 88 1.26% 96.76% # Writes before turning the bus around for reads 946system.physmem.wrPerTurnAround::24 18 0.26% 97.02% # Writes before turning the bus around for reads 947system.physmem.wrPerTurnAround::25 42 0.60% 97.62% # Writes before turning the bus around for reads 948system.physmem.wrPerTurnAround::26 18 0.26% 97.88% # Writes before turning the bus around for reads 949system.physmem.wrPerTurnAround::27 17 0.24% 98.12% # Writes before turning the bus around for reads 950system.physmem.wrPerTurnAround::28 12 0.17% 98.29% # Writes before turning the bus around for reads 951system.physmem.wrPerTurnAround::29 10 0.14% 98.44% # Writes before turning the bus around for reads 952system.physmem.wrPerTurnAround::30 5 0.07% 98.51% # Writes before turning the bus around for reads 953system.physmem.wrPerTurnAround::31 20 0.29% 98.79% # Writes before turning the bus around for reads 954system.physmem.wrPerTurnAround::32 11 0.16% 98.95% # Writes before turning the bus around for reads 955system.physmem.wrPerTurnAround::34 4 0.06% 99.01% # Writes before turning the bus around for reads 956system.physmem.wrPerTurnAround::35 1 0.01% 99.02% # Writes before turning the bus around for reads 957system.physmem.wrPerTurnAround::36 5 0.07% 99.10% # Writes before turning the bus around for reads 958system.physmem.wrPerTurnAround::37 3 0.04% 99.14% # Writes before turning the bus around for reads 959system.physmem.wrPerTurnAround::38 1 0.01% 99.15% # Writes before turning the bus around for reads 960system.physmem.wrPerTurnAround::39 1 0.01% 99.17% # Writes before turning the bus around for reads 961system.physmem.wrPerTurnAround::40 4 0.06% 99.23% # Writes before turning the bus around for reads 962system.physmem.wrPerTurnAround::41 6 0.09% 99.31% # Writes before turning the bus around for reads 963system.physmem.wrPerTurnAround::42 2 0.03% 99.34% # Writes before turning the bus around for reads 964system.physmem.wrPerTurnAround::43 5 0.07% 99.41% # Writes before turning the bus around for reads 965system.physmem.wrPerTurnAround::44 3 0.04% 99.45% # Writes before turning the bus around for reads 966system.physmem.wrPerTurnAround::45 2 0.03% 99.48% # Writes before turning the bus around for reads 967system.physmem.wrPerTurnAround::46 1 0.01% 99.50% # Writes before turning the bus around for reads 968system.physmem.wrPerTurnAround::47 5 0.07% 99.57% # Writes before turning the bus around for reads 969system.physmem.wrPerTurnAround::48 2 0.03% 99.60% # Writes before turning the bus around for reads 970system.physmem.wrPerTurnAround::49 5 0.07% 99.67% # Writes before turning the bus around for reads 971system.physmem.wrPerTurnAround::50 3 0.04% 99.71% # Writes before turning the bus around for reads 972system.physmem.wrPerTurnAround::51 1 0.01% 99.73% # Writes before turning the bus around for reads 973system.physmem.wrPerTurnAround::52 3 0.04% 99.77% # Writes before turning the bus around for reads 974system.physmem.wrPerTurnAround::53 1 0.01% 99.78% # Writes before turning the bus around for reads 975system.physmem.wrPerTurnAround::56 5 0.07% 99.86% # Writes before turning the bus around for reads 976system.physmem.wrPerTurnAround::57 7 0.10% 99.96% # Writes before turning the bus around for reads 977system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads 978system.physmem.wrPerTurnAround::total 6969 # Writes before turning the bus around for reads 979system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 980system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 981system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 982system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 983system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 984system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 985system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 986system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 987system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 988system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 989system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 990system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 991system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 992system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 993system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 994system.physmem.wrQLenPdf::15 1009 # What write queue length does an incoming req see 995system.physmem.wrQLenPdf::16 1042 # What write queue length does an incoming req see 996system.physmem.wrQLenPdf::17 4658 # What write queue length does an incoming req see 997system.physmem.wrQLenPdf::18 4777 # What write queue length does an incoming req see 998system.physmem.wrQLenPdf::19 4795 # What write queue length does an incoming req see 999system.physmem.wrQLenPdf::20 4798 # What write queue length does an incoming req see 1000system.physmem.wrQLenPdf::21 4808 # What write queue length does an incoming req see 1001system.physmem.wrQLenPdf::22 4914 # What write queue length does an incoming req see 1002system.physmem.wrQLenPdf::23 5074 # What write queue length does an incoming req see 1003system.physmem.wrQLenPdf::24 5164 # What write queue length does an incoming req see 1004system.physmem.wrQLenPdf::25 5341 # What write queue length does an incoming req see 1005system.physmem.wrQLenPdf::26 5549 # What write queue length does an incoming req see 1006system.physmem.wrQLenPdf::27 5533 # What write queue length does an incoming req see 1007system.physmem.wrQLenPdf::28 5670 # What write queue length does an incoming req see 1008system.physmem.wrQLenPdf::29 5729 # What write queue length does an incoming req see 1009system.physmem.wrQLenPdf::30 5848 # What write queue length does an incoming req see 1010system.physmem.wrQLenPdf::31 5831 # What write queue length does an incoming req see 1011system.physmem.wrQLenPdf::32 5897 # What write queue length does an incoming req see 1012system.physmem.wrQLenPdf::33 883 # What write queue length does an incoming req see 1013system.physmem.wrQLenPdf::34 930 # What write queue length does an incoming req see 1014system.physmem.wrQLenPdf::35 931 # What write queue length does an incoming req see 1015system.physmem.wrQLenPdf::36 875 # What write queue length does an incoming req see 1016system.physmem.wrQLenPdf::37 964 # What write queue length does an incoming req see 1017system.physmem.wrQLenPdf::38 972 # What write queue length does an incoming req see 1018system.physmem.wrQLenPdf::39 1055 # What write queue length does an incoming req see 1019system.physmem.wrQLenPdf::40 993 # What write queue length does an incoming req see 1020system.physmem.wrQLenPdf::41 1195 # What write queue length does an incoming req see 1021system.physmem.wrQLenPdf::42 1241 # What write queue length does an incoming req see 1022system.physmem.wrQLenPdf::43 1213 # What write queue length does an incoming req see 1023system.physmem.wrQLenPdf::44 1337 # What write queue length does an incoming req see 1024system.physmem.wrQLenPdf::45 1445 # What write queue length does an incoming req see 1025system.physmem.wrQLenPdf::46 1603 # What write queue length does an incoming req see 1026system.physmem.wrQLenPdf::47 1865 # What write queue length does an incoming req see 1027system.physmem.wrQLenPdf::48 2061 # What write queue length does an incoming req see 1028system.physmem.wrQLenPdf::49 1878 # What write queue length does an incoming req see 1029system.physmem.wrQLenPdf::50 1829 # What write queue length does an incoming req see 1030system.physmem.wrQLenPdf::51 1679 # What write queue length does an incoming req see 1031system.physmem.wrQLenPdf::52 1682 # What write queue length does an incoming req see 1032system.physmem.wrQLenPdf::53 1830 # What write queue length does an incoming req see 1033system.physmem.wrQLenPdf::54 1627 # What write queue length does an incoming req see 1034system.physmem.wrQLenPdf::55 808 # What write queue length does an incoming req see 1035system.physmem.wrQLenPdf::56 356 # What write queue length does an incoming req see 1036system.physmem.wrQLenPdf::57 190 # What write queue length does an incoming req see 1037system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see 1038system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see 1039system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see 1040system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see 1041system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 1042system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see 1043system.physmem.writeBursts 118132 # Number of DRAM write bursts, including those merged in the write queue 1044system.physmem.writePktSize::0 0 # Write request sizes (log2) 1045system.physmem.writePktSize::1 0 # Write request sizes (log2) 1046system.physmem.writePktSize::2 0 # Write request sizes (log2) 1047system.physmem.writePktSize::3 0 # Write request sizes (log2) 1048system.physmem.writePktSize::4 0 # Write request sizes (log2) 1049system.physmem.writePktSize::5 0 # Write request sizes (log2) 1050system.physmem.writePktSize::6 118132 # Write request sizes (log2) 1051system.physmem.writeReqs 118132 # Number of write requests accepted 1052system.physmem.writeRowHitRate 81.35 # Row buffer hit rate for writes 1053system.physmem.writeRowHits 96101 # Number of row buffer hits during writes 1054system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1055system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1056system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1057system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1058system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1059system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1060system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1061system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1062system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1063system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1064system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1065system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1066system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1067system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1068system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1069system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1070system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1071system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1072system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1073system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1074system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1075system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1076system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1077system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1078system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1079system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1080system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1081system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1082system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1083system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1084system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1085system.voltage_domain.voltage 1 # Voltage in Volts | 675system.cpu.icache.tags.replacements 1458006 # number of replacements 676system.cpu.icache.tags.tagsinuse 509.628197 # Cycle average of tags in use 677system.cpu.icache.tags.total_refs 18953120 # Total number of references to valid blocks. 678system.cpu.icache.tags.sampled_refs 1458517 # Sample count of references to valid blocks. 679system.cpu.icache.tags.avg_refs 12.994789 # Average number of references to valid blocks. 680system.cpu.icache.tags.warmup_cycle 31559763000 # Cycle when the warmup percentage was hit. 681system.cpu.icache.tags.occ_blocks::cpu.inst 509.628197 # Average occupied blocks per requestor 682system.cpu.icache.tags.occ_percent::cpu.inst 0.995368 # Average percentage of cache occupancy 683system.cpu.icache.tags.occ_percent::total 0.995368 # Average percentage of cache occupancy 684system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 685system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 686system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id 688system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 689system.cpu.icache.tags.tag_accesses 21870509 # Number of tag accesses 690system.cpu.icache.tags.data_accesses 21870509 # Number of data accesses 691system.cpu.icache.ReadReq_hits::cpu.inst 18953123 # number of ReadReq hits 692system.cpu.icache.ReadReq_hits::total 18953123 # number of ReadReq hits 693system.cpu.icache.demand_hits::cpu.inst 18953123 # number of demand (read+write) hits 694system.cpu.icache.demand_hits::total 18953123 # number of demand (read+write) hits 695system.cpu.icache.overall_hits::cpu.inst 18953123 # number of overall hits 696system.cpu.icache.overall_hits::total 18953123 # number of overall hits 697system.cpu.icache.ReadReq_misses::cpu.inst 1458693 # number of ReadReq misses 698system.cpu.icache.ReadReq_misses::total 1458693 # number of ReadReq misses 699system.cpu.icache.demand_misses::cpu.inst 1458693 # number of demand (read+write) misses 700system.cpu.icache.demand_misses::total 1458693 # number of demand (read+write) misses 701system.cpu.icache.overall_misses::cpu.inst 1458693 # number of overall misses 702system.cpu.icache.overall_misses::total 1458693 # number of overall misses 703system.cpu.icache.ReadReq_miss_latency::cpu.inst 20024605540 # number of ReadReq miss cycles 704system.cpu.icache.ReadReq_miss_latency::total 20024605540 # number of ReadReq miss cycles 705system.cpu.icache.demand_miss_latency::cpu.inst 20024605540 # number of demand (read+write) miss cycles 706system.cpu.icache.demand_miss_latency::total 20024605540 # number of demand (read+write) miss cycles 707system.cpu.icache.overall_miss_latency::cpu.inst 20024605540 # number of overall miss cycles 708system.cpu.icache.overall_miss_latency::total 20024605540 # number of overall miss cycles 709system.cpu.icache.ReadReq_accesses::cpu.inst 20411816 # number of ReadReq accesses(hits+misses) 710system.cpu.icache.ReadReq_accesses::total 20411816 # number of ReadReq accesses(hits+misses) 711system.cpu.icache.demand_accesses::cpu.inst 20411816 # number of demand (read+write) accesses 712system.cpu.icache.demand_accesses::total 20411816 # number of demand (read+write) accesses 713system.cpu.icache.overall_accesses::cpu.inst 20411816 # number of overall (read+write) accesses 714system.cpu.icache.overall_accesses::total 20411816 # number of overall (read+write) accesses 715system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071463 # miss rate for ReadReq accesses 716system.cpu.icache.ReadReq_miss_rate::total 0.071463 # miss rate for ReadReq accesses 717system.cpu.icache.demand_miss_rate::cpu.inst 0.071463 # miss rate for demand accesses 718system.cpu.icache.demand_miss_rate::total 0.071463 # miss rate for demand accesses 719system.cpu.icache.overall_miss_rate::cpu.inst 0.071463 # miss rate for overall accesses 720system.cpu.icache.overall_miss_rate::total 0.071463 # miss rate for overall accesses 721system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.772424 # average ReadReq miss latency 722system.cpu.icache.ReadReq_avg_miss_latency::total 13727.772424 # average ReadReq miss latency 723system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.772424 # average overall miss latency 724system.cpu.icache.demand_avg_miss_latency::total 13727.772424 # average overall miss latency 725system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.772424 # average overall miss latency 726system.cpu.icache.overall_avg_miss_latency::total 13727.772424 # average overall miss latency 727system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 728system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 729system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 730system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 731system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 732system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 733system.cpu.icache.fast_writes 0 # number of fast writes performed 734system.cpu.icache.cache_copies 0 # number of cache copies performed 735system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458693 # number of ReadReq MSHR misses 736system.cpu.icache.ReadReq_mshr_misses::total 1458693 # number of ReadReq MSHR misses 737system.cpu.icache.demand_mshr_misses::cpu.inst 1458693 # number of demand (read+write) MSHR misses 738system.cpu.icache.demand_mshr_misses::total 1458693 # number of demand (read+write) MSHR misses 739system.cpu.icache.overall_mshr_misses::cpu.inst 1458693 # number of overall MSHR misses 740system.cpu.icache.overall_mshr_misses::total 1458693 # number of overall MSHR misses 741system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17099831460 # number of ReadReq MSHR miss cycles 742system.cpu.icache.ReadReq_mshr_miss_latency::total 17099831460 # number of ReadReq MSHR miss cycles 743system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17099831460 # number of demand (read+write) MSHR miss cycles 744system.cpu.icache.demand_mshr_miss_latency::total 17099831460 # number of demand (read+write) MSHR miss cycles 745system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17099831460 # number of overall MSHR miss cycles 746system.cpu.icache.overall_mshr_miss_latency::total 17099831460 # number of overall MSHR miss cycles 747system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for ReadReq accesses 748system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071463 # mshr miss rate for ReadReq accesses 749system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for demand accesses 750system.cpu.icache.demand_mshr_miss_rate::total 0.071463 # mshr miss rate for demand accesses 751system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for overall accesses 752system.cpu.icache.overall_mshr_miss_rate::total 0.071463 # mshr miss rate for overall accesses 753system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.707561 # average ReadReq mshr miss latency 754system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.707561 # average ReadReq mshr miss latency 755system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.707561 # average overall mshr miss latency 756system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.707561 # average overall mshr miss latency 757system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.707561 # average overall mshr miss latency 758system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.707561 # average overall mshr miss latency 759system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 760system.cpu.toL2Bus.throughput 125457945 # Throughput (bytes/s) 761system.cpu.toL2Bus.trans_dist::ReadReq 2557417 # Transaction distribution 762system.cpu.toL2Bus.trans_dist::ReadResp 2557383 # Transaction distribution 763system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution 764system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution 765system.cpu.toL2Bus.trans_dist::Writeback 838210 # Transaction distribution 766system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution 767system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution 768system.cpu.toL2Bus.trans_dist::ReadExReq 345773 # Transaction distribution 769system.cpu.toL2Bus.trans_dist::ReadExResp 304222 # Transaction distribution 770system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution 771system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917325 # Packet count per connected master and slave (bytes) 772system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663192 # Packet count per connected master and slave (bytes) 773system.cpu.toL2Bus.pkt_count::total 6580517 # Packet count per connected master and slave (bytes) 774system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352448 # Cumulative packet size per connected master and slave (bytes) 775system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143032604 # Cumulative packet size per connected master and slave (bytes) 776system.cpu.toL2Bus.tot_pkt_size::total 236385052 # Cumulative packet size per connected master and slave (bytes) 777system.cpu.toL2Bus.data_through_bus 236375068 # Total data (bytes) 778system.cpu.toL2Bus.snoop_data_through_bus 13888 # Total snoop data (bytes) 779system.cpu.toL2Bus.reqLayer0.occupancy 2697678498 # Layer occupancy (ticks) 780system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 781system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 782system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 783system.cpu.toL2Bus.respLayer0.occupancy 2191733540 # Layer occupancy (ticks) 784system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 785system.cpu.toL2Bus.respLayer1.occupancy 2194708666 # Layer occupancy (ticks) 786system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 787system.cpu.l2cache.tags.replacements 339421 # number of replacements 788system.cpu.l2cache.tags.tagsinuse 65326.541432 # Cycle average of tags in use 789system.cpu.l2cache.tags.total_refs 2981708 # Total number of references to valid blocks. 790system.cpu.l2cache.tags.sampled_refs 404583 # Sample count of references to valid blocks. 791system.cpu.l2cache.tags.avg_refs 7.369830 # Average number of references to valid blocks. 792system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit. 793system.cpu.l2cache.tags.occ_blocks::writebacks 54488.510247 # Average occupied blocks per requestor 794system.cpu.l2cache.tags.occ_blocks::cpu.inst 10838.031185 # Average occupied blocks per requestor 795system.cpu.l2cache.tags.occ_percent::writebacks 0.831429 # Average percentage of cache occupancy 796system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165375 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::total 0.996804 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 799system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1468 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5155 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2781 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id 804system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id 805system.cpu.l2cache.tags.tag_accesses 30250697 # Number of tag accesses 806system.cpu.l2cache.tags.data_accesses 30250697 # Number of data accesses 807system.cpu.l2cache.ReadReq_hits::cpu.inst 2261599 # number of ReadReq hits 808system.cpu.l2cache.ReadReq_hits::total 2261599 # number of ReadReq hits 809system.cpu.l2cache.Writeback_hits::writebacks 838210 # number of Writeback hits 810system.cpu.l2cache.Writeback_hits::total 838210 # number of Writeback hits 811system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits 812system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 813system.cpu.l2cache.ReadExReq_hits::cpu.inst 187541 # number of ReadExReq hits 814system.cpu.l2cache.ReadExReq_hits::total 187541 # number of ReadExReq hits 815system.cpu.l2cache.demand_hits::cpu.inst 2449140 # number of demand (read+write) hits 816system.cpu.l2cache.demand_hits::total 2449140 # number of demand (read+write) hits 817system.cpu.l2cache.overall_hits::cpu.inst 2449140 # number of overall hits 818system.cpu.l2cache.overall_hits::total 2449140 # number of overall hits 819system.cpu.l2cache.ReadReq_misses::cpu.inst 288654 # number of ReadReq misses 820system.cpu.l2cache.ReadReq_misses::total 288654 # number of ReadReq misses 821system.cpu.l2cache.UpgradeReq_misses::cpu.inst 18 # number of UpgradeReq misses 822system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses 823system.cpu.l2cache.ReadExReq_misses::cpu.inst 116680 # number of ReadExReq misses 824system.cpu.l2cache.ReadExReq_misses::total 116680 # number of ReadExReq misses 825system.cpu.l2cache.demand_misses::cpu.inst 405334 # number of demand (read+write) misses 826system.cpu.l2cache.demand_misses::total 405334 # number of demand (read+write) misses 827system.cpu.l2cache.overall_misses::cpu.inst 405334 # number of overall misses 828system.cpu.l2cache.overall_misses::total 405334 # number of overall misses 829system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18918477985 # number of ReadReq miss cycles 830system.cpu.l2cache.ReadReq_miss_latency::total 18918477985 # number of ReadReq miss cycles 831system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 214497 # number of UpgradeReq miss cycles 832system.cpu.l2cache.UpgradeReq_miss_latency::total 214497 # number of UpgradeReq miss cycles 833system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8091487855 # number of ReadExReq miss cycles 834system.cpu.l2cache.ReadExReq_miss_latency::total 8091487855 # number of ReadExReq miss cycles 835system.cpu.l2cache.demand_miss_latency::cpu.inst 27009965840 # number of demand (read+write) miss cycles 836system.cpu.l2cache.demand_miss_latency::total 27009965840 # number of demand (read+write) miss cycles 837system.cpu.l2cache.overall_miss_latency::cpu.inst 27009965840 # number of overall miss cycles 838system.cpu.l2cache.overall_miss_latency::total 27009965840 # number of overall miss cycles 839system.cpu.l2cache.ReadReq_accesses::cpu.inst 2550253 # number of ReadReq accesses(hits+misses) 840system.cpu.l2cache.ReadReq_accesses::total 2550253 # number of ReadReq accesses(hits+misses) 841system.cpu.l2cache.Writeback_accesses::writebacks 838210 # number of Writeback accesses(hits+misses) 842system.cpu.l2cache.Writeback_accesses::total 838210 # number of Writeback accesses(hits+misses) 843system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 22 # number of UpgradeReq accesses(hits+misses) 844system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) 845system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304221 # number of ReadExReq accesses(hits+misses) 846system.cpu.l2cache.ReadExReq_accesses::total 304221 # number of ReadExReq accesses(hits+misses) 847system.cpu.l2cache.demand_accesses::cpu.inst 2854474 # number of demand (read+write) accesses 848system.cpu.l2cache.demand_accesses::total 2854474 # number of demand (read+write) accesses 849system.cpu.l2cache.overall_accesses::cpu.inst 2854474 # number of overall (read+write) accesses 850system.cpu.l2cache.overall_accesses::total 2854474 # number of overall (read+write) accesses 851system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113186 # miss rate for ReadReq accesses 852system.cpu.l2cache.ReadReq_miss_rate::total 0.113186 # miss rate for ReadReq accesses 853system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.818182 # miss rate for UpgradeReq accesses 854system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818182 # miss rate for UpgradeReq accesses 855system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383537 # miss rate for ReadExReq accesses 856system.cpu.l2cache.ReadExReq_miss_rate::total 0.383537 # miss rate for ReadExReq accesses 857system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142000 # miss rate for demand accesses 858system.cpu.l2cache.demand_miss_rate::total 0.142000 # miss rate for demand accesses 859system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142000 # miss rate for overall accesses 860system.cpu.l2cache.overall_miss_rate::total 0.142000 # miss rate for overall accesses 861system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65540.328507 # average ReadReq miss latency 862system.cpu.l2cache.ReadReq_avg_miss_latency::total 65540.328507 # average ReadReq miss latency 863system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11916.500000 # average UpgradeReq miss latency 864system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11916.500000 # average UpgradeReq miss latency 865system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69347.684736 # average ReadExReq miss latency 866system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69347.684736 # average ReadExReq miss latency 867system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66636.319282 # average overall miss latency 868system.cpu.l2cache.demand_avg_miss_latency::total 66636.319282 # average overall miss latency 869system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66636.319282 # average overall miss latency 870system.cpu.l2cache.overall_avg_miss_latency::total 66636.319282 # average overall miss latency 871system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 872system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 873system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 874system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 875system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 876system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 877system.cpu.l2cache.fast_writes 0 # number of fast writes performed 878system.cpu.l2cache.cache_copies 0 # number of cache copies performed 879system.cpu.l2cache.writebacks::writebacks 76620 # number of writebacks 880system.cpu.l2cache.writebacks::total 76620 # number of writebacks 881system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288654 # number of ReadReq MSHR misses 882system.cpu.l2cache.ReadReq_mshr_misses::total 288654 # number of ReadReq MSHR misses 883system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 18 # number of UpgradeReq MSHR misses 884system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses 885system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116680 # number of ReadExReq MSHR misses 886system.cpu.l2cache.ReadExReq_mshr_misses::total 116680 # number of ReadExReq MSHR misses 887system.cpu.l2cache.demand_mshr_misses::cpu.inst 405334 # number of demand (read+write) MSHR misses 888system.cpu.l2cache.demand_mshr_misses::total 405334 # number of demand (read+write) MSHR misses 889system.cpu.l2cache.overall_mshr_misses::cpu.inst 405334 # number of overall MSHR misses 890system.cpu.l2cache.overall_mshr_misses::total 405334 # number of overall MSHR misses 891system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15309737015 # number of ReadReq MSHR miss cycles 892system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15309737015 # number of ReadReq MSHR miss cycles 893system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 281515 # number of UpgradeReq MSHR miss cycles 894system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 281515 # number of UpgradeReq MSHR miss cycles 895system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6590751145 # number of ReadExReq MSHR miss cycles 896system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6590751145 # number of ReadExReq MSHR miss cycles 897system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21900488160 # number of demand (read+write) MSHR miss cycles 898system.cpu.l2cache.demand_mshr_miss_latency::total 21900488160 # number of demand (read+write) MSHR miss cycles 899system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21900488160 # number of overall MSHR miss cycles 900system.cpu.l2cache.overall_mshr_miss_latency::total 21900488160 # number of overall MSHR miss cycles 901system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333191500 # number of ReadReq MSHR uncacheable cycles 902system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333191500 # number of ReadReq MSHR uncacheable cycles 903system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887604500 # number of WriteReq MSHR uncacheable cycles 904system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887604500 # number of WriteReq MSHR uncacheable cycles 905system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3220796000 # number of overall MSHR uncacheable cycles 906system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3220796000 # number of overall MSHR uncacheable cycles 907system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113186 # mshr miss rate for ReadReq accesses 908system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113186 # mshr miss rate for ReadReq accesses 909system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.818182 # mshr miss rate for UpgradeReq accesses 910system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses 911system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383537 # mshr miss rate for ReadExReq accesses 912system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383537 # mshr miss rate for ReadExReq accesses 913system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142000 # mshr miss rate for demand accesses 914system.cpu.l2cache.demand_mshr_miss_rate::total 0.142000 # mshr miss rate for demand accesses 915system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142000 # mshr miss rate for overall accesses 916system.cpu.l2cache.overall_mshr_miss_rate::total 0.142000 # mshr miss rate for overall accesses 917system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53038.367786 # average ReadReq mshr miss latency 918system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53038.367786 # average ReadReq mshr miss latency 919system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15639.722222 # average UpgradeReq mshr miss latency 920system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15639.722222 # average UpgradeReq mshr miss latency 921system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56485.697163 # average ReadExReq mshr miss latency 922system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56485.697163 # average ReadExReq mshr miss latency 923system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54030.720739 # average overall mshr miss latency 924system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54030.720739 # average overall mshr miss latency 925system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54030.720739 # average overall mshr miss latency 926system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54030.720739 # average overall mshr miss latency 927system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 928system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 929system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 930system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 931system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 932system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 933system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 934system.cpu.dcache.tags.replacements 1395313 # number of replacements 935system.cpu.dcache.tags.tagsinuse 511.982337 # Cycle average of tags in use 936system.cpu.dcache.tags.total_refs 13766743 # Total number of references to valid blocks. 937system.cpu.dcache.tags.sampled_refs 1395825 # Sample count of references to valid blocks. 938system.cpu.dcache.tags.avg_refs 9.862800 # Average number of references to valid blocks. 939system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit. 940system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982337 # Average occupied blocks per requestor 941system.cpu.dcache.tags.occ_percent::cpu.inst 0.999966 # Average percentage of cache occupancy 942system.cpu.dcache.tags.occ_percent::total 0.999966 # Average percentage of cache occupancy 943system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 944system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 945system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 946system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 947system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 948system.cpu.dcache.tags.tag_accesses 63632966 # Number of tag accesses 949system.cpu.dcache.tags.data_accesses 63632966 # Number of data accesses 950system.cpu.dcache.ReadReq_hits::cpu.inst 7808132 # number of ReadReq hits 951system.cpu.dcache.ReadReq_hits::total 7808132 # number of ReadReq hits 952system.cpu.dcache.WriteReq_hits::cpu.inst 5576867 # number of WriteReq hits 953system.cpu.dcache.WriteReq_hits::total 5576867 # number of WriteReq hits 954system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182710 # number of LoadLockedReq hits 955system.cpu.dcache.LoadLockedReq_hits::total 182710 # number of LoadLockedReq hits 956system.cpu.dcache.StoreCondReq_hits::cpu.inst 198999 # number of StoreCondReq hits 957system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits 958system.cpu.dcache.demand_hits::cpu.inst 13384999 # number of demand (read+write) hits 959system.cpu.dcache.demand_hits::total 13384999 # number of demand (read+write) hits 960system.cpu.dcache.overall_hits::cpu.inst 13384999 # number of overall hits 961system.cpu.dcache.overall_hits::total 13384999 # number of overall hits 962system.cpu.dcache.ReadReq_misses::cpu.inst 1201593 # number of ReadReq misses 963system.cpu.dcache.ReadReq_misses::total 1201593 # number of ReadReq misses 964system.cpu.dcache.WriteReq_misses::cpu.inst 573675 # number of WriteReq misses 965system.cpu.dcache.WriteReq_misses::total 573675 # number of WriteReq misses 966system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17309 # number of LoadLockedReq misses 967system.cpu.dcache.LoadLockedReq_misses::total 17309 # number of LoadLockedReq misses 968system.cpu.dcache.demand_misses::cpu.inst 1775268 # number of demand (read+write) misses 969system.cpu.dcache.demand_misses::total 1775268 # number of demand (read+write) misses 970system.cpu.dcache.overall_misses::cpu.inst 1775268 # number of overall misses 971system.cpu.dcache.overall_misses::total 1775268 # number of overall misses 972system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31027712510 # number of ReadReq miss cycles 973system.cpu.dcache.ReadReq_miss_latency::total 31027712510 # number of ReadReq miss cycles 974system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20753893806 # number of WriteReq miss cycles 975system.cpu.dcache.WriteReq_miss_latency::total 20753893806 # number of WriteReq miss cycles 976system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231648000 # number of LoadLockedReq miss cycles 977system.cpu.dcache.LoadLockedReq_miss_latency::total 231648000 # number of LoadLockedReq miss cycles 978system.cpu.dcache.demand_miss_latency::cpu.inst 51781606316 # number of demand (read+write) miss cycles 979system.cpu.dcache.demand_miss_latency::total 51781606316 # number of demand (read+write) miss cycles 980system.cpu.dcache.overall_miss_latency::cpu.inst 51781606316 # number of overall miss cycles 981system.cpu.dcache.overall_miss_latency::total 51781606316 # number of overall miss cycles 982system.cpu.dcache.ReadReq_accesses::cpu.inst 9009725 # number of ReadReq accesses(hits+misses) 983system.cpu.dcache.ReadReq_accesses::total 9009725 # number of ReadReq accesses(hits+misses) 984system.cpu.dcache.WriteReq_accesses::cpu.inst 6150542 # number of WriteReq accesses(hits+misses) 985system.cpu.dcache.WriteReq_accesses::total 6150542 # number of WriteReq accesses(hits+misses) 986system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200019 # number of LoadLockedReq accesses(hits+misses) 987system.cpu.dcache.LoadLockedReq_accesses::total 200019 # number of LoadLockedReq accesses(hits+misses) 988system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198999 # number of StoreCondReq accesses(hits+misses) 989system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses) 990system.cpu.dcache.demand_accesses::cpu.inst 15160267 # number of demand (read+write) accesses 991system.cpu.dcache.demand_accesses::total 15160267 # number of demand (read+write) accesses 992system.cpu.dcache.overall_accesses::cpu.inst 15160267 # number of overall (read+write) accesses 993system.cpu.dcache.overall_accesses::total 15160267 # number of overall (read+write) accesses 994system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133366 # miss rate for ReadReq accesses 995system.cpu.dcache.ReadReq_miss_rate::total 0.133366 # miss rate for ReadReq accesses 996system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093272 # miss rate for WriteReq accesses 997system.cpu.dcache.WriteReq_miss_rate::total 0.093272 # miss rate for WriteReq accesses 998system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086537 # miss rate for LoadLockedReq accesses 999system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086537 # miss rate for LoadLockedReq accesses 1000system.cpu.dcache.demand_miss_rate::cpu.inst 0.117100 # miss rate for demand accesses 1001system.cpu.dcache.demand_miss_rate::total 0.117100 # miss rate for demand accesses 1002system.cpu.dcache.overall_miss_rate::cpu.inst 0.117100 # miss rate for overall accesses 1003system.cpu.dcache.overall_miss_rate::total 0.117100 # miss rate for overall accesses 1004system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25822.148190 # average ReadReq miss latency 1005system.cpu.dcache.ReadReq_avg_miss_latency::total 25822.148190 # average ReadReq miss latency 1006system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36177.092964 # average WriteReq miss latency 1007system.cpu.dcache.WriteReq_avg_miss_latency::total 36177.092964 # average WriteReq miss latency 1008system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13383.095499 # average LoadLockedReq miss latency 1009system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13383.095499 # average LoadLockedReq miss latency 1010system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29168.331945 # average overall miss latency 1011system.cpu.dcache.demand_avg_miss_latency::total 29168.331945 # average overall miss latency 1012system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29168.331945 # average overall miss latency 1013system.cpu.dcache.overall_avg_miss_latency::total 29168.331945 # average overall miss latency 1014system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1015system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1016system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1017system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1018system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1019system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1020system.cpu.dcache.fast_writes 0 # number of fast writes performed 1021system.cpu.dcache.cache_copies 0 # number of cache copies performed 1022system.cpu.dcache.writebacks::writebacks 838210 # number of writebacks 1023system.cpu.dcache.writebacks::total 838210 # number of writebacks 1024system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127240 # number of ReadReq MSHR hits 1025system.cpu.dcache.ReadReq_mshr_hits::total 127240 # number of ReadReq MSHR hits 1026system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269470 # number of WriteReq MSHR hits 1027system.cpu.dcache.WriteReq_mshr_hits::total 269470 # number of WriteReq MSHR hits 1028system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits 1029system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 1030system.cpu.dcache.demand_mshr_hits::cpu.inst 396710 # number of demand (read+write) MSHR hits 1031system.cpu.dcache.demand_mshr_hits::total 396710 # number of demand (read+write) MSHR hits 1032system.cpu.dcache.overall_mshr_hits::cpu.inst 396710 # number of overall MSHR hits 1033system.cpu.dcache.overall_mshr_hits::total 396710 # number of overall MSHR hits 1034system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074353 # number of ReadReq MSHR misses 1035system.cpu.dcache.ReadReq_mshr_misses::total 1074353 # number of ReadReq MSHR misses 1036system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304205 # number of WriteReq MSHR misses 1037system.cpu.dcache.WriteReq_mshr_misses::total 304205 # number of WriteReq MSHR misses 1038system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17306 # number of LoadLockedReq MSHR misses 1039system.cpu.dcache.LoadLockedReq_mshr_misses::total 17306 # number of LoadLockedReq MSHR misses 1040system.cpu.dcache.demand_mshr_misses::cpu.inst 1378558 # number of demand (read+write) MSHR misses 1041system.cpu.dcache.demand_mshr_misses::total 1378558 # number of demand (read+write) MSHR misses 1042system.cpu.dcache.overall_mshr_misses::cpu.inst 1378558 # number of overall MSHR misses 1043system.cpu.dcache.overall_mshr_misses::total 1378558 # number of overall MSHR misses 1044system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26912219745 # number of ReadReq MSHR miss cycles 1045system.cpu.dcache.ReadReq_mshr_miss_latency::total 26912219745 # number of ReadReq MSHR miss cycles 1046system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10275413589 # number of WriteReq MSHR miss cycles 1047system.cpu.dcache.WriteReq_mshr_miss_latency::total 10275413589 # number of WriteReq MSHR miss cycles 1048system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196866500 # number of LoadLockedReq MSHR miss cycles 1049system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196866500 # number of LoadLockedReq MSHR miss cycles 1050system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37187633334 # number of demand (read+write) MSHR miss cycles 1051system.cpu.dcache.demand_mshr_miss_latency::total 37187633334 # number of demand (read+write) MSHR miss cycles 1052system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37187633334 # number of overall MSHR miss cycles 1053system.cpu.dcache.overall_mshr_miss_latency::total 37187633334 # number of overall MSHR miss cycles 1054system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423283000 # number of ReadReq MSHR uncacheable cycles 1055system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423283000 # number of ReadReq MSHR uncacheable cycles 1056system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2003033000 # number of WriteReq MSHR uncacheable cycles 1057system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2003033000 # number of WriteReq MSHR uncacheable cycles 1058system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426316000 # number of overall MSHR uncacheable cycles 1059system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426316000 # number of overall MSHR uncacheable cycles 1060system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119244 # mshr miss rate for ReadReq accesses 1061system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119244 # mshr miss rate for ReadReq accesses 1062system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049460 # mshr miss rate for WriteReq accesses 1063system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049460 # mshr miss rate for WriteReq accesses 1064system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086522 # mshr miss rate for LoadLockedReq accesses 1065system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086522 # mshr miss rate for LoadLockedReq accesses 1066system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090932 # mshr miss rate for demand accesses 1067system.cpu.dcache.demand_mshr_miss_rate::total 0.090932 # mshr miss rate for demand accesses 1068system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090932 # mshr miss rate for overall accesses 1069system.cpu.dcache.overall_mshr_miss_rate::total 0.090932 # mshr miss rate for overall accesses 1070system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25049.699442 # average ReadReq mshr miss latency 1071system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25049.699442 # average ReadReq mshr miss latency 1072system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33777.924719 # average WriteReq mshr miss latency 1073system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33777.924719 # average WriteReq mshr miss latency 1074system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11375.621172 # average LoadLockedReq mshr miss latency 1075system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.621172 # average LoadLockedReq mshr miss latency 1076system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26975.748089 # average overall mshr miss latency 1077system.cpu.dcache.demand_avg_mshr_miss_latency::total 26975.748089 # average overall mshr miss latency 1078system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26975.748089 # average overall mshr miss latency 1079system.cpu.dcache.overall_avg_mshr_miss_latency::total 26975.748089 # average overall mshr miss latency 1080system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1081system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1082system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1083system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1084system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1085system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1086system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1086 1087---------- End Simulation Statistics ---------- | 1087 1088---------- End Simulation Statistics ---------- |