4,5c4,5
< sim_ticks 1893227633000 # Number of ticks simulated
< final_tick 1893227633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 1893227678500 # Number of ticks simulated
> final_tick 1893227678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 25790 # Simulator instruction rate (inst/s)
< host_op_rate 25790 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 869674472 # Simulator tick rate (ticks/s)
< host_mem_usage 393476 # Number of bytes of host memory used
< host_seconds 2176.94 # Real time elapsed on the host
< sim_insts 56143729 # Number of instructions simulated
< sim_ops 56143729 # Number of ops (including micro ops) simulated
---
> host_inst_rate 31053 # Simulator instruction rate (inst/s)
> host_op_rate 31053 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1047239405 # Simulator tick rate (ticks/s)
> host_mem_usage 384600 # Number of bytes of host memory used
> host_seconds 1807.83 # Real time elapsed on the host
> sim_insts 56138739 # Number of instructions simulated
> sim_ops 56138739 # Number of ops (including micro ops) simulated
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 1046400 # Number of bytes read from this memory
20,25c20,25
< system.physmem.bytes_read::total 25908864 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7567040 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7567040 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25907712 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1046400 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1046400 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 16350 # Number of read requests responded to by this memory
28,32c28,32
< system.physmem.num_reads::total 404826 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 118235 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 118235 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 553315 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 13131201 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::total 404808 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 552707 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 13131200 # Total read bandwidth from this memory (bytes/s)
34,41c34,41
< system.physmem.bw_read::total 13685023 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 553315 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 553315 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3996899 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3996899 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3996899 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 553315 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 13131201 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 13684414 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 552707 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 552707 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3996629 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3996629 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3996629 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 552707 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 13131200 # Total bandwidth to/from this memory (bytes/s)
43,53c43,53
< system.physmem.bw_total::total 17681922 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 404826 # Number of read requests accepted
< system.physmem.writeReqs 118235 # Number of write requests accepted
< system.physmem.readBursts 404826 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 118235 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25901888 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7565888 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25908864 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7567040 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 17681043 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 404808 # Number of read requests accepted
> system.physmem.writeReqs 118227 # Number of write requests accepted
> system.physmem.readBursts 404808 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7564480 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25907712 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue
58,60c58,60
< system.physmem.perBankRdBursts::2 25813 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25780 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25224 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 25811 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25775 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25223 # Per bank write bursts
63,64c63,64
< system.physmem.perBankRdBursts::7 24580 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25111 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 24582 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25110 # Per bank write bursts
66c66
< system.physmem.perBankRdBursts::10 25520 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 25516 # Per bank write bursts
68,70c68,70
< system.physmem.perBankRdBursts::12 24529 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25563 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25801 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 24528 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25560 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25799 # Per bank write bursts
72,87c72,87
< system.physmem.perBankWrBursts::0 7828 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7672 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8070 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7747 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7316 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6943 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6787 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6421 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7240 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6874 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7389 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6891 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7084 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8012 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7998 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7945 # Per bank write bursts
---
> system.physmem.perBankWrBursts::0 7831 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7673 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8069 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7745 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7318 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6942 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6789 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6426 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7239 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6872 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7384 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6889 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7081 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8010 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7995 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7932 # Per bank write bursts
89,90c89,90
< system.physmem.numWrRetry 56 # Number of times write queue was full causing retry
< system.physmem.totGap 1893218679000 # Total gap between requests
---
> system.physmem.numWrRetry 72 # Number of times write queue was full causing retry
> system.physmem.totGap 1893218795000 # Total gap between requests
97c97
< system.physmem.readPktSize::6 404826 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 404808 # Read request sizes (log2)
104,107c104,107
< system.physmem.writePktSize::6 118235 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 402419 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2232 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 118227 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 402398 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2233 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
152,218c152,218
< system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5544 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5699 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6317 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6408 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7244 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8363 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 6744 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 7269 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 7829 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 7406 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6814 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6026 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5996 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5739 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5792 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 489 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 273 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 271 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 355 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 368 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 352 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 241 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 264 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 231 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 169 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 314 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 296 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 63385 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 528.007825 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 321.906071 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 413.488828 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14518 22.90% 22.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11005 17.36% 40.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4663 7.36% 47.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3176 5.01% 52.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2328 3.67% 56.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2299 3.63% 59.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1937 3.06% 62.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1572 2.48% 65.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 21887 34.53% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63385 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5244 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 77.176964 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2915.674794 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5241 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1311 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2380 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5474 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5628 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6323 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7088 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6716 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 7120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 7724 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7371 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6619 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6877 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5827 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5756 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 472 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 360 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 368 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 322 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 350 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 427 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 382 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 322 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 331 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 372 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 291 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 341 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 253 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 327 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 242 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 375 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 332 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 231 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 189 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 63391 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 527.918474 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 322.301426 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 413.348187 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14401 22.72% 22.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11109 17.52% 40.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4782 7.54% 47.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3159 4.98% 52.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2221 3.50% 56.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2316 3.65% 59.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1932 3.05% 62.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1599 2.52% 65.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 21872 34.50% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63391 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5234 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 77.317348 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2918.457754 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5231 99.94% 99.94% # Reads before turning the bus around for writes
222,250c222,249
< system.physmem.rdPerTurnAround::total 5244 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5244 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.543288 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.756988 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 24.319215 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 4714 89.89% 89.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 44 0.84% 90.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 176 3.36% 94.09% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-47 4 0.08% 94.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-55 4 0.08% 94.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-63 12 0.23% 94.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-71 7 0.13% 94.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 2 0.04% 94.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 32 0.61% 95.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-95 5 0.10% 95.35% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-103 158 3.01% 98.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 14 0.27% 98.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-119 6 0.11% 98.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-127 4 0.08% 98.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-135 6 0.11% 98.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-143 3 0.06% 98.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-151 2 0.04% 99.03% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-167 2 0.04% 99.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-175 11 0.21% 99.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 4 0.08% 99.35% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-191 14 0.27% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-199 9 0.17% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-207 1 0.02% 99.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-223 4 0.08% 99.89% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 5234 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5234 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.582155 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.722612 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 24.927693 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-23 4724 90.26% 90.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-31 39 0.75% 91.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-39 163 3.11% 94.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-47 4 0.08% 94.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-55 3 0.06% 94.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-63 11 0.21% 94.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-71 8 0.15% 94.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-79 2 0.04% 94.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-87 33 0.63% 95.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-103 144 2.75% 98.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-111 23 0.44% 98.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-119 9 0.17% 98.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-127 3 0.06% 98.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-135 7 0.13% 98.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-143 3 0.06% 98.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-151 1 0.02% 98.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-175 10 0.19% 99.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-183 5 0.10% 99.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-191 14 0.27% 99.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-199 10 0.19% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::200-207 3 0.06% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::216-223 5 0.10% 99.89% # Writes before turning the bus around for reads
252,258c251,259
< system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5244 # Writes before turning the bus around for reads
< system.physmem.totQLat 5894702000 # Total ticks spent queuing
< system.physmem.totMemAccLat 13483145750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2023585000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 14565.00 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::256-263 1 0.02% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::264-271 1 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-279 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-359 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5234 # Writes before turning the bus around for reads
> system.physmem.totQLat 5912751750 # Total ticks spent queuing
> system.physmem.totMemAccLat 13500876750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 14610.21 # Average queueing delay per DRAM burst
260c261
< system.physmem.avgMemAccLat 33315.00 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 33360.21 # Average memory access latency per DRAM burst
263c264
< system.physmem.avgRdBWSys 13.69 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s
270,321c271,322
< system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing
< system.physmem.readRowHits 363769 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95780 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.88 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes
< system.physmem.avgGap 3619498.83 # Average gap between requests
< system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 221604180 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 117785415 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1444679040 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 306852480 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 4717362000.000001 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 4796151000 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 296411520 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 10938570180 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 5566653120 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 443189598645 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 471596477220 # Total energy per rank (pJ)
< system.physmem_0.averagePower 249.096553 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 1881819292000 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 462054000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2003948000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 1843451492500 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 14496450250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 8825649500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 23988038750 # Time in different power states
< system.physmem_1.actEnergy 230964720 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 122760660 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1445000340 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 310240260 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 4792348080.000001 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 4813778250 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 297177120 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 11174584380 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 5627937120 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 443035577925 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 471852130095 # Total energy per rank (pJ)
< system.physmem_1.averagePower 249.231588 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 1881891335250 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 468372250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 2035962000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 1842731534750 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 14656099500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 8829934000 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 24505730500 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 15259378 # Number of BP lookups
< system.cpu.branchPred.condPredicted 13119579 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 525820 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 12061992 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 4569562 # Number of BTB hits
---
> system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing
> system.physmem.readRowHits 363798 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95706 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.89 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 80.95 # Row buffer hit rate for writes
> system.physmem.avgGap 3619678.98 # Average gap between requests
> system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 222139680 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 118070040 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1444636200 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 4706913120.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 4768209600 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 303610560 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 10937646210 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 5541404160 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 443214367815 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 471564552855 # Total energy per rank (pJ)
> system.physmem_0.averagePower 249.079684 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 1881862215000 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 479498250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1999510000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 1843562153500 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 14430696500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 8769616250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 23986204000 # Time in different power states
> system.physmem_1.actEnergy 230472060 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 122498805 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 310078440 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 4819392240.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 4890695190 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 314585760 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 11137759530 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 5641159680 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 443008801920 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 471922426215 # Total energy per rank (pJ)
> system.physmem_1.averagePower 249.268712 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 1881676600250 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 514596250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2047516000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 1842563195250 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 14690458500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 8987140500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 24424772000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 15251875 # Number of BP lookups
> system.cpu.branchPred.condPredicted 13114549 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 526465 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 12070936 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 4577345 # Number of BTB hits
323,329c324,330
< system.cpu.branchPred.BTBHitPct 37.883975 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 862888 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 32219 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 6522078 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 538261 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 5983817 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 225046 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 37.920382 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 863154 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 33512 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 6526029 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 541717 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 5984312 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 221941 # Number of mispredicted indirect branches.
335,336c336,337
< system.cpu.dtb.read_hits 9322510 # DTB read hits
< system.cpu.dtb.read_misses 17386 # DTB read misses
---
> system.cpu.dtb.read_hits 9319487 # DTB read hits
> system.cpu.dtb.read_misses 17755 # DTB read misses
338,340c339,341
< system.cpu.dtb.read_accesses 764595 # DTB read accesses
< system.cpu.dtb.write_hits 6393584 # DTB write hits
< system.cpu.dtb.write_misses 2379 # DTB write misses
---
> system.cpu.dtb.read_accesses 764786 # DTB read accesses
> system.cpu.dtb.write_hits 6392965 # DTB write hits
> system.cpu.dtb.write_misses 2560 # DTB write misses
342,344c343,345
< system.cpu.dtb.write_accesses 298734 # DTB write accesses
< system.cpu.dtb.data_hits 15716094 # DTB hits
< system.cpu.dtb.data_misses 19765 # DTB misses
---
> system.cpu.dtb.write_accesses 298884 # DTB write accesses
> system.cpu.dtb.data_hits 15712452 # DTB hits
> system.cpu.dtb.data_misses 20315 # DTB misses
346,350c347,351
< system.cpu.dtb.data_accesses 1063329 # DTB accesses
< system.cpu.itb.fetch_hits 4018414 # ITB hits
< system.cpu.itb.fetch_misses 6313 # ITB misses
< system.cpu.itb.fetch_acv 710 # ITB acv
< system.cpu.itb.fetch_accesses 4024727 # ITB accesses
---
> system.cpu.dtb.data_accesses 1063670 # DTB accesses
> system.cpu.itb.fetch_hits 4023125 # ITB hits
> system.cpu.itb.fetch_misses 6293 # ITB misses
> system.cpu.itb.fetch_acv 687 # ITB acv
> system.cpu.itb.fetch_accesses 4029418 # ITB accesses
363,368c364,369
< system.cpu.numPwrStateTransitions 12750 # Number of power state transitions
< system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::mean 281835914.509804 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 440008281.220830 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1000-5e+10 6375 100.00% 100.00% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::min_value 224500 # Distribution of time spent in the clock gated state
---
> system.cpu.numPwrStateTransitions 12752 # Number of power state transitions
> system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::mean 281784609.786700 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 439970621.768515 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::min_value 121000 # Distribution of time spent in the clock gated state
370,373c371,374
< system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateResidencyTicks::ON 96523678000 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 1796703955000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 193068084 # number of cpu cycles simulated
---
> system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateResidencyTicks::ON 96569006500 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 1796658672000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 193159059 # number of cpu cycles simulated
376,385c377,386
< system.cpu.committedInsts 56143729 # Number of instructions committed
< system.cpu.committedOps 56143729 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 2983109 # Number of ops (including micro ops) which were discarded before commit
< system.cpu.numFetchSuspends 6375 # Number of times Execute suspended instruction fetching
< system.cpu.quiesceCycles 3593387182 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 3.438818 # CPI: cycles per instruction
< system.cpu.ipc 0.290798 # IPC: instructions per cycle
< system.cpu.op_class_0::No_OpClass 3199033 5.70% 5.70% # Class of committed instruction
< system.cpu.op_class_0::IntAlu 36198718 64.48% 70.17% # Class of committed instruction
< system.cpu.op_class_0::IntMult 60825 0.11% 70.28% # Class of committed instruction
---
> system.cpu.committedInsts 56138739 # Number of instructions committed
> system.cpu.committedOps 56138739 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 2973387 # Number of ops (including micro ops) which were discarded before commit
> system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching
> system.cpu.quiesceCycles 3593296298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 3.440745 # CPI: cycles per instruction
> system.cpu.ipc 0.290635 # IPC: instructions per cycle
> system.cpu.op_class_0::No_OpClass 3199075 5.70% 5.70% # Class of committed instruction
> system.cpu.op_class_0::IntAlu 36194440 64.47% 70.17% # Class of committed instruction
> system.cpu.op_class_0::IntMult 60814 0.11% 70.28% # Class of committed instruction
392,416c393,417
< system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction
< system.cpu.op_class_0::FloatMisc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction
< system.cpu.op_class_0::MemRead 9175039 16.34% 86.70% # Class of committed instruction
< system.cpu.op_class_0::MemWrite 6234994 11.11% 97.80% # Class of committed instruction
---
> system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
> system.cpu.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
> system.cpu.op_class_0::MemRead 9174678 16.34% 86.70% # Class of committed instruction
> system.cpu.op_class_0::MemWrite 6234348 11.11% 97.80% # Class of committed instruction
419c420
< system.cpu.op_class_0::IprAccess 950928 1.69% 100.00% # Class of committed instruction
---
> system.cpu.op_class_0::IprAccess 951192 1.69% 100.00% # Class of committed instruction
421c422
< system.cpu.op_class_0::total 56143729 # Class of committed instruction
---
> system.cpu.op_class_0::total 56138739 # Class of committed instruction
423,426c424,427
< system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211453 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74770 40.93% 40.93% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 211522 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74796 40.93% 40.93% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl
428,430c429,431
< system.cpu.kern.ipl_count::31 105857 57.95% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182663 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73403 49.32% 49.32% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::31 105900 57.95% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182732 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73429 49.32% 49.32% # number of times we switched to this ipl from a different ipl
433,440c434,441
< system.cpu.kern.ipl_good::31 73403 49.32% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 148842 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1837707081000 97.07% 97.07% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 86418000 0.00% 97.07% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 712034000 0.04% 97.11% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 54721100500 2.89% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1893226633500 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981717 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::31 73429 49.32% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 148894 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1837688968000 97.07% 97.07% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 86405500 0.00% 97.07% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 711997500 0.04% 97.11% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 54739315500 2.89% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1893226686500 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl
443,444c444,445
< system.cpu.kern.ipl_used::31 0.693417 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814845 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.693381 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814822 # fraction of swpipl calls that actually changed the ipl
452c453
< system.cpu.kern.callpal::swpipl 175496 91.22% 93.42% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175565 91.22% 93.43% # number of callpals executed
461c462
< system.cpu.kern.callpal::total 192387 # number of callpals executed
---
> system.cpu.kern.callpal::total 192456 # number of callpals executed
463c464
< system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
---
> system.cpu.kern.mode_switch::user 1736 # number of protection mode switches
465,466c466,467
< system.cpu.kern.mode_good::kernel 1907
< system.cpu.kern.mode_good::user 1739
---
> system.cpu.kern.mode_good::kernel 1904
> system.cpu.kern.mode_good::user 1736
468c469
< system.cpu.kern.mode_switch_good::kernel 0.324596 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch_good::kernel 0.324085 # fraction of useful protection mode switches
471,474c472,475
< system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 37288586500 1.97% 1.97% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 4317914500 0.23% 2.20% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1851620122500 97.80% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_switch_good::total 0.392375 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 37303090500 1.97% 1.97% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 4315388500 0.23% 2.20% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1851608197500 97.80% 100.00% # number of ticks spent at the given mode
476,483c477,484
< system.cpu.tickCycles 85319079 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 107749005 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 1394486 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.980102 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 13946466 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1394998 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 9.997481 # Average number of references to valid blocks.
---
> system.cpu.tickCycles 85358190 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 107800869 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 1394352 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 13943564 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1394864 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 9.996361 # Average number of references to valid blocks.
485c486
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.980102 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor
493,559c494,560
< system.cpu.dcache.tags.tag_accesses 63927467 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63927467 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 7985618 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7985618 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5578297 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5578297 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 183538 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 183538 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 198978 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 198978 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 13563915 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13563915 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13563915 # number of overall hits
< system.cpu.dcache.overall_hits::total 13563915 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1096590 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1096590 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 573634 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 573634 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 16462 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 16462 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1670224 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1670224 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1670224 # number of overall misses
< system.cpu.dcache.overall_misses::total 1670224 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 33587119500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 33587119500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 25315634500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 25315634500 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222567500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 222567500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 58902754000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 58902754000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 58902754000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 58902754000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 9082208 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9082208 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6151931 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6151931 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200000 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200000 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 198978 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 198978 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15234139 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15234139 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15234139 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15234139 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120740 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.120740 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093245 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.093245 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082310 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082310 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.109637 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.109637 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.109637 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.109637 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30628.693951 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 30628.693951 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44132.032794 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 44132.032794 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13520.076540 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13520.076540 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 35266.379839 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 35266.379839 # average overall miss latency
---
> system.cpu.dcache.tags.tag_accesses 63916074 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63916074 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 7983580 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7983580 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5577346 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5577346 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 183586 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 183586 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 199016 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 199016 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 13560926 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13560926 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13560926 # number of overall hits
> system.cpu.dcache.overall_hits::total 13560926 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1096421 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1096421 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 573901 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 573901 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 16452 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 16452 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1670322 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1670322 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1670322 # number of overall misses
> system.cpu.dcache.overall_misses::total 1670322 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 33580747500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 33580747500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 25364054000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 25364054000 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223095000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 223095000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 58944801500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 58944801500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 58944801500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 58944801500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 9080001 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9080001 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6151247 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6151247 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200038 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200038 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 199016 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 199016 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15231248 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15231248 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15231248 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15231248 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120751 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.120751 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093298 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.093298 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082244 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082244 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.109664 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.109664 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.109664 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.109664 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30627.603357 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 30627.603357 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44195.870019 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 44195.870019 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.357403 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.357403 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 35289.484004 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 35289.484004 # average overall miss latency
566,571c567,572
< system.cpu.dcache.writebacks::writebacks 837775 # number of writebacks
< system.cpu.dcache.writebacks::total 837775 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21966 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 21966 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269674 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 269674 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 837673 # number of writebacks
> system.cpu.dcache.writebacks::total 837673 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269878 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 269878 # number of WriteReq MSHR hits
574,587c575,588
< system.cpu.dcache.demand_mshr_hits::cpu.data 291640 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 291640 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 291640 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 291640 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074624 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1074624 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303960 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 303960 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16459 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 16459 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1378584 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1378584 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1378584 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1378584 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 291859 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 291859 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 291859 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 291859 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074440 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1074440 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304023 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304023 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16449 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 16449 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1378463 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1378463 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1378463 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1378463 # number of overall MSHR misses
594,639c595,640
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32024640000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 32024640000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12912591500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 12912591500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205405000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205405000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44937231500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 44937231500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44937231500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 44937231500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534181500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534181500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534181500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534181500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118322 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118322 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049409 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049409 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082295 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082295 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.090493 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.090493 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29800.786135 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29800.786135 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42481.219568 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42481.219568 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.798287 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.798287 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221382.611833 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221382.611833 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92682.987978 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92682.987978 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 1476860 # number of replacements
< system.cpu.icache.tags.tagsinuse 509.256241 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 19221452 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1477371 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 13.010579 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 36168783500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 509.256241 # Average occupied blocks per requestor
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32016506000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 32016506000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12938125500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12938125500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205942500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205942500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44954631500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 44954631500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44954631500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 44954631500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534159000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534159000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534159000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534159000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118330 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118330 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049425 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049425 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082229 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082229 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.090502 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.090502 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29798.319124 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29798.319124 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42556.403627 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42556.403627 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12520.062010 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12520.062010 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.365079 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.365079 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92681.628708 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92681.628708 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 1477259 # number of replacements
> system.cpu.icache.tags.tagsinuse 509.256262 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 19240724 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1477770 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 13.020107 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 36168160500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 509.256262 # Average occupied blocks per requestor
643,645c644,646
< system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id
647,685c648,686
< system.cpu.icache.tags.tag_accesses 22176547 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 22176547 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 19221455 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 19221455 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 19221455 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 19221455 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 19221455 # number of overall hits
< system.cpu.icache.overall_hits::total 19221455 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1477546 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1477546 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1477546 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1477546 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1477546 # number of overall misses
< system.cpu.icache.overall_misses::total 1477546 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 20691200000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 20691200000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 20691200000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 20691200000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 20691200000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 20691200000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 20699001 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 20699001 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 20699001 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 20699001 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 20699001 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 20699001 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071382 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.071382 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.071382 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.071382 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.071382 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.071382 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14003.760289 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14003.760289 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14003.760289 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14003.760289 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 22196619 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 22196619 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 19240727 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 19240727 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 19240727 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 19240727 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 19240727 # number of overall hits
> system.cpu.icache.overall_hits::total 19240727 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1477946 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1477946 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1477946 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1477946 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1477946 # number of overall misses
> system.cpu.icache.overall_misses::total 1477946 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 20694155000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 20694155000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 20694155000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 20694155000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 20694155000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 20694155000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 20718673 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 20718673 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 20718673 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 20718673 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 20718673 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 20718673 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071334 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.071334 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.071334 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.071334 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.071334 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.071334 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14001.969625 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14001.969625 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14001.969625 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14001.969625 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14001.969625 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14001.969625 # average overall miss latency
692,731c693,732
< system.cpu.icache.writebacks::writebacks 1476860 # number of writebacks
< system.cpu.icache.writebacks::total 1476860 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477546 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1477546 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1477546 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1477546 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1477546 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1477546 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19213654000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19213654000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19213654000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19213654000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19213654000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19213654000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071382 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.071382 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.071382 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13003.760289 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13003.760289 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 339644 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65408.616626 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 5336317 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 405166 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 13.170693 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 6813000000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 268.269404 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 5779.515007 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 59360.832216 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.004093 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088188 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.905774 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.998056 # Average percentage of cache occupancy
---
> system.cpu.icache.writebacks::writebacks 1477259 # number of writebacks
> system.cpu.icache.writebacks::total 1477259 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477946 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1477946 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1477946 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1477946 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1477946 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1477946 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19216209000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 19216209000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19216209000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 19216209000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19216209000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 19216209000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071334 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.071334 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.071334 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13001.969625 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13001.969625 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13001.969625 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13001.969625 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13001.969625 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13001.969625 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 339629 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65408.640121 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 5336861 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 405151 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 13.172523 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 6812650000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 268.308507 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 5784.509565 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.822049 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.004094 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088265 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.905698 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy
735c736
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
737c738
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59335 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59336 # Occupied blocks per task id
739,759c740,760
< system.cpu.l2cache.tags.tag_accesses 46341070 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 46341070 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 837775 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 837775 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 1476292 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 1476292 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187328 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187328 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461124 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1461124 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818824 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 818824 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 1461124 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1006152 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2467276 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 1461124 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1006152 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2467276 # number of overall hits
---
> system.cpu.l2cache.tags.tag_accesses 46345268 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 46345268 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 837673 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 837673 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 1476684 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 1476684 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187384 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187384 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461541 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1461541 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818635 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 818635 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 1461541 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1006019 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2467560 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 1461541 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1006019 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2467560 # number of overall hits
762,773c763,774
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116642 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116642 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16369 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 16369 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272228 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 272228 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 16369 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 388870 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 405239 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 16369 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 388870 # number of overall misses
< system.cpu.l2cache.overall_misses::total 405239 # number of overall misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116650 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116650 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16351 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 16351 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272221 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 272221 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 16351 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 388871 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 405222 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 16351 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 388871 # number of overall misses
> system.cpu.l2cache.overall_misses::total 405222 # number of overall misses
776,819c777,820
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10483953000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 10483953000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1616348000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 1616348000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21973293500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 21973293500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1616348000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 32457246500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34073594500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1616348000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 32457246500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34073594500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 837775 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 837775 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 1476292 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 1476292 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 303970 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 303970 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477493 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1477493 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091052 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1091052 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1477493 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1395022 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2872515 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1477493 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1395022 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2872515 # number of overall (read+write) accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.285714 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383729 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383729 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011079 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011079 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249510 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249510 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011079 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.278755 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.141075 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011079 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.278755 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.141075 # miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10508664000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10508664000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1613902000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 1613902000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21967740000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 21967740000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1613902000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 32476404000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 34090306000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1613902000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 32476404000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 34090306000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 837673 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 837673 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 1476684 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 1476684 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 304034 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304034 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477892 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1477892 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1090856 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1090856 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1477892 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1394890 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2872782 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1477892 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1394890 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2872782 # number of overall (read+write) accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.272727 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.272727 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383674 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383674 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011064 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011064 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249548 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249548 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011064 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.278783 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.141056 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011064 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.278783 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.141056 # miss rate for overall accesses
822,833c823,834
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89881.457794 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89881.457794 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98744.455984 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98744.455984 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80716.507854 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80716.507854 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 84082.712918 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 84082.712918 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90087.132447 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90087.132447 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98703.565531 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98703.565531 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80698.182727 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80698.182727 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98703.565531 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83514.594814 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 84127.480739 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98703.565531 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83514.594814 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 84127.480739 # average overall miss latency
840,841c841,842
< system.cpu.l2cache.writebacks::writebacks 76723 # number of writebacks
< system.cpu.l2cache.writebacks::total 76723 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 76715 # number of writebacks
> system.cpu.l2cache.writebacks::total 76715 # number of writebacks
844,855c845,856
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116642 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116642 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16369 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16369 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272228 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272228 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 16369 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 388870 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 405239 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 16369 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 388870 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 405239 # number of overall MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116650 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116650 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16351 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16351 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272221 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272221 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 16351 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 388871 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 405222 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 16351 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 388871 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 405222 # number of overall MSHR misses
864,893c865,894
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9317533000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9317533000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1452658000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1452658000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19254021000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19254021000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1452658000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28571554000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 30024212000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1452658000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28571554000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 30024212000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447536000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447536000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447536000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447536000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383729 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383729 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011079 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249510 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249510 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.141075 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.141075 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9342164000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9342164000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1450392000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1450392000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19248668000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19248668000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1450392000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28590832000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 30041224000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1450392000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28590832000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 30041224000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447515000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447515000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447515000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447515000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.272727 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383674 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383674 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011064 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249548 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249548 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278783 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.141056 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278783 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.141056 # mshr miss rate for overall accesses
896,916c897,917
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79881.457794 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79881.457794 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88744.455984 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88744.455984 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70727.555578 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70727.555578 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208879.653680 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208879.653680 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.559174 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.559174 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 5743935 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871442 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80087.132447 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80087.132447 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88703.565531 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88703.565531 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70709.710125 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70709.710125 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87447.290521 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87447.290521 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 5744469 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871707 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
918c919
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
920c921
< system.cpu.toL2Bus.trans_dist::ReadResp 2575661 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2575864 # Transaction distribution
923,945c924,946
< system.cpu.toL2Bus.trans_dist::WritebackDirty 914498 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 1476860 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 819632 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 303970 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 303970 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477546 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091213 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4431899 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217835 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8649734 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189078592 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142951868 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 332030460 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 340255 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 4923648 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 3229187 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.001046 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.032331 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 914388 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 1477259 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 819593 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 304034 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 304034 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477946 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091017 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4433097 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217440 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8650537 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189129664 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142936828 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 332066492 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 340239 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 4923200 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 3229438 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.001049 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.032373 # Request fanout histogram
947,948c948,949
< system.cpu.toL2Bus.snoop_fanout::0 3225808 99.90% 99.90% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 3379 0.10% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 3226050 99.90% 99.90% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3388 0.10% 100.00% # Request fanout histogram
953,954c954,955
< system.cpu.toL2Bus.snoop_fanout::total 3229187 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 5199690500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 3229438 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 5200254500 # Layer occupancy (ticks)
956c957
< system.cpu.toL2Bus.snoopLayer0.occupancy 292383 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks)
958c959
< system.cpu.toL2Bus.respLayer0.occupancy 2216461215 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2217065706 # Layer occupancy (ticks)
960c961
< system.cpu.toL2Bus.respLayer1.occupancy 2104266491 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2104067991 # Layer occupancy (ticks)
974c975
< system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
1005c1006
< system.iobus.reqLayer0.occupancy 5413000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer0.occupancy 5413500 # Layer occupancy (ticks)
1007c1008
< system.iobus.reqLayer1.occupancy 807000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 792000 # Layer occupancy (ticks)
1013c1014
< system.iobus.reqLayer22.occupancy 181000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks)
1015c1016
< system.iobus.reqLayer23.occupancy 15127500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 15611000 # Layer occupancy (ticks)
1019c1020
< system.iobus.reqLayer25.occupancy 5984000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 5971500 # Layer occupancy (ticks)
1023c1024
< system.iobus.reqLayer27.occupancy 216248283 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 216263272 # Layer occupancy (ticks)
1029c1030
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
1031c1032
< system.iocache.tags.tagsinuse 1.299538 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.299521 # Cycle average of tags in use
1035,1038c1036,1039
< system.iocache.tags.warmup_cycle 1735874305000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.299538 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.081221 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.081221 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1735874841000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.299521 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.081220 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.081220 # Average percentage of cache occupancy
1044c1045
< system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
1055,1060c1056,1061
< system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931902900 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4931902900 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 4961787283 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4961787283 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 4961787283 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4961787283 # number of overall miss cycles
---
> system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948356889 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4948356889 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 4978241272 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4978241272 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 4978241272 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4978241272 # number of overall miss cycles
1079,1085c1080,1086
< system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118692.310839 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118692.310839 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 118916.411815 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 118916.411815 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked
---
> system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119088.296327 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 119088.296327 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 119310.755470 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 119310.755470 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 1846 # number of cycles access was blocked
1087c1088
< system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 14 # number of cycles access was blocked
1089c1090
< system.iocache.avg_blocked_cycles::no_mshrs 111.625000 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 131.857143 # average number of cycles each access was blocked
1103,1108c1104,1109
< system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851851307 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2851851307 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 2873085690 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2873085690 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 2873085690 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2873085690 # number of overall MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868303297 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2868303297 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 2889537680 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2889537680 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 2889537680 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2889537680 # number of overall MSHR miss cycles
1119,1126c1120,1127
< system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68633.310238 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68633.310238 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency
< system.membus.snoop_filter.tot_requests 827515 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 381393 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69029.247617 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69029.247617 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 827499 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 381391 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1131c1132
< system.membus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
1133c1134
< system.membus.trans_dist::ReadResp 295677 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 295651 # Transaction distribution
1136,1137c1137,1138
< system.membus.trans_dist::WritebackDirty 118235 # Transaction distribution
< system.membus.trans_dist::CleanEvict 262254 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution
> system.membus.trans_dist::CleanEvict 262247 # Transaction distribution
1140,1143c1141,1144
< system.membus.trans_dist::ReadExReq 116510 # Transaction distribution
< system.membus.trans_dist::ReadExResp 116510 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 288770 # Transaction distribution
< system.membus.trans_dist::BadAddressError 23 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 116518 # Transaction distribution
> system.membus.trans_dist::ReadExResp 116518 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution
> system.membus.trans_dist::BadAddressError 24 # Transaction distribution
1145c1146
< system.membus.trans_dist::InvalidateResp 127 # Transaction distribution
---
> system.membus.trans_dist::InvalidateResp 124 # Transaction distribution
1147,1149c1148,1150
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148837 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181989 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148786 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181940 # Packet count per connected master and slave (bytes)
1152c1153
< system.membus.pkt_count::total 1265414 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1265365 # Packet count per connected master and slave (bytes)
1154,1155c1155,1156
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30818176 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30862524 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816512 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860860 # Cumulative packet size per connected master and slave (bytes)
1158,1159c1159,1160
< system.membus.pkt_size::total 33520252 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 561 # Total snoops (count)
---
> system.membus.pkt_size::total 33518588 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 558 # Total snoops (count)
1161,1163c1162,1164
< system.membus.snoop_fanout::samples 463523 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.001461 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.038189 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 463506 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.001454 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.038105 # Request fanout histogram
1165,1166c1166,1167
< system.membus.snoop_fanout::0 462846 99.85% 99.85% # Request fanout histogram
< system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram
> system.membus.snoop_fanout::1 674 0.15% 100.00% # Request fanout histogram
1171,1172c1172,1173
< system.membus.snoop_fanout::total 463523 # Request fanout histogram
< system.membus.reqLayer0.occupancy 29930000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 463506 # Request fanout histogram
> system.membus.reqLayer0.occupancy 30386000 # Layer occupancy (ticks)
1174c1175
< system.membus.reqLayer1.occupancy 1319547835 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1319436087 # Layer occupancy (ticks)
1176c1177
< system.membus.reqLayer2.occupancy 29000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks)
1178c1179
< system.membus.respLayer1.occupancy 2160176250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2160035750 # Layer occupancy (ticks)
1180c1181
< system.membus.respLayer2.occupancy 1081022 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1079521 # Layer occupancy (ticks)
1182,1186c1183,1187
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
1218,1240c1219,1241
< system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
< system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states
---
> system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states
> system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states