3,5c3,5
< sim_seconds 1.909061 # Number of seconds simulated
< sim_ticks 1909061460000 # Number of ticks simulated
< final_tick 1909061460000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.889223 # Number of seconds simulated
> sim_ticks 1889223246000 # Number of ticks simulated
> final_tick 1889223246000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 24403 # Simulator instruction rate (inst/s)
< host_op_rate 24403 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 829686396 # Simulator tick rate (ticks/s)
< host_mem_usage 385840 # Number of bytes of host memory used
< host_seconds 2300.94 # Real time elapsed on the host
< sim_insts 56149847 # Number of instructions simulated
< sim_ops 56149847 # Number of ops (including micro ops) simulated
---
> host_inst_rate 22780 # Simulator instruction rate (inst/s)
> host_op_rate 22780 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 766551699 # Simulator tick rate (ticks/s)
> host_mem_usage 396616 # Number of bytes of host memory used
> host_seconds 2464.57 # Real time elapsed on the host
> sim_insts 56141873 # Number of instructions simulated
> sim_ops 56141873 # Number of ops (including micro ops) simulated
16,18c16,18
< system.physmem.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 1046656 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24857664 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24859008 # Number of bytes read from this memory
20,26c20,26
< system.physmem.bytes_read::total 25905280 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1046656 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1046656 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7563328 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7563328 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 16354 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388401 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25907520 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388422 # Number of read requests responded to by this memory
28,53c28,53
< system.physmem.num_reads::total 404770 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 118177 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 118177 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 548257 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 13020882 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 13569642 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 548257 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 548257 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3961804 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3961804 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3961804 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 548257 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 13020882 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 17531446 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 404770 # Number of read requests accepted
< system.physmem.writeReqs 118177 # Number of write requests accepted
< system.physmem.readBursts 404770 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 118177 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25897600 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7561728 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25905280 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7563328 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_reads::total 404805 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 554488 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 13158322 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 508 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 13713318 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 554488 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 554488 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4005100 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4005100 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4005100 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 554488 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 13158322 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 508 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 17718418 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 404805 # Number of read requests accepted
> system.physmem.writeReqs 118227 # Number of write requests accepted
> system.physmem.readBursts 404805 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7565120 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25907520 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue
56,72c56,72
< system.physmem.perBankRdBursts::0 25467 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25712 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25810 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25757 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25010 # Per bank write bursts
< system.physmem.perBankRdBursts::5 25117 # Per bank write bursts
< system.physmem.perBankRdBursts::6 24705 # Per bank write bursts
< system.physmem.perBankRdBursts::7 24573 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25203 # Per bank write bursts
< system.physmem.perBankRdBursts::9 25292 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25386 # Per bank write bursts
< system.physmem.perBankRdBursts::11 25018 # Per bank write bursts
< system.physmem.perBankRdBursts::12 24535 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25541 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25794 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25730 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7820 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 25470 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25713 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25812 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25774 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25230 # Per bank write bursts
> system.physmem.perBankRdBursts::5 24950 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24793 # Per bank write bursts
> system.physmem.perBankRdBursts::7 24569 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25113 # Per bank write bursts
> system.physmem.perBankRdBursts::9 25266 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25525 # Per bank write bursts
> system.physmem.perBankRdBursts::11 24857 # Per bank write bursts
> system.physmem.perBankRdBursts::12 24533 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25560 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25804 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25731 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7815 # Per bank write bursts
74,78c74,78
< system.physmem.perBankWrBursts::2 8070 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7721 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7116 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7111 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6703 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 8068 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7736 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7326 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6953 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6780 # Per bank write bursts
80,87c80,87
< system.physmem.perBankWrBursts::8 7317 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6903 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7274 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7007 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7092 # Per bank write bursts
< system.physmem.perBankWrBursts::13 7990 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7984 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7946 # Per bank write bursts
---
> system.physmem.perBankWrBursts::8 7238 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6883 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7397 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6875 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7088 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8006 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7993 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7949 # Per bank write bursts
89,90c89,90
< system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
< system.physmem.totGap 1909052547000 # Total gap between requests
---
> system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
> system.physmem.totGap 1889214280000 # Total gap between requests
97c97
< system.physmem.readPktSize::6 404770 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 404805 # Read request sizes (log2)
104,107c104,107
< system.physmem.writePktSize::6 118177 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 402459 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2130 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 118227 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 402482 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2156 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see
152,218c152,218
< system.physmem.wrQLenPdf::15 1514 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2905 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 7219 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5886 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6802 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6024 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5843 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6456 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 6884 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 6578 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8579 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8848 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7457 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7892 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7078 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7321 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6026 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5605 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 214 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 136 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 127 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 112 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 91 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 184 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 88 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 89 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 64573 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 518.162823 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 316.799935 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 407.231768 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14977 23.19% 23.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11234 17.40% 40.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4851 7.51% 48.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3268 5.06% 53.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2473 3.83% 56.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2033 3.15% 60.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 4174 6.46% 66.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1362 2.11% 68.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 20201 31.28% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 64573 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 76.433321 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2890.025475 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5291 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1475 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2724 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5709 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5854 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6607 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6640 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7607 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8810 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7088 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 7791 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8480 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7557 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6981 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7102 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5712 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5654 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5555 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 285 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 204 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 196 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 170 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 235 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 209 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 122 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 101 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 98 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 99 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 80 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 63746 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 524.988548 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 319.641335 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 414.335221 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14725 23.10% 23.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 10901 17.10% 40.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5357 8.40% 48.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3110 4.88% 53.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2601 4.08% 57.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1701 2.67% 60.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1560 2.45% 62.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1439 2.26% 64.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 22352 35.06% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63746 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 76.386372 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2900.765356 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5295 99.94% 99.94% # Reads before turning the bus around for writes
222,254c222,256
< system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.318096 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.102648 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 19.930772 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 4682 88.44% 88.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 33 0.62% 89.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 23 0.43% 89.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-47 33 0.62% 90.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-55 222 4.19% 94.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-63 11 0.21% 94.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-71 11 0.21% 94.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 35 0.66% 95.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 195 3.68% 99.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-95 5 0.09% 99.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-103 6 0.11% 99.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 4 0.08% 99.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-135 5 0.09% 99.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-143 2 0.04% 99.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-151 1 0.02% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-167 2 0.04% 99.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-175 9 0.17% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 4 0.08% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-191 2 0.04% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-215 5 0.09% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-223 1 0.02% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-231 1 0.02% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads
< system.physmem.totQLat 2639973000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10227160500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2023250000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 6524.09 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5298 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.311250 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.880356 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 22.145944 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-23 4698 88.67% 88.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-31 33 0.62% 89.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-39 235 4.44% 93.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-47 22 0.42% 94.15% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-55 12 0.23% 94.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-63 14 0.26% 94.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-71 10 0.19% 94.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-79 4 0.08% 94.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-87 30 0.57% 95.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-95 15 0.28% 95.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-103 179 3.38% 99.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-111 1 0.02% 99.15% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-119 1 0.02% 99.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-127 1 0.02% 99.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-135 6 0.11% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-159 2 0.04% 99.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-167 4 0.08% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-175 12 0.23% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-183 2 0.04% 99.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-191 4 0.08% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-231 8 0.15% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5298 # Writes before turning the bus around for reads
> system.physmem.totQLat 2164522000 # Total ticks spent queuing
> system.physmem.totMemAccLat 9752647000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 5348.46 # Average queueing delay per DRAM burst
256,260c258,262
< system.physmem.avgMemAccLat 25274.09 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.57 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.96 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.57 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.96 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24098.46 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.71 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.71 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s
266,283c268,285
< system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing
< system.physmem.readRowHits 362738 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95491 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.64 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes
< system.physmem.avgGap 3650566.02 # Average gap between requests
< system.physmem.pageHitRate 87.64 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 238623840 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 130201500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1576777800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 379980720 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 124690266480 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 68013230490 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1085773099500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1280802180330 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.908515 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1806022540250 # Time in different power states
< system.physmem_0.memoryStateTime::REF 63747580000 # Time in different power states
---
> system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing
> system.physmem.readRowHits 363251 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95908 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.76 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 81.12 # Row buffer hit rate for writes
> system.physmem.avgGap 3612043.39 # Average gap between requests
> system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 234556560 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 127982250 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1578025800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 380868480 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 60772181625 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1080221277750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1266709348065 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.494357 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1796832063750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 63085100000 # Time in different power states
285c287
< system.physmem_0.memoryStateTime::ACT 39286273500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 29299865000 # Time in different power states
287,297c289,299
< system.physmem_1.actEnergy 249548040 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 136162125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1579492200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 385644240 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 124690266480 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 68685352830 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1085183526750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1280909992665 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.964984 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1805042162250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 63747580000 # Time in different power states
---
> system.physmem_1.actEnergy 247363200 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 134970000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1578634200 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 385099920 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 61856765370 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1079269896750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1266867185040 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.577899 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1795248089750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 63085100000 # Time in different power states
299c301
< system.physmem_1.memoryStateTime::ACT 40266665250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 30883852750 # Time in different power states
301,307c303,309
< system.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 15258422 # Number of BP lookups
< system.cpu.branchPred.condPredicted 13121569 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 520615 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 12105776 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 4568162 # Number of BTB hits
---
> system.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 15253451 # Number of BP lookups
> system.cpu.branchPred.condPredicted 13119801 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 515637 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 12113296 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 4570787 # Number of BTB hits
309,315c311,317
< system.cpu.branchPred.BTBHitPct 37.735392 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 863536 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 33630 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 6539212 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 544524 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 5994688 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 219095 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 37.733636 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 859438 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 30658 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 6570706 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 545483 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 6025223 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 218035 # Number of mispredicted indirect branches.
321,322c323,324
< system.cpu.dtb.read_hits 9320175 # DTB read hits
< system.cpu.dtb.read_misses 17427 # DTB read misses
---
> system.cpu.dtb.read_hits 9316925 # DTB read hits
> system.cpu.dtb.read_misses 17695 # DTB read misses
324,336c326,338
< system.cpu.dtb.read_accesses 764388 # DTB read accesses
< system.cpu.dtb.write_hits 6394455 # DTB write hits
< system.cpu.dtb.write_misses 2545 # DTB write misses
< system.cpu.dtb.write_acv 159 # DTB write access violations
< system.cpu.dtb.write_accesses 298887 # DTB write accesses
< system.cpu.dtb.data_hits 15714630 # DTB hits
< system.cpu.dtb.data_misses 19972 # DTB misses
< system.cpu.dtb.data_acv 370 # DTB access violations
< system.cpu.dtb.data_accesses 1063275 # DTB accesses
< system.cpu.itb.fetch_hits 4019631 # ITB hits
< system.cpu.itb.fetch_misses 6355 # ITB misses
< system.cpu.itb.fetch_acv 661 # ITB acv
< system.cpu.itb.fetch_accesses 4025986 # ITB accesses
---
> system.cpu.dtb.read_accesses 764827 # DTB read accesses
> system.cpu.dtb.write_hits 6393212 # DTB write hits
> system.cpu.dtb.write_misses 2442 # DTB write misses
> system.cpu.dtb.write_acv 158 # DTB write access violations
> system.cpu.dtb.write_accesses 298820 # DTB write accesses
> system.cpu.dtb.data_hits 15710137 # DTB hits
> system.cpu.dtb.data_misses 20137 # DTB misses
> system.cpu.dtb.data_acv 369 # DTB access violations
> system.cpu.dtb.data_accesses 1063647 # DTB accesses
> system.cpu.itb.fetch_hits 4018824 # ITB hits
> system.cpu.itb.fetch_misses 6310 # ITB misses
> system.cpu.itb.fetch_acv 701 # ITB acv
> system.cpu.itb.fetch_accesses 4025134 # ITB accesses
349,355c351,356
< system.cpu.numPwrStateTransitions 12756 # Number of power state transitions
< system.cpu.pwrStateClkGateDist::samples 6378 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::mean 281603673.878959 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 439873554.784215 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1000-5e+10 6377 99.98% 100.00% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
---
> system.cpu.numPwrStateTransitions 12752 # Number of power state transitions
> system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::mean 281746974.905897 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 439847984.325030 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::min_value 19000 # Distribution of time spent in the clock gated state
357,360c358,361
< system.cpu.pwrStateClkGateDist::total 6378 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateResidencyTicks::ON 112993228000 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 1796068232000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 226008061 # number of cpu cycles simulated
---
> system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateResidencyTicks::ON 92804534000 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 1796418712000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 185630526 # number of cpu cycles simulated
363,372c364,373
< system.cpu.committedInsts 56149847 # Number of instructions committed
< system.cpu.committedOps 56149847 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 2969857 # Number of ops (including micro ops) which were discarded before commit
< system.cpu.numFetchSuspends 6378 # Number of times Execute suspended instruction fetching
< system.cpu.quiesceCycles 3592114868 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 4.025088 # CPI: cycles per instruction
< system.cpu.ipc 0.248442 # IPC: instructions per cycle
< system.cpu.op_class_0::No_OpClass 3199355 5.70% 5.70% # Class of committed instruction
< system.cpu.op_class_0::IntAlu 36201883 64.47% 70.17% # Class of committed instruction
< system.cpu.op_class_0::IntMult 60840 0.11% 70.28% # Class of committed instruction
---
> system.cpu.committedInsts 56141873 # Number of instructions committed
> system.cpu.committedOps 56141873 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 2958149 # Number of ops (including micro ops) which were discarded before commit
> system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching
> system.cpu.quiesceCycles 3592815966 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 3.306454 # CPI: cycles per instruction
> system.cpu.ipc 0.302439 # IPC: instructions per cycle
> system.cpu.op_class_0::No_OpClass 3199005 5.70% 5.70% # Class of committed instruction
> system.cpu.op_class_0::IntAlu 36197195 64.47% 70.17% # Class of committed instruction
> system.cpu.op_class_0::IntMult 60822 0.11% 70.28% # Class of committed instruction
378,402c379,403
< system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
< system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
< system.cpu.op_class_0::MemRead 9320961 16.60% 86.95% # Class of committed instruction
< system.cpu.op_class_0::MemWrite 6373595 11.35% 98.31% # Class of committed instruction
< system.cpu.op_class_0::IprAccess 951498 1.69% 100.00% # Class of committed instruction
---
> system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction
> system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction
> system.cpu.op_class_0::MemRead 9319321 16.60% 86.95% # Class of committed instruction
> system.cpu.op_class_0::MemWrite 6372729 11.35% 98.31% # Class of committed instruction
> system.cpu.op_class_0::IprAccess 951086 1.69% 100.00% # Class of committed instruction
404c405
< system.cpu.op_class_0::total 56149847 # Class of committed instruction
---
> system.cpu.op_class_0::total 56141873 # Class of committed instruction
406,413c407,414
< system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211594 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74821 40.93% 40.93% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::22 1907 1.04% 42.04% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 105943 57.96% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182802 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73454 49.32% 49.32% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 211498 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74792 40.94% 40.94% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::22 1903 1.04% 42.05% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 105883 57.95% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182709 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73425 49.32% 49.32% # number of times we switched to this ipl from a different ipl
415,423c416,424
< system.cpu.kern.ipl_good::22 1907 1.28% 50.68% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73454 49.32% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 148946 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1839859866500 96.38% 96.38% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 85941500 0.00% 96.38% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 711439500 0.04% 96.42% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 68403193000 3.58% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1909060440500 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981730 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::22 1903 1.28% 50.68% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73425 49.32% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 148884 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1835945903000 97.18% 97.18% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 85568000 0.00% 97.18% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 710063500 0.04% 97.22% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 52480708000 2.78% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1889222242500 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl
426,427c427,428
< system.cpu.kern.ipl_used::31 0.693335 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814794 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.693454 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814870 # fraction of swpipl calls that actually changed the ipl
466,467c467,468
< system.cpu.kern.callpal::swpipl 175631 91.22% 93.43% # number of callpals executed
< system.cpu.kern.callpal::rdps 6810 3.54% 96.96% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175546 91.22% 93.43% # number of callpals executed
> system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed
472c473
< system.cpu.kern.callpal::rti 5132 2.67% 99.64% # number of callpals executed
---
> system.cpu.kern.callpal::rti 5128 2.66% 99.64% # number of callpals executed
475,480c476,481
< system.cpu.kern.callpal::total 192526 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5877 # number of protection mode switches
< system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
< system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
< system.cpu.kern.mode_good::kernel 1906
< system.cpu.kern.mode_good::user 1738
---
> system.cpu.kern.callpal::total 192434 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches
> system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
> system.cpu.kern.mode_switch::idle 2091 # number of protection mode switches
> system.cpu.kern.mode_good::kernel 1905
> system.cpu.kern.mode_good::user 1737
482c483
< system.cpu.kern.mode_switch_good::kernel 0.324315 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch_good::kernel 0.324200 # fraction of useful protection mode switches
484,488c485,489
< system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.392625 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 38921683000 2.04% 2.04% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 4598347000 0.24% 2.28% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1865540400500 97.72% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_switch_good::idle 0.080344 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.392622 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 36856948000 1.95% 1.95% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 4192339500 0.22% 2.17% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1848172945000 97.83% 100.00% # number of ticks spent at the given mode
490,501c491,502
< system.cpu.tickCycles 85327235 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 140680826 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 1394976 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.976740 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 13944378 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1395488 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 9.992474 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 124106500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.976740 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy
---
> system.cpu.tickCycles 85233988 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 100396538 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 1394263 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.980931 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 13942036 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1394775 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 9.995903 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 94238500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.980931 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy
503,504c504,505
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
507,573c508,574
< system.cpu.dcache.tags.tag_accesses 63924438 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63924438 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 7983946 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7983946 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5577839 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5577839 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 183518 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 183518 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 199043 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 199043 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 13561785 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13561785 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13561785 # number of overall hits
< system.cpu.dcache.overall_hits::total 13561785 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1096703 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1096703 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 574639 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 574639 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 16549 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 16549 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1671342 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1671342 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1671342 # number of overall misses
< system.cpu.dcache.overall_misses::total 1671342 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 45383174000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 45383174000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 33964439500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 33964439500 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 226601500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 226601500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 79347613500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 79347613500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 79347613500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 79347613500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 9080649 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9080649 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6152478 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6152478 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200067 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200067 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 199043 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 199043 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15233127 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15233127 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15233127 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15233127 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120774 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.120774 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093400 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.093400 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082717 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082717 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.109718 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.109718 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.109718 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.109718 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41381.462438 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 41381.462438 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59105.698534 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 59105.698534 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13692.760892 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13692.760892 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 47475.390136 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 47475.390136 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 47475.390136 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 47475.390136 # average overall miss latency
---
> system.cpu.dcache.tags.tag_accesses 63909041 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63909041 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 7981560 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7981560 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5577988 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5577988 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 183448 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 183448 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 199007 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 199007 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 13559548 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13559548 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13559548 # number of overall hits
> system.cpu.dcache.overall_hits::total 13559548 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1096304 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1096304 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 573678 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 573678 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 16581 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 16581 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1669982 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1669982 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1669982 # number of overall misses
> system.cpu.dcache.overall_misses::total 1669982 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 31558344500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 31558344500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 22538815500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 22538815500 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222577500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 222577500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 54097160000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 54097160000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 54097160000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 54097160000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 9077864 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9077864 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6151666 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6151666 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200029 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200029 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 199007 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 199007 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15229530 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15229530 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15229530 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15229530 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120767 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.120767 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093256 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.093256 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082893 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082893 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.109654 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.109654 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.109654 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.109654 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28786.125472 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 28786.125472 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39288.268855 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 39288.268855 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.647548 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13423.647548 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 32393.858137 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 32393.858137 # average overall miss latency
580,585c581,586
< system.cpu.dcache.writebacks::writebacks 838068 # number of writebacks
< system.cpu.dcache.writebacks::total 838068 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21939 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 21939 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270415 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 270415 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 837697 # number of writebacks
> system.cpu.dcache.writebacks::total 837697 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269759 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 269759 # number of WriteReq MSHR hits
588,601c589,602
< system.cpu.dcache.demand_mshr_hits::cpu.data 292354 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 292354 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 292354 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 292354 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074764 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1074764 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304224 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304224 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16546 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 16546 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1378988 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1378988 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1378988 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1378988 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 291740 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 291740 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 291740 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 291740 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074323 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1074323 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303919 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 303919 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16578 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 16578 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1378242 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1378242 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1378242 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1378242 # number of overall MSHR misses
604,655c605,656
< system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9625 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::total 9625 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses
< system.cpu.dcache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43721360500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 43721360500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17277660500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 17277660500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 209790000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 209790000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60999021000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 60999021000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60999021000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 60999021000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1527294000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1527294000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1527294000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 1527294000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118358 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118358 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049447 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049447 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082702 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082702 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090526 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.090526 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090526 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.090526 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40679.963694 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40679.963694 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56792.562388 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56792.562388 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12679.197389 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12679.197389 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44234.627858 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 44234.627858 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44234.627858 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 44234.627858 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220388.744589 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220388.744589 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92255.753549 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92255.753549 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 1477492 # number of replacements
< system.cpu.icache.tags.tagsinuse 508.111413 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 19219698 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1478003 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 13.003829 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 50147606500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 508.111413 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.992405 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.992405 # Average percentage of cache occupancy
---
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16551 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 16551 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30011433500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 30011433500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11481403000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11481403000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205832000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205832000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41492836500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 41492836500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41492836500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 41492836500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534160500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534160500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534160500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534160500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118345 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118345 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049404 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049404 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082878 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082878 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.090498 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.090498 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27935.205241 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27935.205241 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37777.838832 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37777.838832 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12415.972976 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12415.972976 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.581530 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.581530 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92692.918857 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92692.918857 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 1476241 # number of replacements
> system.cpu.icache.tags.tagsinuse 509.437018 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 19208652 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1476752 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 13.007365 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 33938325500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 509.437018 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.994994 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.994994 # Average percentage of cache occupancy
657,658c658,660
< system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 401 # Occupied blocks per task id
660,698c662,700
< system.cpu.icache.tags.tag_accesses 22176055 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 22176055 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 19219701 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 19219701 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 19219701 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 19219701 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 19219701 # number of overall hits
< system.cpu.icache.overall_hits::total 19219701 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1478177 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1478177 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1478177 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1478177 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1478177 # number of overall misses
< system.cpu.icache.overall_misses::total 1478177 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21231255000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21231255000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21231255000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21231255000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21231255000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21231255000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 20697878 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 20697878 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 20697878 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 20697878 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 20697878 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 20697878 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071417 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.071417 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.071417 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.071417 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.071417 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.071417 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14363.134455 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14363.134455 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14363.134455 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14363.134455 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14363.134455 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14363.134455 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 22162507 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 22162507 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 19208655 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 19208655 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 19208655 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 19208655 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 19208655 # number of overall hits
> system.cpu.icache.overall_hits::total 19208655 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1476926 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1476926 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1476926 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1476926 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1476926 # number of overall misses
> system.cpu.icache.overall_misses::total 1476926 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 20401531500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 20401531500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 20401531500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 20401531500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 20401531500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 20401531500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 20685581 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 20685581 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 20685581 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 20685581 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 20685581 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 20685581 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071399 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.071399 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.071399 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.071399 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.071399 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.071399 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13813.509614 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13813.509614 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13813.509614 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13813.509614 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13813.509614 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13813.509614 # average overall miss latency
705,781c707,783
< system.cpu.icache.writebacks::writebacks 1477492 # number of writebacks
< system.cpu.icache.writebacks::total 1477492 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1478177 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1478177 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1478177 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1478177 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1478177 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1478177 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19753078000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19753078000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19753078000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19753078000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19753078000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19753078000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071417 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071417 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071417 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.071417 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071417 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.071417 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13363.134455 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13363.134455 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13363.134455 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13363.134455 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13363.134455 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13363.134455 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 339587 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65260.798092 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 5032980 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 404749 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 12.434818 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 9689078000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 54026.178970 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 5735.607676 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5499.011446 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.824374 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087518 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.083908 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.995801 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 888 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5593 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2924 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55531 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 46662747 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 46662747 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 838068 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 838068 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 1476917 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 1476917 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187586 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187586 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461767 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1461767 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819079 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 819079 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 1461767 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1006665 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2468432 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 1461767 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1006665 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2468432 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 15 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 15 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116651 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116651 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16355 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 16355 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272198 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 272198 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 16355 # number of demand (read+write) misses
---
> system.cpu.icache.writebacks::writebacks 1476241 # number of writebacks
> system.cpu.icache.writebacks::total 1476241 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1476926 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1476926 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1476926 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1476926 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1476926 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1476926 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18924605500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 18924605500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18924605500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 18924605500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18924605500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 18924605500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071399 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071399 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071399 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.071399 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071399 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.071399 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12813.509614 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12813.509614 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12813.509614 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12813.509614 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12813.509614 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12813.509614 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 339622 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65416.328180 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 5334629 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 405144 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 13.167242 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 6356009000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 267.504634 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 5791.332200 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 59357.491346 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.004082 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088369 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.905723 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.998174 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 631 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5153 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59330 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 46327377 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 46327377 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 837697 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 837697 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 1475656 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 1475656 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187300 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187300 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1460502 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1460502 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818651 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 818651 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 1460502 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1005951 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2466453 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 1460502 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1005951 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2466453 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116630 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116630 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16369 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 16369 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272219 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 272219 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 16369 # number of demand (read+write) misses
783,784c785,786
< system.cpu.l2cache.demand_misses::total 405204 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 16355 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 405218 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 16369 # number of overall misses
786,804c788,806
< system.cpu.l2cache.overall_misses::total 405204 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 396500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 396500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14845341000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 14845341000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2146863500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2146863500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33671183000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 33671183000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2146863500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 48516524000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 50663387500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2146863500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 48516524000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 50663387500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 838068 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 838068 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 1476917 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 1476917 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 405218 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 249500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 249500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9053314500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9053314500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1334237500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 1334237500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19962557500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 19962557500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1334237500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 29015872000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 30350109500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1334237500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 29015872000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 30350109500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 837697 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 837697 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 1475656 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 1475656 # number of WritebackClean accesses(hits+misses)
807,846c809,848
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 304237 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304237 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1478122 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1478122 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091277 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1091277 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1478122 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1395514 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2873636 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1478122 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1395514 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2873636 # number of overall (read+write) accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383421 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383421 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011065 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011065 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249431 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249431 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011065 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.278642 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.141007 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011065 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.278642 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.141007 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 26433.333333 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 26433.333333 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127262.869585 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127262.869585 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131266.493427 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131266.493427 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123701.066870 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123701.066870 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131266.493427 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124769.573793 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 125031.804967 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131266.493427 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124769.573793 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 125031.804967 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 303930 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 303930 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1476871 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1476871 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1090870 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1090870 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1476871 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1394800 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2871671 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1476871 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1394800 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2871671 # number of overall (read+write) accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383740 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383740 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011084 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011084 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249543 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249543 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011084 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.278785 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.141109 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011084 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.278785 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.141109 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49900 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49900 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77624.234759 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77624.234759 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81510.018938 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81510.018938 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73332.711897 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73332.711897 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81510.018938 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74619.896155 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74898.226387 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81510.018938 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74619.896155 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74898.226387 # average overall miss latency
853,863c855,865
< system.cpu.l2cache.writebacks::writebacks 76665 # number of writebacks
< system.cpu.l2cache.writebacks::total 76665 # number of writebacks
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 15 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 15 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116651 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116651 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16355 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16355 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272198 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272198 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 16355 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 76715 # number of writebacks
> system.cpu.l2cache.writebacks::total 76715 # number of writebacks
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116630 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116630 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16369 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16369 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272219 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272219 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 16369 # number of demand (read+write) MSHR misses
865,866c867,868
< system.cpu.l2cache.demand_mshr_misses::total 405204 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 16355 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 405218 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 16369 # number of overall MSHR misses
868c870
< system.cpu.l2cache.overall_mshr_misses::total 405204 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::total 405218 # number of overall MSHR misses
871,929c873,931
< system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9625 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9625 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1032500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1032500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13678831000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13678831000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1983313500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1983313500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30952316500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30952316500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1983313500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631147500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 46614461000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1983313500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631147500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 46614461000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440649500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440649500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1440649500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1440649500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383421 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383421 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011065 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011065 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249431 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249431 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011065 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278642 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.141007 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011065 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278642 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.141007 # mshr miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68833.333333 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68833.333333 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117262.869585 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117262.869585 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121266.493427 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121266.493427 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113712.505235 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113712.505235 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121266.493427 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114777.580758 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115039.488751 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121266.493427 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114777.580758 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115039.488751 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207885.930736 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207885.930736 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87022.017517 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87022.017517 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 5746179 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2872664 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1960 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16551 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16551 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 199500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 199500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7887014500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7887014500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1170547500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1170547500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17243377000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17243377000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1170547500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25130391500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26300939000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1170547500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25130391500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26300939000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447515000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447515000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447515000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447515000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383740 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383740 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011084 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249543 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249543 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278785 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.141109 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278785 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.141109 # mshr miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39900 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39900 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67624.234759 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67624.234759 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71510.018938 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71510.018938 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63343.767334 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63343.767334 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87457.857531 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87457.857531 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 5742250 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2870700 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1972 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
931c933
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
933,938c935,940
< system.cpu.toL2Bus.trans_dist::ReadResp 2576516 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 9625 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 9625 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 956247 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 1477492 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 820003 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2574859 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 914412 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 1476241 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 819473 # Transaction distribution
941,957c943,959
< system.cpu.toL2Bus.trans_dist::ReadExReq 304237 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 304237 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1478177 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091450 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4433791 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219310 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8653101 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189159296 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143002060 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 332161356 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 423210 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 3313265 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.001022 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.031947 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 303930 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 303930 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1476926 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091030 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 241 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4430038 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217161 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8647199 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 188999168 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142932652 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 331931820 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 340234 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 4923264 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 3228320 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.000974 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.031197 # Request fanout histogram
959,960c961,962
< system.cpu.toL2Bus.snoop_fanout::0 3309880 99.90% 99.90% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 3385 0.10% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 3225175 99.90% 99.90% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3145 0.10% 100.00% # Request fanout histogram
965,966c967,968
< system.cpu.toL2Bus.snoop_fanout::total 3313265 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 5201739500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 3228320 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 5198149000 # Layer occupancy (ticks)
970c972
< system.cpu.toL2Bus.respLayer0.occupancy 2217424681 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2215530716 # Layer occupancy (ticks)
972c974
< system.cpu.toL2Bus.respLayer1.occupancy 2105003991 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2103938977 # Layer occupancy (ticks)
986c988
< system.iobus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
989,991c991,993
< system.iobus.trans_dist::WriteReq 51177 # Transaction distribution
< system.iobus.trans_dist::WriteResp 51177 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5106 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::WriteReq 51173 # Transaction distribution
> system.iobus.trans_dist::WriteResp 51173 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5098 # Packet count per connected master and slave (bytes)
1000c1002
< system.iobus.pkt_count_system.bridge.master::total 33110 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 33102 # Packet count per connected master and slave (bytes)
1003,1004c1005,1006
< system.iobus.pkt_count::total 116560 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20424 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 116552 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20392 # Cumulative packet size per connected master and slave (bytes)
1013c1015
< system.iobus.pkt_size_system.bridge.master::total 44364 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 44332 # Cumulative packet size per connected master and slave (bytes)
1016,1017c1018,1019
< system.iobus.pkt_size::total 2705972 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 5417500 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2705940 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 5405000 # Layer occupancy (ticks)
1019c1021
< system.iobus.reqLayer1.occupancy 799000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 800000 # Layer occupancy (ticks)
1021c1023
< system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 10000 # Layer occupancy (ticks)
1027c1029
< system.iobus.reqLayer23.occupancy 15625500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 14495500 # Layer occupancy (ticks)
1031c1033
< system.iobus.reqLayer25.occupancy 6004000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 5973000 # Layer occupancy (ticks)
1035c1037
< system.iobus.reqLayer27.occupancy 215719668 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 216181312 # Layer occupancy (ticks)
1037c1039
< system.iobus.respLayer0.occupancy 23485000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 23481000 # Layer occupancy (ticks)
1041c1043
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
1043c1045
< system.iocache.tags.tagsinuse 1.297488 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.301361 # Cycle average of tags in use
1047,1050c1049,1052
< system.iocache.tags.warmup_cycle 1750571994000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.297488 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.081093 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.081093 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1731952426000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.301361 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.081335 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.081335 # Average percentage of cache occupancy
1056c1058
< system.iocache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
1065,1072c1067,1074
< system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244162285 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 5244162285 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 5266079668 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 5266079668 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 5266079668 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 5266079668 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21934383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21934383 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::tsunami.ide 4859195929 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4859195929 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 4881130312 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4881130312 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 4881130312 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4881130312 # number of overall miss cycles
1089,1097c1091,1099
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126207.217101 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 126207.217101 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 126209.219125 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 126209.219125 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 126209.219125 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 126209.219125 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126788.341040 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 126788.341040 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116942.528133 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 116942.528133 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 116983.350797 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 116983.350797 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked
1099c1101
< system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
1101c1103
< system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked
1113,1120c1115,1122
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3164763984 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 3164763984 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 3178031367 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 3178031367 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 3178031367 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 3178031367 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13284383 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 13284383 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2779181979 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2779181979 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 2792466362 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2792466362 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 2792466362 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2792466362 # number of overall MSHR miss cycles
1129,1137c1131,1145
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76163.938776 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76163.938776 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76166.120240 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 76166.120240 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76166.120240 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 76166.120240 # average overall mshr miss latency
< system.membus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76788.341040 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 76788.341040 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66884.433457 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66884.433457 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 827436 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 381422 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
1139,1144c1147,1152
< system.membus.trans_dist::ReadResp 295632 # Transaction distribution
< system.membus.trans_dist::WriteReq 9625 # Transaction distribution
< system.membus.trans_dist::WriteResp 9625 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 118177 # Transaction distribution
< system.membus.trans_dist::CleanEvict 262256 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 167 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 295668 # Transaction distribution
> system.membus.trans_dist::WriteReq 9621 # Transaction distribution
> system.membus.trans_dist::WriteResp 9621 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution
> system.membus.trans_dist::CleanEvict 262241 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 137 # Transaction distribution
1146,1149c1154,1157
< system.membus.trans_dist::ReadExReq 116499 # Transaction distribution
< system.membus.trans_dist::ReadExResp 116499 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 288726 # Transaction distribution
< system.membus.trans_dist::BadAddressError 24 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 116498 # Transaction distribution
> system.membus.trans_dist::ReadExResp 116498 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 288761 # Transaction distribution
> system.membus.trans_dist::BadAddressError 23 # Transaction distribution
1151,1154c1159,1162
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33110 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148698 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181856 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33102 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148773 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181921 # Packet count per connected master and slave (bytes)
1157,1160c1165,1168
< system.membus.pkt_count::total 1265281 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44364 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30810880 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30855244 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1265346 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44332 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816320 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860652 # Cumulative packet size per connected master and slave (bytes)
1163c1171
< system.membus.pkt_size::total 33512972 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 33518380 # Cumulative packet size per connected master and slave (bytes)
1166,1168c1174,1176
< system.membus.snoop_fanout::samples 843934 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 463499 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.001458 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.038162 # Request fanout histogram
1170,1171c1178,1179
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 843934 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 462823 99.85% 99.85% # Request fanout histogram
> system.membus.snoop_fanout::1 676 0.15% 100.00% # Request fanout histogram
1174c1182
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1176,1177c1184,1185
< system.membus.snoop_fanout::total 843934 # Request fanout histogram
< system.membus.reqLayer0.occupancy 30445500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 463499 # Request fanout histogram
> system.membus.reqLayer0.occupancy 29272500 # Layer occupancy (ticks)
1179c1187
< system.membus.reqLayer1.occupancy 1319244966 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1319341290 # Layer occupancy (ticks)
1181c1189
< system.membus.reqLayer2.occupancy 29500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 31000 # Layer occupancy (ticks)
1183c1191
< system.membus.respLayer1.occupancy 2159924750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2160301000 # Layer occupancy (ticks)
1187,1191c1195,1199
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
1223,1245c1231,1253
< system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
< system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states
---
> system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states
> system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states