7,9c7,9
< host_inst_rate 20030 # Simulator instruction rate (inst/s)
< host_op_rate 20030 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 680419212 # Simulator tick rate (ticks/s)
---
> host_inst_rate 20979 # Simulator instruction rate (inst/s)
> host_op_rate 20979 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 712669715 # Simulator tick rate (ticks/s)
11c11
< host_seconds 2802.81 # Real time elapsed on the host
---
> host_seconds 2675.97 # Real time elapsed on the host
566,567d565
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
608,611c606,607
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2161966000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2161966000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3690574000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3690574000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528608000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528608000 # number of overall MSHR uncacheable cycles
634,638c630,631
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224666.528110 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224666.528110 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222954.993053 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222954.993053 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641 # average overall mshr uncacheable latency
697,698d689
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
725d715
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
846,847d835
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
886,889c874,875
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051300500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051300500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3493264000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3493264000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1441963500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1441963500 # number of overall MSHR uncacheable cycles
920,924c906,907
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213166.424192 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213166.424192 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211035.099378 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211035.099378 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87111.913248 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87111.913248 # average overall mshr uncacheable latency
1056,1059c1039,1042
< system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
< system.iocache.demand_misses::total 173 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
< system.iocache.overall_misses::total 173 # number of overall misses
---
> system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
> system.iocache.overall_misses::total 41725 # number of overall misses
1064,1067c1047,1050
< system.iocache.demand_miss_latency::tsunami.ide 21917383 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21917383 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21917383 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21917383 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::tsunami.ide 5267241666 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 5267241666 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 5267241666 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 5267241666 # number of overall miss cycles
1072,1075c1055,1058
< system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
1088,1091c1071,1074
< system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 126690.075145 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 126690.075145 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126237.068089 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126237.068089 # average overall miss latency
1098,1099d1080
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1106,1109c1087,1090
< system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
1114,1117c1095,1098
< system.iocache.demand_mshr_miss_latency::tsunami.ide 13267383 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 13267383 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 13267383 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 13267383 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::tsunami.ide 3179192366 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3179192366 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 3179192366 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3179192366 # number of overall MSHR miss cycles
1130,1134c1111,1114
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency
< host_inst_rate 20030 # Simulator instruction rate (inst/s)
< host_op_rate 20030 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 680419212 # Simulator tick rate (ticks/s)
---
> host_inst_rate 20979 # Simulator instruction rate (inst/s)
> host_op_rate 20979 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 712669715 # Simulator tick rate (ticks/s)
11c11
< host_seconds 2802.81 # Real time elapsed on the host
---
> host_seconds 2675.97 # Real time elapsed on the host
566,567d565
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
608,611c606,607
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2161966000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2161966000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3690574000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3690574000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528608000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528608000 # number of overall MSHR uncacheable cycles
634,638c630,631
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224666.528110 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224666.528110 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222954.993053 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222954.993053 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641 # average overall mshr uncacheable latency
697,698d689
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
725d715
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
846,847d835
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
886,889c874,875
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051300500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051300500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3493264000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3493264000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1441963500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1441963500 # number of overall MSHR uncacheable cycles
920,924c906,907
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213166.424192 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213166.424192 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211035.099378 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211035.099378 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87111.913248 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87111.913248 # average overall mshr uncacheable latency
1056,1059c1039,1042
< system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
< system.iocache.demand_misses::total 173 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
< system.iocache.overall_misses::total 173 # number of overall misses
---
> system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
> system.iocache.overall_misses::total 41725 # number of overall misses
1064,1067c1047,1050
< system.iocache.demand_miss_latency::tsunami.ide 21917383 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21917383 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21917383 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21917383 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::tsunami.ide 5267241666 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 5267241666 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 5267241666 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 5267241666 # number of overall miss cycles
1072,1075c1055,1058
< system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
1088,1091c1071,1074
< system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 126690.075145 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 126690.075145 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126237.068089 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126237.068089 # average overall miss latency
1098,1099d1080
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1106,1109c1087,1090
< system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
1114,1117c1095,1098
< system.iocache.demand_mshr_miss_latency::tsunami.ide 13267383 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 13267383 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 13267383 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 13267383 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::tsunami.ide 3179192366 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3179192366 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 3179192366 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3179192366 # number of overall MSHR miss cycles
1130,1134c1111,1114
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency