7,11c7,11
< host_inst_rate 269376 # Simulator instruction rate (inst/s)
< host_op_rate 269376 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 9144869235 # Simulator tick rate (ticks/s)
< host_mem_usage 376080 # Number of bytes of host memory used
< host_seconds 208.43 # Real time elapsed on the host
---
> host_inst_rate 268534 # Simulator instruction rate (inst/s)
> host_op_rate 268534 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9116285517 # Simulator tick rate (ticks/s)
> host_mem_usage 332204 # Number of bytes of host memory used
> host_seconds 209.08 # Real time elapsed on the host
153c153
< system.physmem.wrQLenPdf::17 5601 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::17 5600 # What write queue length does an incoming req see
156c156
< system.physmem.wrQLenPdf::20 6564 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::20 6565 # What write queue length does an incoming req see
200,213c200,213
< system.physmem.bytesPerActivate::samples 64393 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 519.603311 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 318.318586 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 407.156918 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14830 23.03% 23.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11097 17.23% 40.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4950 7.69% 47.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3246 5.04% 52.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2531 3.93% 56.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1970 3.06% 59.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 4174 6.48% 66.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1358 2.11% 68.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 20237 31.43% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 64393 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 64400 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 519.546832 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 318.268868 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 407.153797 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14837 23.04% 23.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11098 17.23% 40.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4944 7.68% 47.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3257 5.06% 53.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2526 3.92% 56.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1968 3.06% 59.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 4176 6.48% 66.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1357 2.11% 68.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 20237 31.42% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 64400 # Bytes accessed per row activation
263,264c263,264
< system.physmem.totQLat 2636864500 # Total ticks spent queuing
< system.physmem.totMemAccLat 10223958250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2637486000 # Total ticks spent queuing
> system.physmem.totMemAccLat 10224579750 # Total ticks spent from burst creation until serviced by the DRAM
266c266
< system.physmem.avgQLat 6516.49 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6518.02 # Average queueing delay per DRAM burst
268c268
< system.physmem.avgMemAccLat 25266.49 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25268.02 # Average memory access latency per DRAM burst
279,280c279,280
< system.physmem.readRowHits 362818 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95583 # Number of row buffer hits during writes
---
> system.physmem.readRowHits 362820 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95574 # Number of row buffer hits during writes
285,286c285,286
< system.physmem_0.actEnergy 237542760 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 129611625 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.actEnergy 237573000 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 129628125 # Energy for precharge commands per rank (pJ)
290,294c290,294
< system.physmem_0.actBackEnergy 67952834145 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1084018111500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1278788448510 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.912661 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1803102997000 # Time in different power states
---
> system.physmem_0.actBackEnergy 67955758245 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1084015546500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1278788854350 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.912874 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1803098707000 # Time in different power states
297c297
< system.physmem_0.memoryStateTime::ACT 39293158000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 39297448000 # Time in different power states
299,300c299,300
< system.physmem_1.actEnergy 249268320 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 136009500 # Energy for precharge commands per rank (pJ)
---
> system.physmem_1.actEnergy 249291000 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 136021875 # Energy for precharge commands per rank (pJ)
304,308c304,308
< system.physmem_1.actBackEnergy 68401366290 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1083624670500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1278869710170 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.955290 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1802449451000 # Time in different power states
---
> system.physmem_1.actBackEnergy 68412640320 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1083614781000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1278871129755 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.956034 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1802432810250 # Time in different power states
311c311
< system.physmem_1.memoryStateTime::ACT 39946717750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 39963358500 # Time in different power states
378c378
< system.cpu.kern.ipl_ticks::0 1837271257000 96.39% 96.39% # number of cycles we spent at this ipl
---
> system.cpu.kern.ipl_ticks::0 1837271633000 96.39% 96.39% # number of cycles we spent at this ipl
381c381
< system.cpu.kern.ipl_ticks::31 67985555000 3.57% 100.00% # number of cycles we spent at this ipl
---
> system.cpu.kern.ipl_ticks::31 67985179000 3.57% 100.00% # number of cycles we spent at this ipl
450,451c450,451
< system.cpu.tickCycles 84511190 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 137195507 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 84511215 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 137195482 # Total number of cycles that the object has spent stopped
490,493c490,493
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974936500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 46974936500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956179000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 33956179000 # number of WriteReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974912500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 46974912500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956321000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 33956321000 # number of WriteReq miss cycles
496,499c496,499
< system.cpu.dcache.demand_miss_latency::cpu.data 80931115500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 80931115500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 80931115500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 80931115500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 80931233500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 80931233500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 80931233500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 80931233500 # number of overall miss cycles
522,525c522,525
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.646994 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.646994 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.177737 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.177737 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.627021 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.627021 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.424605 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.424605 # average WriteReq miss latency
528,531c528,531
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 45547.881459 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 45547.881459 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 45547.947869 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 45547.947869 # average overall miss latency
568,571c568,571
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817588500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817588500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272399000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272399000 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817391500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817391500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272477000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272477000 # number of WriteReq MSHR miss cycles
574,579c574,579
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089987500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 61089987500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089987500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 61089987500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1530266500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1530266500 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089868500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 61089868500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089868500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 61089868500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529366500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529366500 # number of ReadReq MSHR uncacheable cycles
582,583c582,583
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3692775000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3692775000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3691875000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3691875000 # number of overall MSHR uncacheable cycles
594,597c594,597
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40785.018453 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40785.018453 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.508845 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.508845 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40784.835087 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40784.835087 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.765083 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.765083 # average WriteReq mshr miss latency
600,605c600,605
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.919797 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.919797 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.919797 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.919797 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220690.294202 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220690.294202 # average ReadReq mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.498990 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.498990 # average ReadReq mshr uncacheable latency
608,609c608,609
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223020.594275 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223020.594275 # average overall mshr uncacheable latency
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222966.239884 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222966.239884 # average overall mshr uncacheable latency
613c613
< system.cpu.icache.tags.total_refs 18947784 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 18947783 # Total number of references to valid blocks.
615c615
< system.cpu.icache.tags.avg_refs 12.969877 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 12.969876 # Average number of references to valid blocks.
625,632c625,632
< system.cpu.icache.tags.tag_accesses 21869953 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 21869953 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 18947787 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 18947787 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 18947787 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 18947787 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 18947787 # number of overall hits
< system.cpu.icache.overall_hits::total 18947787 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 21869952 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 21869952 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 18947786 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 18947786 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 18947786 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 18947786 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 18947786 # number of overall hits
> system.cpu.icache.overall_hits::total 18947786 # number of overall hits
639,650c639,650
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009217000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21009217000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21009217000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21009217000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21009217000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21009217000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 20408870 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 20408870 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 20408870 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 20408870 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 20408870 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 20408870 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009954000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 21009954000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 21009954000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 21009954000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 21009954000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 21009954000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 20408869 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 20408869 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 20408869 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 20408869 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 20408869 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 20408869 # number of overall (read+write) accesses
657,662c657,662
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.208436 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14379.208436 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.208436 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14379.208436 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.208436 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14379.208436 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.712857 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14379.712857 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14379.712857 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14379.712857 # average overall miss latency
679,684c679,684
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548134000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19548134000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548134000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19548134000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548134000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19548134000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548871000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 19548871000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548871000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 19548871000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548871000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 19548871000 # number of overall MSHR miss cycles
691,696c691,696
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.208436 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.208436 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.208436 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.208436 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.208436 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.208436 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.712857 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.712857 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency
699c699
< system.cpu.l2cache.tags.tagsinuse 65260.797469 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 65260.797416 # Cycle average of tags in use
704,706c704,706
< system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251550 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395782 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150137 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251440 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395876 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150100 # Average occupied blocks per requestor
754,765c754,765
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837528000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 14837528000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2141943000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2141943000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680651000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680651000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2141943000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 48518179000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 50660122000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2141943000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 48518179000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 50660122000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837606000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 14837606000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2142680000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2142680000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680454000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680454000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2142680000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 48518060000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 50660740000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2142680000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 48518060000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 50660740000 # number of overall miss cycles
800,811c800,811
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.169443 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.169443 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131214.346974 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131214.346974 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.759286 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.759286 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 125028.065846 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 125028.065846 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.838058 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.838058 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131259.495222 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131259.495222 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.035572 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.035572 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 125029.591056 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 125029.591056 # average overall miss latency
844,857c844,857
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13670938000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13670938000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1978703000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1978703000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960659500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960659500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1978703000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631597500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 46610300500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1978703000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631597500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 46610300500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1443571000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1443571000 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13671016000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13671016000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1979440000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1979440000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960462500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960462500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1979440000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631478500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 46610918500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1979440000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631478500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 46610918500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442671000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442671000 # number of ReadReq MSHR uncacheable cycles
860,861c860,861
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3495402500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3495402500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3494502500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494502500 # number of overall MSHR uncacheable cycles
878,891c878,891
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.169443 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.169443 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121214.346974 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121214.346974 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113739.395019 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113739.395019 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208187.337756 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208187.337756 # average ReadReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.838058 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.838058 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121259.495222 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121259.495222 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113738.671305 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113738.671305 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.542544 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.542544 # average ReadReq mshr uncacheable latency
894,895c894,895
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211100.525426 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211100.525426 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211046.171035 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211046.171035 # average overall mshr uncacheable latency
961c961
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
968d967
< system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
970,971d968
< system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
977c974
< system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
984d980
< system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
986,987d981
< system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
994c988
< system.iobus.reqLayer1.occupancy 386000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 784500 # Layer occupancy (ticks)
1008c1002
< system.iobus.reqLayer26.occupancy 224500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer26.occupancy 98500 # Layer occupancy (ticks)
1010c1004
< system.iobus.reqLayer27.occupancy 98500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 215092991 # Layer occupancy (ticks)
1012,1017d1005
< system.iobus.reqLayer28.occupancy 142500 # Layer occupancy (ticks)
< system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer29.occupancy 215092991 # Layer occupancy (ticks)
< system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer30.occupancy 31500 # Layer occupancy (ticks)
< system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1164c1152
< system.membus.respLayer1.occupancy 2160247074 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2160244574 # Layer occupancy (ticks)
< host_inst_rate 269376 # Simulator instruction rate (inst/s)
< host_op_rate 269376 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 9144869235 # Simulator tick rate (ticks/s)
< host_mem_usage 376080 # Number of bytes of host memory used
< host_seconds 208.43 # Real time elapsed on the host
---
> host_inst_rate 268534 # Simulator instruction rate (inst/s)
> host_op_rate 268534 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9116285517 # Simulator tick rate (ticks/s)
> host_mem_usage 332204 # Number of bytes of host memory used
> host_seconds 209.08 # Real time elapsed on the host
153c153
< system.physmem.wrQLenPdf::17 5601 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::17 5600 # What write queue length does an incoming req see
156c156
< system.physmem.wrQLenPdf::20 6564 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::20 6565 # What write queue length does an incoming req see
200,213c200,213
< system.physmem.bytesPerActivate::samples 64393 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 519.603311 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 318.318586 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 407.156918 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14830 23.03% 23.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11097 17.23% 40.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4950 7.69% 47.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3246 5.04% 52.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2531 3.93% 56.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1970 3.06% 59.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 4174 6.48% 66.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1358 2.11% 68.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 20237 31.43% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 64393 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 64400 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 519.546832 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 318.268868 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 407.153797 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14837 23.04% 23.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11098 17.23% 40.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4944 7.68% 47.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3257 5.06% 53.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2526 3.92% 56.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1968 3.06% 59.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 4176 6.48% 66.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1357 2.11% 68.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 20237 31.42% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 64400 # Bytes accessed per row activation
263,264c263,264
< system.physmem.totQLat 2636864500 # Total ticks spent queuing
< system.physmem.totMemAccLat 10223958250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2637486000 # Total ticks spent queuing
> system.physmem.totMemAccLat 10224579750 # Total ticks spent from burst creation until serviced by the DRAM
266c266
< system.physmem.avgQLat 6516.49 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6518.02 # Average queueing delay per DRAM burst
268c268
< system.physmem.avgMemAccLat 25266.49 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25268.02 # Average memory access latency per DRAM burst
279,280c279,280
< system.physmem.readRowHits 362818 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95583 # Number of row buffer hits during writes
---
> system.physmem.readRowHits 362820 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95574 # Number of row buffer hits during writes
285,286c285,286
< system.physmem_0.actEnergy 237542760 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 129611625 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.actEnergy 237573000 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 129628125 # Energy for precharge commands per rank (pJ)
290,294c290,294
< system.physmem_0.actBackEnergy 67952834145 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1084018111500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1278788448510 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.912661 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1803102997000 # Time in different power states
---
> system.physmem_0.actBackEnergy 67955758245 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1084015546500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1278788854350 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.912874 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1803098707000 # Time in different power states
297c297
< system.physmem_0.memoryStateTime::ACT 39293158000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 39297448000 # Time in different power states
299,300c299,300
< system.physmem_1.actEnergy 249268320 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 136009500 # Energy for precharge commands per rank (pJ)
---
> system.physmem_1.actEnergy 249291000 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 136021875 # Energy for precharge commands per rank (pJ)
304,308c304,308
< system.physmem_1.actBackEnergy 68401366290 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1083624670500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1278869710170 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.955290 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1802449451000 # Time in different power states
---
> system.physmem_1.actBackEnergy 68412640320 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1083614781000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1278871129755 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.956034 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1802432810250 # Time in different power states
311c311
< system.physmem_1.memoryStateTime::ACT 39946717750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 39963358500 # Time in different power states
378c378
< system.cpu.kern.ipl_ticks::0 1837271257000 96.39% 96.39% # number of cycles we spent at this ipl
---
> system.cpu.kern.ipl_ticks::0 1837271633000 96.39% 96.39% # number of cycles we spent at this ipl
381c381
< system.cpu.kern.ipl_ticks::31 67985555000 3.57% 100.00% # number of cycles we spent at this ipl
---
> system.cpu.kern.ipl_ticks::31 67985179000 3.57% 100.00% # number of cycles we spent at this ipl
450,451c450,451
< system.cpu.tickCycles 84511190 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 137195507 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 84511215 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 137195482 # Total number of cycles that the object has spent stopped
490,493c490,493
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974936500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 46974936500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956179000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 33956179000 # number of WriteReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974912500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 46974912500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956321000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 33956321000 # number of WriteReq miss cycles
496,499c496,499
< system.cpu.dcache.demand_miss_latency::cpu.data 80931115500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 80931115500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 80931115500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 80931115500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 80931233500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 80931233500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 80931233500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 80931233500 # number of overall miss cycles
522,525c522,525
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.646994 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.646994 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.177737 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.177737 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.627021 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.627021 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.424605 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.424605 # average WriteReq miss latency
528,531c528,531
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 45547.881459 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 45547.881459 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 45547.947869 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 45547.947869 # average overall miss latency
568,571c568,571
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817588500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817588500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272399000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272399000 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817391500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817391500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272477000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272477000 # number of WriteReq MSHR miss cycles
574,579c574,579
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089987500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 61089987500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089987500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 61089987500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1530266500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1530266500 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089868500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 61089868500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089868500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 61089868500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529366500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529366500 # number of ReadReq MSHR uncacheable cycles
582,583c582,583
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3692775000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3692775000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3691875000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3691875000 # number of overall MSHR uncacheable cycles
594,597c594,597
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40785.018453 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40785.018453 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.508845 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.508845 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40784.835087 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40784.835087 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.765083 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.765083 # average WriteReq mshr miss latency
600,605c600,605
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.919797 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.919797 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.919797 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.919797 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220690.294202 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220690.294202 # average ReadReq mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.498990 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.498990 # average ReadReq mshr uncacheable latency
608,609c608,609
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223020.594275 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223020.594275 # average overall mshr uncacheable latency
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222966.239884 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222966.239884 # average overall mshr uncacheable latency
613c613
< system.cpu.icache.tags.total_refs 18947784 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 18947783 # Total number of references to valid blocks.
615c615
< system.cpu.icache.tags.avg_refs 12.969877 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 12.969876 # Average number of references to valid blocks.
625,632c625,632
< system.cpu.icache.tags.tag_accesses 21869953 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 21869953 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 18947787 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 18947787 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 18947787 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 18947787 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 18947787 # number of overall hits
< system.cpu.icache.overall_hits::total 18947787 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 21869952 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 21869952 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 18947786 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 18947786 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 18947786 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 18947786 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 18947786 # number of overall hits
> system.cpu.icache.overall_hits::total 18947786 # number of overall hits
639,650c639,650
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009217000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21009217000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21009217000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21009217000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21009217000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21009217000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 20408870 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 20408870 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 20408870 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 20408870 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 20408870 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 20408870 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009954000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 21009954000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 21009954000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 21009954000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 21009954000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 21009954000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 20408869 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 20408869 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 20408869 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 20408869 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 20408869 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 20408869 # number of overall (read+write) accesses
657,662c657,662
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.208436 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14379.208436 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.208436 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14379.208436 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.208436 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14379.208436 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.712857 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14379.712857 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14379.712857 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14379.712857 # average overall miss latency
679,684c679,684
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548134000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 19548134000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548134000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 19548134000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548134000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 19548134000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548871000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 19548871000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548871000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 19548871000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548871000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 19548871000 # number of overall MSHR miss cycles
691,696c691,696
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.208436 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.208436 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.208436 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.208436 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.208436 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.208436 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.712857 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.712857 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency
699c699
< system.cpu.l2cache.tags.tagsinuse 65260.797469 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 65260.797416 # Cycle average of tags in use
704,706c704,706
< system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251550 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395782 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150137 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251440 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395876 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150100 # Average occupied blocks per requestor
754,765c754,765
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837528000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 14837528000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2141943000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2141943000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680651000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680651000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2141943000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 48518179000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 50660122000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2141943000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 48518179000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 50660122000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837606000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 14837606000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2142680000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2142680000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680454000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680454000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2142680000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 48518060000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 50660740000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2142680000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 48518060000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 50660740000 # number of overall miss cycles
800,811c800,811
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.169443 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.169443 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131214.346974 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131214.346974 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.759286 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.759286 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 125028.065846 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 125028.065846 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.838058 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.838058 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131259.495222 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131259.495222 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.035572 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.035572 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 125029.591056 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 125029.591056 # average overall miss latency
844,857c844,857
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13670938000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13670938000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1978703000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1978703000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960659500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960659500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1978703000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631597500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 46610300500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1978703000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631597500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 46610300500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1443571000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1443571000 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13671016000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13671016000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1979440000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1979440000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960462500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960462500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1979440000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631478500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 46610918500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1979440000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631478500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 46610918500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442671000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442671000 # number of ReadReq MSHR uncacheable cycles
860,861c860,861
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3495402500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3495402500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3494502500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494502500 # number of overall MSHR uncacheable cycles
878,891c878,891
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.169443 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.169443 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121214.346974 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121214.346974 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113739.395019 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113739.395019 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208187.337756 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208187.337756 # average ReadReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.838058 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.838058 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121259.495222 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121259.495222 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113738.671305 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113738.671305 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.542544 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.542544 # average ReadReq mshr uncacheable latency
894,895c894,895
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211100.525426 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211100.525426 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211046.171035 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211046.171035 # average overall mshr uncacheable latency
961c961
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
968d967
< system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
970,971d968
< system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
977c974
< system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
984d980
< system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
986,987d981
< system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
994c988
< system.iobus.reqLayer1.occupancy 386000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 784500 # Layer occupancy (ticks)
1008c1002
< system.iobus.reqLayer26.occupancy 224500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer26.occupancy 98500 # Layer occupancy (ticks)
1010c1004
< system.iobus.reqLayer27.occupancy 98500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 215092991 # Layer occupancy (ticks)
1012,1017d1005
< system.iobus.reqLayer28.occupancy 142500 # Layer occupancy (ticks)
< system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer29.occupancy 215092991 # Layer occupancy (ticks)
< system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer30.occupancy 31500 # Layer occupancy (ticks)
< system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1164c1152
< system.membus.respLayer1.occupancy 2160247074 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2160244574 # Layer occupancy (ticks)