3,5c3,5
< sim_seconds 1.887168 # Number of seconds simulated
< sim_ticks 1887168480000 # Number of ticks simulated
< final_tick 1887168480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.906037 # Number of seconds simulated
> sim_ticks 1906037467000 # Number of ticks simulated
> final_tick 1906037467000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 181674 # Simulator instruction rate (inst/s)
< host_op_rate 181674 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 6108559174 # Simulator tick rate (ticks/s)
< host_mem_usage 367844 # Number of bytes of host memory used
< host_seconds 308.94 # Real time elapsed on the host
< sim_insts 56125948 # Number of instructions simulated
< sim_ops 56125948 # Number of ops (including micro ops) simulated
---
> host_inst_rate 252781 # Simulator instruction rate (inst/s)
> host_op_rate 252781 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 8583432112 # Simulator tick rate (ticks/s)
> host_mem_usage 376892 # Number of bytes of host memory used
> host_seconds 222.06 # Real time elapsed on the host
> sim_insts 56132533 # Number of instructions simulated
> sim_ops 56132533 # Number of ops (including micro ops) simulated
16,17c16,17
< system.physmem.bytes_read::cpu.inst 1049920 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24850048 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1050496 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory
19,25c19,25
< system.physmem.bytes_read::total 25900928 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1049920 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1049920 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7553472 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7553472 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 16405 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388282 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25909440 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1050496 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1050496 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7561088 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7561088 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 16414 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory
27,52c27,52
< system.physmem.num_reads::total 404702 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 118023 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 118023 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 556347 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 13167901 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 13724757 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 556347 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 556347 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4002542 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4002542 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4002542 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 556347 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 13167901 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 17727299 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 404702 # Number of read requests accepted
< system.physmem.writeReqs 118023 # Number of write requests accepted
< system.physmem.readBursts 404702 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 118023 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25893824 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7551936 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25900928 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7553472 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_reads::total 404835 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 118142 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 118142 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 551141 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 13041708 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 13593353 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 551141 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 551141 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3966915 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3966915 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3966915 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 551141 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 13041708 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 17560268 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 404835 # Number of read requests accepted
> system.physmem.writeReqs 118142 # Number of write requests accepted
> system.physmem.readBursts 404835 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 118142 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25902720 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7559680 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25909440 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7561088 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue
54,69c54,69
< system.physmem.neitherReadNorWriteReqs 41707 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 25482 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25721 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25818 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25768 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25084 # Per bank write bursts
< system.physmem.perBankRdBursts::5 25019 # Per bank write bursts
< system.physmem.perBankRdBursts::6 24651 # Per bank write bursts
< system.physmem.perBankRdBursts::7 24525 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25293 # Per bank write bursts
< system.physmem.perBankRdBursts::9 25189 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25397 # Per bank write bursts
< system.physmem.perBankRdBursts::11 24988 # Per bank write bursts
< system.physmem.perBankRdBursts::12 24521 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25565 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25830 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 41709 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 25494 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25705 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25829 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25773 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25090 # Per bank write bursts
> system.physmem.perBankRdBursts::5 25012 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24715 # Per bank write bursts
> system.physmem.perBankRdBursts::7 24579 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25194 # Per bank write bursts
> system.physmem.perBankRdBursts::9 25292 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25390 # Per bank write bursts
> system.physmem.perBankRdBursts::11 24989 # Per bank write bursts
> system.physmem.perBankRdBursts::12 24533 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25560 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25835 # Per bank write bursts
71,85c71,85
< system.physmem.perBankWrBursts::0 7815 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7682 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8062 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7737 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7196 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7012 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6647 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6398 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7404 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6806 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7277 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6969 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7052 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8011 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7982 # Per bank write bursts
---
> system.physmem.perBankWrBursts::0 7824 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7665 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8071 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7733 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7203 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7017 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6707 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6431 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7312 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6902 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7273 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6973 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7066 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8009 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7985 # Per bank write bursts
88,89c88,89
< system.physmem.numWrRetry 29 # Number of times write queue was full causing retry
< system.physmem.totGap 1887159671500 # Total gap between requests
---
> system.physmem.numWrRetry 13 # Number of times write queue was full causing retry
> system.physmem.totGap 1906028705500 # Total gap between requests
96c96
< system.physmem.readPktSize::6 404702 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 404835 # Read request sizes (log2)
103,106c103,106
< system.physmem.writePktSize::6 118023 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 402323 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2193 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 118142 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 402462 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2192 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 64 # What read queue length does an incoming req see
151,217c151,217
< system.physmem.wrQLenPdf::15 1508 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 1846 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6025 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6254 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7072 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7254 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 9744 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8775 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 7502 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8222 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6817 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6604 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7036 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5493 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5524 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 181 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 183 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 169 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 184 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 145 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 143 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 120 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 87 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 94 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 63563 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 526.182842 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 320.768050 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 414.563237 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14483 22.79% 22.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 10991 17.29% 40.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4893 7.70% 47.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3583 5.64% 53.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2419 3.81% 57.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1815 2.86% 60.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1455 2.29% 62.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1407 2.21% 64.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 22517 35.42% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63563 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5279 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 76.639515 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2907.321691 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5276 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1507 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1810 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5625 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5632 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6322 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6596 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6037 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6430 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7912 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 8339 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9439 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8363 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8669 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7496 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6853 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6204 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5785 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5489 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 161 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 164 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 205 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 169 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 110 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 186 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 139 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 90 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 170 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 114 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 115 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 90 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 136 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 62 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 64437 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 519.304127 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 318.318074 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 406.802576 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14872 23.08% 23.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11053 17.15% 40.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5024 7.80% 48.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3269 5.07% 53.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2580 4.00% 57.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1937 3.01% 60.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 4194 6.51% 66.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1317 2.04% 68.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 20191 31.33% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 64437 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5312 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 76.190700 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2898.366893 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5309 99.94% 99.94% # Reads before turning the bus around for writes
221,255c221,264
< system.physmem.rdPerTurnAround::total 5279 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5279 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.352529 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.833418 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 22.552708 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 4665 88.37% 88.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 223 4.22% 92.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 69 1.31% 93.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-47 13 0.25% 94.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-55 7 0.13% 94.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-63 8 0.15% 94.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-71 10 0.19% 94.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 11 0.21% 94.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 9 0.17% 95.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-95 33 0.63% 95.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-103 187 3.54% 99.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 5 0.09% 99.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-119 2 0.04% 99.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-127 2 0.04% 99.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-135 7 0.13% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-159 1 0.02% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-167 3 0.06% 99.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-175 3 0.06% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 6 0.11% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-223 1 0.02% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-231 9 0.17% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5279 # Writes before turning the bus around for reads
< system.physmem.totQLat 2194493000 # Total ticks spent queuing
< system.physmem.totMemAccLat 9780574250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2022955000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 5423.98 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5312 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5312 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.236446 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.912972 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 20.909399 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 4665 87.82% 87.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 19 0.36% 88.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 18 0.34% 88.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 199 3.75% 92.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 5 0.09% 92.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 25 0.47% 92.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 40 0.75% 93.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 5 0.09% 93.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 6 0.11% 93.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 23 0.43% 94.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 6 0.11% 94.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 4 0.08% 94.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 9 0.17% 94.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 1 0.02% 94.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 20 0.38% 94.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 24 0.45% 95.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 32 0.60% 96.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 3 0.06% 96.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 171 3.22% 99.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 4 0.08% 99.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 2 0.04% 99.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 1 0.02% 99.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 3 0.06% 99.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 1 0.02% 99.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 2 0.04% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 4 0.08% 99.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 2 0.04% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 8 0.15% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 3 0.06% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-211 1 0.02% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-227 1 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::228-231 2 0.04% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5312 # Writes before turning the bus around for reads
> system.physmem.totQLat 2653633250 # Total ticks spent queuing
> system.physmem.totMemAccLat 10242320750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2023650000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 6556.55 # Average queueing delay per DRAM burst
257,261c266,270
< system.physmem.avgMemAccLat 24173.98 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.72 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.72 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 25306.55 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.97 # Average system write bandwidth in MiByte/s
267,284c276,293
< system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing
< system.physmem.readRowHits 363582 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95445 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.86 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes
< system.physmem.avgGap 3610234.20 # Average gap between requests
< system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 233596440 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 127458375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1576130400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 379397520 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 60352481790 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1079356093500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1265285353785 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.470116 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1795392967750 # Time in different power states
< system.physmem_0.memoryStateTime::REF 63016460000 # Time in different power states
---
> system.physmem.avgWrQLen 23.01 # Average write queue length when enqueuing
> system.physmem.readRowHits 362859 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95554 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes
> system.physmem.avgGap 3644574.63 # Average gap between requests
> system.physmem.pageHitRate 87.67 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 238049280 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 129888000 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1577136600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 380058480 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 124492945200 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 67941192465 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1084023651750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1278782921775 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.912502 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1803110214250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 63646700000 # Time in different power states
286c295
< system.physmem_0.memoryStateTime::ACT 28752031000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 39278414500 # Time in different power states
288,298c297,307
< system.physmem_1.actEnergy 246939840 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 134739000 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1579679400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 385236000 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 61300664820 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1078524362250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1265431817070 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.547722 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1794008459000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 63016460000 # Time in different power states
---
> system.physmem_1.actEnergy 249094440 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 135914625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1579757400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 385359120 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 124492945200 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 68603580630 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1083442617750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1278889269165 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.968292 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1802146960250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 63646700000 # Time in different power states
300c309
< system.physmem_1.memoryStateTime::ACT 30136553500 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 40241682250 # Time in different power states
302,306c311,315
< system.cpu.branchPred.lookups 14997890 # Number of BP lookups
< system.cpu.branchPred.condPredicted 13009268 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 370594 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9393435 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 5198350 # Number of BTB hits
---
> system.cpu.branchPred.lookups 15005157 # Number of BP lookups
> system.cpu.branchPred.condPredicted 13016352 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 370563 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9544476 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 5200630 # Number of BTB hits
308,310c317,319
< system.cpu.branchPred.BTBHitPct 55.340246 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 807960 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 32049 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 54.488376 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 807259 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 30802 # Number of incorrect RAS predictions.
316,317c325,326
< system.cpu.dtb.read_hits 9241004 # DTB read hits
< system.cpu.dtb.read_misses 17472 # DTB read misses
---
> system.cpu.dtb.read_hits 9242284 # DTB read hits
> system.cpu.dtb.read_misses 17197 # DTB read misses
319,321c328,330
< system.cpu.dtb.read_accesses 766036 # DTB read accesses
< system.cpu.dtb.write_hits 6386411 # DTB write hits
< system.cpu.dtb.write_misses 2301 # DTB write misses
---
> system.cpu.dtb.read_accesses 765766 # DTB read accesses
> system.cpu.dtb.write_hits 6387071 # DTB write hits
> system.cpu.dtb.write_misses 2294 # DTB write misses
323,325c332,334
< system.cpu.dtb.write_accesses 298419 # DTB write accesses
< system.cpu.dtb.data_hits 15627415 # DTB hits
< system.cpu.dtb.data_misses 19773 # DTB misses
---
> system.cpu.dtb.write_accesses 298411 # DTB write accesses
> system.cpu.dtb.data_hits 15629355 # DTB hits
> system.cpu.dtb.data_misses 19491 # DTB misses
327,331c336,340
< system.cpu.dtb.data_accesses 1064455 # DTB accesses
< system.cpu.itb.fetch_hits 4013195 # ITB hits
< system.cpu.itb.fetch_misses 6857 # ITB misses
< system.cpu.itb.fetch_acv 677 # ITB acv
< system.cpu.itb.fetch_accesses 4020052 # ITB accesses
---
> system.cpu.dtb.data_accesses 1064177 # DTB accesses
> system.cpu.itb.fetch_hits 4015320 # ITB hits
> system.cpu.itb.fetch_misses 6841 # ITB misses
> system.cpu.itb.fetch_acv 659 # ITB acv
> system.cpu.itb.fetch_accesses 4022161 # ITB accesses
344c353
< system.cpu.numCycles 182043546 # number of cpu cycles simulated
---
> system.cpu.numCycles 223168437 # number of cpu cycles simulated
347,353c356,362
< system.cpu.committedInsts 56125948 # Number of instructions committed
< system.cpu.committedOps 56125948 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 2502558 # Number of ops (including micro ops) which were discarded before commit
< system.cpu.numFetchSuspends 5565 # Number of times Execute suspended instruction fetching
< system.cpu.quiesceCycles 3594204473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 3.243483 # CPI: cycles per instruction
< system.cpu.ipc 0.308311 # IPC: instructions per cycle
---
> system.cpu.committedInsts 56132533 # Number of instructions committed
> system.cpu.committedOps 56132533 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 2504504 # Number of ops (including micro ops) which were discarded before commit
> system.cpu.numFetchSuspends 5489 # Number of times Execute suspended instruction fetching
> system.cpu.quiesceCycles 3590815720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 3.975741 # CPI: cycles per instruction
> system.cpu.ipc 0.251525 # IPC: instructions per cycle
355,357c364,366
< system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211461 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74782 40.94% 40.94% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 211546 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74811 40.93% 40.93% # number of times we switched to this ipl
359,372c368,381
< system.cpu.kern.ipl_count::22 1902 1.04% 42.05% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 105860 57.95% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182675 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73415 49.32% 49.32% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::22 1902 1.28% 50.68% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73415 49.32% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1834747397000 97.22% 97.22% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 80828500 0.00% 97.23% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 680298500 0.04% 97.26% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 51658959000 2.74% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1887167483000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 105910 57.95% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182756 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73444 49.32% 49.32% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73444 49.32% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 148923 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1837436986000 96.40% 96.40% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 81017000 0.00% 96.41% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 682412000 0.04% 96.44% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 67836062500 3.56% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1906036477500 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981727 # fraction of swpipl calls that actually changed the ipl
375,376c384,385
< system.cpu.kern.ipl_used::31 0.693510 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814906 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.693457 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814873 # fraction of swpipl calls that actually changed the ipl
412c421
< system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed
---
> system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
415,416c424,425
< system.cpu.kern.callpal::swpipl 175514 91.22% 93.43% # number of callpals executed
< system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175591 91.23% 93.43% # number of callpals executed
> system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed
421c430
< system.cpu.kern.callpal::rti 5127 2.66% 99.64% # number of callpals executed
---
> system.cpu.kern.callpal::rti 5129 2.66% 99.64% # number of callpals executed
424,431c433,440
< system.cpu.kern.callpal::total 192398 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5868 # number of protection mode switches
< system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
< system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
< system.cpu.kern.mode_good::kernel 1907
< system.cpu.kern.mode_good::user 1739
< system.cpu.kern.mode_good::idle 168
< system.cpu.kern.mode_switch_good::kernel 0.324983 # fraction of useful protection mode switches
---
> system.cpu.kern.callpal::total 192481 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches
> system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
> system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
> system.cpu.kern.mode_good::kernel 1909
> system.cpu.kern.mode_good::user 1740
> system.cpu.kern.mode_good::idle 169
> system.cpu.kern.mode_switch_good::kernel 0.325047 # fraction of useful protection mode switches
433,449c442,458
< system.cpu.kern.mode_switch_good::idle 0.080114 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.393034 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 36501486500 1.93% 1.93% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 4115911000 0.22% 2.15% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1846550075500 97.85% 100.00% # number of ticks spent at the given mode
< system.cpu.kern.swap_context 4173 # number of times the context was actually changed
< system.cpu.tickCycles 86269078 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 95774468 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 1395484 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.981722 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 13771544 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1395996 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 9.865031 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 90850500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.981722 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy
---
> system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.393243 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 38636753000 2.03% 2.03% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 4528404000 0.24% 2.26% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1862871310500 97.74% 100.00% # number of ticks spent at the given mode
> system.cpu.kern.swap_context 4175 # number of times the context was actually changed
> system.cpu.tickCycles 86394668 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 136773769 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 1395457 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.977331 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 13772866 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1395969 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 9.866169 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 121717500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.977331 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999956 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999956 # Average percentage of cache occupancy
451,453c460,462
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
455,520c464,529
< system.cpu.dcache.tags.tag_accesses 63656757 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63656757 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 7813939 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7813939 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5575873 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5575873 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 182717 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 182717 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 198981 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 198981 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 13389812 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13389812 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13389812 # number of overall hits
< system.cpu.dcache.overall_hits::total 13389812 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1201834 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1201834 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 574561 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 574561 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 17285 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17285 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1776395 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1776395 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1776395 # number of overall misses
< system.cpu.dcache.overall_misses::total 1776395 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 32870602000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 32870602000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 22298477500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 22298477500 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232185000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 232185000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 55169079500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 55169079500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 55169079500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 55169079500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 9015773 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9015773 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6150434 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6150434 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200002 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200002 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 198981 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 198981 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15166207 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15166207 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15166207 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15166207 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133303 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.133303 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093418 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.093418 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086424 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086424 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.117128 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.117128 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.117128 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.117128 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27350.367854 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 27350.367854 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38809.591149 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38809.591149 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13432.745155 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13432.745155 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 31056.763558 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 31056.763558 # average overall miss latency
---
> system.cpu.dcache.tags.tag_accesses 63663599 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63663599 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 7815159 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7815159 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5575814 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5575814 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 182834 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 182834 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 199026 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 199026 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 13390973 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13390973 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13390973 # number of overall hits
> system.cpu.dcache.overall_hits::total 13390973 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1201770 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1201770 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 575091 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 575091 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 17213 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17213 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1776861 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1776861 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1776861 # number of overall misses
> system.cpu.dcache.overall_misses::total 1776861 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 46961675000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 46961675000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 33993891500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 33993891500 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 235176000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 235176000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 80955566500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 80955566500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 80955566500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 80955566500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 9016929 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9016929 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6150905 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6150905 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200047 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200047 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 199026 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 199026 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15167834 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15167834 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15167834 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15167834 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133279 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.133279 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093497 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.093497 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086045 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086045 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.117147 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.117147 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.117147 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.117147 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39077.090458 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 39077.090458 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59110.456432 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 59110.456432 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13662.696799 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13662.696799 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 45561.001395 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 45561.001395 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 45561.001395 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 45561.001395 # average overall miss latency
529,534c538,543
< system.cpu.dcache.writebacks::writebacks 838310 # number of writebacks
< system.cpu.dcache.writebacks::total 838310 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127379 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 127379 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270264 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 270264 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 838295 # number of writebacks
> system.cpu.dcache.writebacks::total 838295 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127341 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 127341 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270722 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 270722 # number of WriteReq MSHR hits
537,550c546,559
< system.cpu.dcache.demand_mshr_hits::cpu.data 397643 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 397643 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 397643 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 397643 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074455 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1074455 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304297 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304297 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17282 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17282 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1378752 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1378752 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1378752 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1378752 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 398063 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 398063 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 398063 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 398063 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074429 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304369 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304369 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17210 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17210 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1378798 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1378798 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1378798 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1378798 # number of overall MSHR misses
553,598c562,607
< system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9620 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::total 9620 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16550 # number of overall MSHR uncacheable misses
< system.cpu.dcache.overall_mshr_uncacheable_misses::total 16550 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29867395000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 29867395000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11355989000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11355989000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214737500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214737500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41223384000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 41223384000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41223384000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 41223384000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450621500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450621500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2041589000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2041589000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3492210500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3492210500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119175 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119175 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049476 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049476 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086409 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086409 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090909 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.090909 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090909 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.090909 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27797.716051 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27797.716051 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37318.767520 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37318.767520 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12425.500521 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12425.500521 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29899.056538 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 29899.056538 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29899.056538 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 29899.056538 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209324.891775 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209324.891775 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212223.388773 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212223.388773 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211009.697885 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211009.697885 # average overall mshr uncacheable latency
---
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9622 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 9622 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16552 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 16552 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43805969000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 43805969000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17294633000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 17294633000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 217700500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217700500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61100602000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 61100602000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61100602000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 61100602000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450655500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450655500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2042490500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2042490500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3493146000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3493146000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119157 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119157 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049484 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049484 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086030 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086030 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090903 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.090903 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090903 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.090903 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40771.394853 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40771.394853 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56821.269577 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56821.269577 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12649.651365 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12649.651365 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44314.397033 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 44314.397033 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44314.397033 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 44314.397033 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209329.797980 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209329.797980 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212272.968198 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212272.968198 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211040.720155 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211040.720155 # average overall mshr uncacheable latency
600,608c609,617
< system.cpu.icache.tags.replacements 1459068 # number of replacements
< system.cpu.icache.tags.tagsinuse 509.460685 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 18942908 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1459579 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 12.978337 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 33609235500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 509.460685 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.995040 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.995040 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 1459812 # number of replacements
> system.cpu.icache.tags.tagsinuse 508.108213 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 18945545 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1460323 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 12.973531 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 50089035500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 508.108213 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.992399 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.992399 # Average percentage of cache occupancy
610,612c619,621
< system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id
614,651c623,660
< system.cpu.icache.tags.tag_accesses 21862421 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 21862421 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 18942911 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 18942911 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 18942911 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 18942911 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 18942911 # number of overall hits
< system.cpu.icache.overall_hits::total 18942911 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1459755 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1459755 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1459755 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1459755 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1459755 # number of overall misses
< system.cpu.icache.overall_misses::total 1459755 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 20136698000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 20136698000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 20136698000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 20136698000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 20136698000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 20136698000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 20402666 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 20402666 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 20402666 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 20402666 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 20402666 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 20402666 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071547 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.071547 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.071547 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.071547 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.071547 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.071547 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13794.573747 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13794.573747 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13794.573747 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13794.573747 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13794.573747 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13794.573747 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 21866544 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 21866544 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 18945548 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 18945548 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 18945548 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 18945548 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 18945548 # number of overall hits
> system.cpu.icache.overall_hits::total 18945548 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1460498 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1460498 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1460498 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1460498 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1460498 # number of overall misses
> system.cpu.icache.overall_misses::total 1460498 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 20983654500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 20983654500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 20983654500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 20983654500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 20983654500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 20983654500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 20406046 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 20406046 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 20406046 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 20406046 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 20406046 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 20406046 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071572 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.071572 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.071572 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.071572 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.071572 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.071572 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14367.465412 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14367.465412 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14367.465412 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14367.465412 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14367.465412 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14367.465412 # average overall miss latency
660,683c669,692
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459755 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1459755 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1459755 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1459755 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1459755 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1459755 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18676943000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 18676943000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18676943000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 18676943000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18676943000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 18676943000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071547 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071547 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071547 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.071547 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071547 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.071547 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12794.573747 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12794.573747 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12794.573747 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12794.573747 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12794.573747 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12794.573747 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1460498 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1460498 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1460498 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1460498 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1460498 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1460498 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19523156500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 19523156500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19523156500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 19523156500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19523156500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 19523156500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071572 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071572 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071572 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.071572 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071572 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.071572 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13367.465412 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13367.465412 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13367.465412 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13367.465412 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13367.465412 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13367.465412 # average overall mshr miss latency
685,702c694,711
< system.cpu.l2cache.tags.replacements 339197 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65316.861882 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4997134 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 404357 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 12.358223 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 6286116000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 54372.711085 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 5866.673832 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5077.476965 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.829662 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.089518 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.077476 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996656 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65160 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5171 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2816 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.replacements 339330 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65261.345003 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4998363 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 404492 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 12.357137 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 9675364000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 53948.276768 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 5807.945434 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5505.122802 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.823185 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088622 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.084002 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.995809 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 863 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5644 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2903 # Occupied blocks per task id
704,708c713,717
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994263 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 46375417 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 46375417 # Number of data accesses
< system.cpu.l2cache.Writeback_hits::writebacks 838310 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 838310 # number of Writeback hits
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 46387191 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 46387191 # Number of data accesses
> system.cpu.l2cache.Writeback_hits::writebacks 838295 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 838295 # number of Writeback hits
711,722c720,731
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187763 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187763 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1443287 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1443287 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819540 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 819540 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 1443287 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1007303 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2450590 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 1443287 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1007303 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2450590 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187729 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187729 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1444018 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1444018 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819422 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 819422 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 1444018 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1007151 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2451169 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 1444018 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1007151 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2451169 # number of overall hits
725,752c734,761
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116544 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116544 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16406 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 16406 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272166 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 272166 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 16406 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 388710 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 405116 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 16406 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 388710 # number of overall misses
< system.cpu.l2cache.overall_misses::total 405116 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 253000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 253000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8923529500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8923529500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1314713000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 1314713000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19729862500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 19729862500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1314713000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 28653392000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 29968105000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1314713000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 28653392000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 29968105000 # number of overall miss cycles
< system.cpu.l2cache.Writeback_accesses::writebacks 838310 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 838310 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116650 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116650 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16415 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 16415 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272186 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 272186 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 16415 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 388836 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 405251 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 16415 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 388836 # number of overall misses
> system.cpu.l2cache.overall_misses::total 405251 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 404000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 404000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14861542500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 14861542500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2151733500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2151733500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33671733000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 33671733000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2151733500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 48533275500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 50685009000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2151733500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 48533275500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 50685009000 # number of overall miss cycles
> system.cpu.l2cache.Writeback_accesses::writebacks 838295 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 838295 # number of Writeback accesses(hits+misses)
755,766c764,775
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 304307 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304307 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1459693 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1459693 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091706 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1091706 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1459693 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1396013 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2855706 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1459693 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1396013 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2855706 # number of overall (read+write) accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 304379 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304379 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1460433 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1460433 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091608 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1091608 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1460433 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1395987 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2856420 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1460433 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1395987 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2856420 # number of overall (read+write) accesses
769,794c778,803
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382982 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.382982 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011239 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011239 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249303 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249303 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011239 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.278443 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.141862 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011239 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.278443 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.141862 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14882.352941 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14882.352941 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76567.901393 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76567.901393 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80136.108741 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80136.108741 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72492.017739 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72492.017739 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80136.108741 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73714.059324 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73974.133335 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80136.108741 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73714.059324 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73974.133335 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383239 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383239 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011240 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011240 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249344 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249344 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011240 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.278538 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.141874 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011240 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.278538 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.141874 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23764.705882 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23764.705882 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127402.850407 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127402.850407 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131083.368870 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131083.368870 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123708.541218 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123708.541218 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131083.368870 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124816.826374 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 125070.657444 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131083.368870 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124816.826374 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 125070.657444 # average overall miss latency
803,804c812,813
< system.cpu.l2cache.writebacks::writebacks 76511 # number of writebacks
< system.cpu.l2cache.writebacks::total 76511 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 76630 # number of writebacks
> system.cpu.l2cache.writebacks::total 76630 # number of writebacks
809,820c818,829
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116544 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116544 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16406 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16406 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272166 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272166 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 16406 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 388710 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 405116 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 16406 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 388710 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 405116 # number of overall MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116650 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116650 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16415 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16415 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272186 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272186 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 16415 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 388836 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 405251 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 16415 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 388836 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 405251 # number of overall MSHR misses
823,846c832,855
< system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9620 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9620 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16550 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16550 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 453499 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 453499 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7758089500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7758089500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1150653000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1150653000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17010167000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17010167000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1150653000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24768256500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 25918909500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1150653000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24768256500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 25918909500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363977000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363977000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1930958000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1930958000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3294935000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3294935000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9622 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9622 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16552 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16552 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1214500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1214500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13695042500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13695042500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1987583500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1987583500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30951837500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30951837500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1987583500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44646880000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 46634463500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1987583500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44646880000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 46634463500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364010000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364010000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1931836500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1931836500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3295846500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3295846500 # number of overall MSHR uncacheable cycles
851,882c860,891
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382982 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382982 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011239 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249303 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249303 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.141862 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.141862 # mshr miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26676.411765 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26676.411765 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66567.901393 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66567.901393 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70136.108741 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70136.108741 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62499.235761 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62499.235761 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196822.077922 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196822.077922 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200723.284823 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200723.284823 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199089.728097 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199089.728097 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383239 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383239 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011240 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249344 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249344 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278538 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.141874 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278538 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.141874 # mshr miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71441.176471 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71441.176471 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117402.850407 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117402.850407 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121083.368870 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121083.368870 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113715.758709 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113715.758709 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121083.368870 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114821.878633 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115075.505057 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121083.368870 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114821.878633 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115075.505057 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196826.839827 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196826.839827 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200772.864269 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200772.864269 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199120.740696 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199120.740696 # average overall mshr uncacheable latency
883a893,898
> system.cpu.toL2Bus.snoop_filter.tot_requests 5711775 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2855459 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1981 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1240 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
885,889c900,904
< system.cpu.toL2Bus.trans_dist::ReadResp 2558531 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 9620 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 9620 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 956362 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 2277135 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2559171 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 9622 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 9622 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 956450 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 2277896 # Transaction distribution
892,895c907,910
< system.cpu.toL2Bus.trans_dist::ReadExReq 304307 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 304307 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459755 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091879 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 304379 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 304379 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1460498 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091781 # Transaction distribution
898,907c913,922
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377903 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219455 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8597358 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93420352 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143049956 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 236470308 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 422854 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 6149527 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.068727 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.252989 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4380147 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219373 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8599520 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93467712 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143047028 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 236514740 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 422969 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 6151080 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.000871 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.029504 # Request fanout histogram
909,911c924,926
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 5726891 93.13% 93.13% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 422636 6.87% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 6145721 99.91% 99.91% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 5359 0.09% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
913,916c928,931
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 6149527 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3706565999 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 6151080 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3707269500 # Layer occupancy (ticks)
918c933
< system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 284383 # Layer occupancy (ticks)
920c935
< system.cpu.toL2Bus.respLayer0.occupancy 2189850563 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2190955582 # Layer occupancy (ticks)
922c937
< system.cpu.toL2Bus.respLayer1.occupancy 2105755497 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2105716998 # Layer occupancy (ticks)
938,940c953,955
< system.iobus.trans_dist::WriteReq 51172 # Transaction distribution
< system.iobus.trans_dist::WriteResp 51172 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5096 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::WriteReq 51174 # Transaction distribution
> system.iobus.trans_dist::WriteResp 51174 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5100 # Packet count per connected master and slave (bytes)
952c967
< system.iobus.pkt_count_system.bridge.master::total 33100 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 33104 # Packet count per connected master and slave (bytes)
955,956c970,971
< system.iobus.pkt_count::total 116550 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20384 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 116554 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20400 # Cumulative packet size per connected master and slave (bytes)
968c983
< system.iobus.pkt_size_system.bridge.master::total 44324 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 44340 # Cumulative packet size per connected master and slave (bytes)
971,972c986,987
< system.iobus.pkt_size::total 2705932 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 4707000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2705948 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 4711000 # Layer occupancy (ticks)
994c1009
< system.iobus.reqLayer29.occupancy 216043265 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 215087245 # Layer occupancy (ticks)
998c1013
< system.iobus.respLayer0.occupancy 23480000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 23482000 # Layer occupancy (ticks)
1003c1018
< system.iocache.tags.tagsinuse 1.302220 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.290787 # Cycle average of tags in use
1007,1010c1022,1025
< system.iocache.tags.warmup_cycle 1729987199000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.302220 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.081389 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.081389 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1748608829000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.290787 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.080674 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.080674 # Average percentage of cache occupancy
1024,1031c1039,1046
< system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908791382 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4908791382 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21943883 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21943883 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427163362 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 5427163362 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 21943883 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 21943883 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 21943883 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 21943883 # number of overall miss cycles
1048,1056c1063,1071
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118136.103725 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118136.103725 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126843.254335 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 126843.254335 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130611.363159 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 130611.363159 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 126843.254335 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126843.254335 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126843.254335 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126843.254335 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1058c1073
< system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1060c1075
< system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1074,1081c1089,1096
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831191382 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2831191382 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13293883 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 13293883 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3349563362 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 3349563362 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 13293883 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 13293883 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 13293883 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 13293883 # number of overall MSHR miss cycles
1090,1097c1105,1112
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68136.103725 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68136.103725 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 76843.254335 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80611.363159 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80611.363159 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76843.254335 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76843.254335 # average overall mshr miss latency
1100,1109c1115,1124
< system.membus.trans_dist::ReadResp 295659 # Transaction distribution
< system.membus.trans_dist::WriteReq 9620 # Transaction distribution
< system.membus.trans_dist::WriteResp 9620 # Transaction distribution
< system.membus.trans_dist::Writeback 118023 # Transaction distribution
< system.membus.trans_dist::CleanEvict 262178 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 157 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 157 # Transaction distribution
< system.membus.trans_dist::ReadExReq 116404 # Transaction distribution
< system.membus.trans_dist::ReadExResp 116404 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 295688 # Transaction distribution
> system.membus.trans_dist::WriteReq 9622 # Transaction distribution
> system.membus.trans_dist::WriteResp 9622 # Transaction distribution
> system.membus.trans_dist::Writeback 118142 # Transaction distribution
> system.membus.trans_dist::CleanEvict 262192 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 159 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 159 # Transaction distribution
> system.membus.trans_dist::ReadExReq 116508 # Transaction distribution
> system.membus.trans_dist::ReadExResp 116508 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 288774 # Transaction distribution
1113,1114c1128,1129
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33100 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148635 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33104 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1149038 # Packet count per connected master and slave (bytes)
1116c1131
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181767 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1182174 # Packet count per connected master and slave (bytes)
1119,1122c1134,1137
< system.membus.pkt_count::total 1306584 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44324 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796672 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30840996 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1306991 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44340 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30812800 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30857140 # Cumulative packet size per connected master and slave (bytes)
1125c1140
< system.membus.pkt_size::total 33498724 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 33514868 # Cumulative packet size per connected master and slave (bytes)
1127c1142
< system.membus.snoop_fanout::samples 843798 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 844052 # Request fanout histogram
1132c1147
< system.membus.snoop_fanout::1 843798 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 844052 100.00% 100.00% # Request fanout histogram
1137,1138c1152,1153
< system.membus.snoop_fanout::total 843798 # Request fanout histogram
< system.membus.reqLayer0.occupancy 29290000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 844052 # Request fanout histogram
> system.membus.reqLayer0.occupancy 29776500 # Layer occupancy (ticks)
1140c1155
< system.membus.reqLayer1.occupancy 1318757186 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1319401645 # Layer occupancy (ticks)
1144c1159
< system.membus.respLayer1.occupancy 2160035845 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2160603841 # Layer occupancy (ticks)
1146c1161
< system.membus.respLayer2.occupancy 72019946 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 69882415 # Layer occupancy (ticks)