3,5c3,5
< sim_seconds 1.886196 # Number of seconds simulated
< sim_ticks 1886195993000 # Number of ticks simulated
< final_tick 1886195993000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.887168 # Number of seconds simulated
> sim_ticks 1887168480000 # Number of ticks simulated
> final_tick 1887168480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 256659 # Simulator instruction rate (inst/s)
< host_op_rate 256659 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 8626071053 # Simulator tick rate (ticks/s)
< host_mem_usage 374008 # Number of bytes of host memory used
< host_seconds 218.66 # Real time elapsed on the host
< sim_insts 56121694 # Number of instructions simulated
< sim_ops 56121694 # Number of ops (including micro ops) simulated
---
> host_inst_rate 181674 # Simulator instruction rate (inst/s)
> host_op_rate 181674 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 6108559174 # Simulator tick rate (ticks/s)
> host_mem_usage 367844 # Number of bytes of host memory used
> host_seconds 308.94 # Real time elapsed on the host
> sim_insts 56125948 # Number of instructions simulated
> sim_ops 56125948 # Number of ops (including micro ops) simulated
16,17c16,17
< system.physmem.bytes_read::cpu.inst 1049728 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24850240 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1049920 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24850048 # Number of bytes read from this memory
20,25c20,25
< system.physmem.bytes_inst_read::cpu.inst 1049728 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1049728 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7553600 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7553600 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 16402 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388285 # Number of read requests responded to by this memory
---
> system.physmem.bytes_inst_read::cpu.inst 1049920 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1049920 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7553472 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7553472 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 16405 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388282 # Number of read requests responded to by this memory
28,31c28,31
< system.physmem.num_writes::writebacks 118025 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 118025 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 556532 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 13174792 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::writebacks 118023 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 118023 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 556347 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 13167901 # Total read bandwidth from this memory (bytes/s)
33,40c33,40
< system.physmem.bw_read::total 13731833 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 556532 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 556532 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4004674 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4004674 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4004674 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 556532 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 13174792 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 13724757 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 556347 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 556347 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4002542 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4002542 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4002542 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 556347 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 13167901 # Total bandwidth to/from this memory (bytes/s)
42c42
< system.physmem.bw_total::total 17736507 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::total 17727299 # Total bandwidth to/from this memory (bytes/s)
44c44
< system.physmem.writeReqs 118025 # Number of write requests accepted
---
> system.physmem.writeReqs 118023 # Number of write requests accepted
46,49c46,49
< system.physmem.writeBursts 118025 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25894272 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7551808 # Total number of bytes written to DRAM
---
> system.physmem.writeBursts 118023 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25893824 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7551936 # Total number of bytes written to DRAM
51,52c51,52
< system.physmem.bytesWrittenSys 7553600 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bytesWrittenSys 7553472 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
54,62c54,62
< system.physmem.neitherReadNorWriteReqs 41706 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 25487 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25728 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25822 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25769 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25085 # Per bank write bursts
< system.physmem.perBankRdBursts::5 25016 # Per bank write bursts
< system.physmem.perBankRdBursts::6 24650 # Per bank write bursts
< system.physmem.perBankRdBursts::7 24524 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 41707 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 25482 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25721 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25818 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25768 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25084 # Per bank write bursts
> system.physmem.perBankRdBursts::5 25019 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24651 # Per bank write bursts
> system.physmem.perBankRdBursts::7 24525 # Per bank write bursts
64,73c64,73
< system.physmem.perBankRdBursts::9 25190 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25398 # Per bank write bursts
< system.physmem.perBankRdBursts::11 24986 # Per bank write bursts
< system.physmem.perBankRdBursts::12 24522 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25563 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25828 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25737 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7820 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7688 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8067 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 25189 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25397 # Per bank write bursts
> system.physmem.perBankRdBursts::11 24988 # Per bank write bursts
> system.physmem.perBankRdBursts::12 24521 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25565 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25830 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25740 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7815 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7682 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8062 # Per bank write bursts
76,82c76,82
< system.physmem.perBankWrBursts::5 7011 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6646 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6392 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7401 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6804 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7278 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6972 # Per bank write bursts
---
> system.physmem.perBankWrBursts::5 7012 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6647 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6398 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7404 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6806 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7277 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6969 # Per bank write bursts
84,86c84,86
< system.physmem.perBankWrBursts::13 8008 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7983 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7942 # Per bank write bursts
---
> system.physmem.perBankWrBursts::13 8011 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7982 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7949 # Per bank write bursts
88,89c88,89
< system.physmem.numWrRetry 17 # Number of times write queue was full causing retry
< system.physmem.totGap 1886187226500 # Total gap between requests
---
> system.physmem.numWrRetry 29 # Number of times write queue was full causing retry
> system.physmem.totGap 1887159671500 # Total gap between requests
103,104c103,104
< system.physmem.writePktSize::6 118025 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 402327 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 118023 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 402323 # What read queue length does an incoming req see
106c106
< system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see
151,217c151,217
< system.physmem.wrQLenPdf::15 1481 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 1905 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6090 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6347 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6056 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6388 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7084 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7338 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 9716 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8808 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 7466 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8358 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6772 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6976 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5877 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5494 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 111 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 117 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 91 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 177 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 111 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 96 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 193 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 112 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 82 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 56 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 63594 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 525.931377 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 320.890659 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 414.200803 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14460 22.74% 22.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 10997 17.29% 40.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4933 7.76% 47.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3625 5.70% 53.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2479 3.90% 57.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1827 2.87% 60.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1418 2.23% 62.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1367 2.15% 64.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 22488 35.36% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63594 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5295 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 76.408121 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2902.928186 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5292 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1508 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1846 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6025 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5962 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6254 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7072 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7254 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 9744 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 8775 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 7502 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8222 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6817 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6604 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7036 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5493 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5524 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 194 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 125 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 169 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 139 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 131 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 158 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 87 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 94 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 63563 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 526.182842 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 320.768050 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 414.563237 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14483 22.79% 22.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 10991 17.29% 40.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4893 7.70% 47.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3583 5.64% 53.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2419 3.81% 57.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1815 2.86% 60.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1455 2.29% 62.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1407 2.21% 64.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 22517 35.42% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63563 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5279 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 76.639515 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2907.321691 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5276 99.94% 99.94% # Reads before turning the bus around for writes
221,256c221,255
< system.physmem.rdPerTurnAround::total 5295 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5295 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.284608 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.797942 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 22.673735 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 4676 88.31% 88.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 227 4.29% 92.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 77 1.45% 94.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-47 16 0.30% 94.35% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-55 14 0.26% 94.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-63 6 0.11% 94.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-71 7 0.13% 94.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 9 0.17% 95.03% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 7 0.13% 95.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-95 34 0.64% 95.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-103 171 3.23% 99.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 10 0.19% 99.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-127 1 0.02% 99.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-135 5 0.09% 99.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-143 3 0.06% 99.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-159 1 0.02% 99.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-175 2 0.04% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 4 0.08% 99.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-191 4 0.08% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-199 8 0.15% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-223 2 0.04% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5295 # Writes before turning the bus around for reads
< system.physmem.totQLat 2213284250 # Total ticks spent queuing
< system.physmem.totMemAccLat 9799496750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2022990000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 5470.33 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5279 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5279 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.352529 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.833418 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 22.552708 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-23 4665 88.37% 88.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-31 223 4.22% 92.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-39 69 1.31% 93.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-47 13 0.25% 94.15% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-55 7 0.13% 94.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-63 8 0.15% 94.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-71 10 0.19% 94.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-79 11 0.21% 94.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-87 9 0.17% 95.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-95 33 0.63% 95.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-103 187 3.54% 99.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-111 5 0.09% 99.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-119 2 0.04% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-127 2 0.04% 99.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-135 7 0.13% 99.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-159 1 0.02% 99.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-167 3 0.06% 99.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-175 3 0.06% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-183 6 0.11% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::216-223 1 0.02% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-231 9 0.17% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5279 # Writes before turning the bus around for reads
> system.physmem.totQLat 2194493000 # Total ticks spent queuing
> system.physmem.totMemAccLat 9780574250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2022955000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 5423.98 # Average queueing delay per DRAM burst
258,259c257,258
< system.physmem.avgMemAccLat 24220.33 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24173.98 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.72 # Average DRAM read bandwidth in MiByte/s
261c260
< system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 13.72 # Average system read bandwidth in MiByte/s
268,273c267,272
< system.physmem.avgWrQLen 24.19 # Average write queue length when enqueuing
< system.physmem.readRowHits 363516 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95485 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.85 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes
< system.physmem.avgGap 3608360.06 # Average gap between requests
---
> system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing
> system.physmem.readRowHits 363582 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95445 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.86 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes
> system.physmem.avgGap 3610234.20 # Average gap between requests
275,285c274,284
< system.physmem_0.actEnergy 233845920 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 127594500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1576231800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 379449360 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 60326866845 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1078799265750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1264640388495 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.471373 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1794467110750 # Time in different power states
< system.physmem_0.memoryStateTime::REF 62984220000 # Time in different power states
---
> system.physmem_0.actEnergy 233596440 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 127458375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1576130400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 379397520 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 60352481790 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1079356093500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1265285353785 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.470116 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1795392967750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 63016460000 # Time in different power states
287c286
< system.physmem_0.memoryStateTime::ACT 28744633000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 28752031000 # Time in different power states
289,299c288,298
< system.physmem_1.actEnergy 246924720 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 134730750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1579632600 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 385171200 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 61494025635 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1077775442250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1264813061475 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.562919 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1792762379750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 62984220000 # Time in different power states
---
> system.physmem_1.actEnergy 246939840 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 134739000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1579679400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 385236000 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 61300664820 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1078524362250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1265431817070 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.547722 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1794008459000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 63016460000 # Time in different power states
301c300
< system.physmem_1.memoryStateTime::ACT 30449364000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 30136553500 # Time in different power states
303,307c302,306
< system.cpu.branchPred.lookups 15004879 # Number of BP lookups
< system.cpu.branchPred.condPredicted 13013312 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 375549 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 10036322 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 5207234 # Number of BTB hits
---
> system.cpu.branchPred.lookups 14997890 # Number of BP lookups
> system.cpu.branchPred.condPredicted 13009268 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 370594 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9393435 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 5198350 # Number of BTB hits
309,311c308,310
< system.cpu.branchPred.BTBHitPct 51.883887 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 808293 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 31321 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 55.340246 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 807960 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 32049 # Number of incorrect RAS predictions.
317,318c316,317
< system.cpu.dtb.read_hits 9242647 # DTB read hits
< system.cpu.dtb.read_misses 17811 # DTB read misses
---
> system.cpu.dtb.read_hits 9241004 # DTB read hits
> system.cpu.dtb.read_misses 17472 # DTB read misses
320,322c319,321
< system.cpu.dtb.read_accesses 766734 # DTB read accesses
< system.cpu.dtb.write_hits 6385782 # DTB write hits
< system.cpu.dtb.write_misses 2309 # DTB write misses
---
> system.cpu.dtb.read_accesses 766036 # DTB read accesses
> system.cpu.dtb.write_hits 6386411 # DTB write hits
> system.cpu.dtb.write_misses 2301 # DTB write misses
324,326c323,325
< system.cpu.dtb.write_accesses 298407 # DTB write accesses
< system.cpu.dtb.data_hits 15628429 # DTB hits
< system.cpu.dtb.data_misses 20120 # DTB misses
---
> system.cpu.dtb.write_accesses 298419 # DTB write accesses
> system.cpu.dtb.data_hits 15627415 # DTB hits
> system.cpu.dtb.data_misses 19773 # DTB misses
328,332c327,331
< system.cpu.dtb.data_accesses 1065141 # DTB accesses
< system.cpu.itb.fetch_hits 4016387 # ITB hits
< system.cpu.itb.fetch_misses 6834 # ITB misses
< system.cpu.itb.fetch_acv 689 # ITB acv
< system.cpu.itb.fetch_accesses 4023221 # ITB accesses
---
> system.cpu.dtb.data_accesses 1064455 # DTB accesses
> system.cpu.itb.fetch_hits 4013195 # ITB hits
> system.cpu.itb.fetch_misses 6857 # ITB misses
> system.cpu.itb.fetch_acv 677 # ITB acv
> system.cpu.itb.fetch_accesses 4020052 # ITB accesses
345c344
< system.cpu.numCycles 180216793 # number of cpu cycles simulated
---
> system.cpu.numCycles 182043546 # number of cpu cycles simulated
348,354c347,353
< system.cpu.committedInsts 56121694 # Number of instructions committed
< system.cpu.committedOps 56121694 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 2519198 # Number of ops (including micro ops) which were discarded before commit
< system.cpu.numFetchSuspends 5577 # Number of times Execute suspended instruction fetching
< system.cpu.quiesceCycles 3592175193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 3.211179 # CPI: cycles per instruction
< system.cpu.ipc 0.311412 # IPC: instructions per cycle
---
> system.cpu.committedInsts 56125948 # Number of instructions committed
> system.cpu.committedOps 56125948 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 2502558 # Number of ops (including micro ops) which were discarded before commit
> system.cpu.numFetchSuspends 5565 # Number of times Execute suspended instruction fetching
> system.cpu.quiesceCycles 3594204473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 3.243483 # CPI: cycles per instruction
> system.cpu.ipc 0.308311 # IPC: instructions per cycle
356,373c355,372
< system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211471 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74788 40.94% 40.94% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73421 49.32% 49.32% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73422 49.32% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 148877 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1833775262000 97.22% 97.22% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 81341000 0.00% 97.23% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 679703500 0.04% 97.26% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 51658703500 2.74% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1886195010000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 211461 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74782 40.94% 40.94% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::22 1902 1.04% 42.05% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 105860 57.95% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182675 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73415 49.32% 49.32% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::22 1902 1.28% 50.68% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73415 49.32% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1834747397000 97.22% 97.22% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 80828500 0.00% 97.23% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 680298500 0.04% 97.26% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 51658959000 2.74% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1887167483000 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl
376,377c375,376
< system.cpu.kern.ipl_used::31 0.693550 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814934 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.693510 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814906 # fraction of swpipl calls that actually changed the ipl
416,417c415,416
< system.cpu.kern.callpal::swpipl 175525 91.23% 93.43% # number of callpals executed
< system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175514 91.22% 93.43% # number of callpals executed
> system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed
425c424
< system.cpu.kern.callpal::total 192408 # number of callpals executed
---
> system.cpu.kern.callpal::total 192398 # number of callpals executed
436,438c435,437
< system.cpu.kern.mode_ticks::kernel 36513483500 1.94% 1.94% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 4123557000 0.22% 2.15% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1845557959500 97.85% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_ticks::kernel 36501486500 1.93% 1.93% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 4115911000 0.22% 2.15% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1846550075500 97.85% 100.00% # number of ticks spent at the given mode
440,446c439,445
< system.cpu.tickCycles 84408299 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 95808494 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 1395428 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.981685 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 13773051 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1395940 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 9.866506 # Average number of references to valid blocks.
---
> system.cpu.tickCycles 86269078 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 95774468 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 1395484 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.981722 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 13771544 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1395996 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 9.865031 # Average number of references to valid blocks.
448c447
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.981685 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.981722 # Average occupied blocks per requestor
453,454c452,453
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
456,521c455,520
< system.cpu.dcache.tags.tag_accesses 63660654 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63660654 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 7815445 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7815445 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5575784 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5575784 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 182800 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 182800 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 198989 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 198989 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 13391229 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13391229 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13391229 # number of overall hits
< system.cpu.dcache.overall_hits::total 13391229 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1201797 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1201797 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 574153 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 574153 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 17210 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17210 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1775950 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1775950 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1775950 # number of overall misses
< system.cpu.dcache.overall_misses::total 1775950 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 32866409500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 32866409500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 22318082000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 22318082000 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230873000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 230873000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 55184491500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 55184491500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 55184491500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 55184491500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 9017242 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9017242 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6149937 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6149937 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200010 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200010 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 198989 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 198989 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15167179 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15167179 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15167179 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15167179 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133278 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.133278 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093359 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.093359 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086046 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086046 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.117092 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.117092 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.117092 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.117092 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27347.721371 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 27347.721371 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38871.314789 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38871.314789 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13415.049390 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13415.049390 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 31073.223627 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 31073.223627 # average overall miss latency
---
> system.cpu.dcache.tags.tag_accesses 63656757 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63656757 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 7813939 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7813939 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5575873 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5575873 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 182717 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 182717 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 198981 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 198981 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 13389812 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13389812 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13389812 # number of overall hits
> system.cpu.dcache.overall_hits::total 13389812 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1201834 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1201834 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 574561 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 574561 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 17285 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17285 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1776395 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1776395 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1776395 # number of overall misses
> system.cpu.dcache.overall_misses::total 1776395 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 32870602000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 32870602000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 22298477500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 22298477500 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232185000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 232185000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 55169079500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 55169079500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 55169079500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 55169079500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 9015773 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9015773 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6150434 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6150434 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200002 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200002 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 198981 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 198981 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15166207 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15166207 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15166207 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15166207 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133303 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.133303 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093418 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.093418 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086424 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086424 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.117128 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.117128 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.117128 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.117128 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27350.367854 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 27350.367854 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38809.591149 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 38809.591149 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13432.745155 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13432.745155 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 31056.763558 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 31056.763558 # average overall miss latency
530,535c529,534
< system.cpu.dcache.writebacks::writebacks 838228 # number of writebacks
< system.cpu.dcache.writebacks::total 838228 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127318 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 127318 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269861 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 269861 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 838310 # number of writebacks
> system.cpu.dcache.writebacks::total 838310 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127379 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 127379 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270264 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 270264 # number of WriteReq MSHR hits
538,599c537,598
< system.cpu.dcache.demand_mshr_hits::cpu.data 397179 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 397179 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 397179 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 397179 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074479 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1074479 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304292 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304292 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17207 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17207 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1378771 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1378771 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1378771 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1378771 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses
< system.cpu.dcache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29864669500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 29864669500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11367980000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11367980000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 213500500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 213500500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41232649500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 41232649500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41232649500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 41232649500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1451443000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1451443000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2042111500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2042111500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3493554500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3493554500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119158 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119158 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049479 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049479 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086031 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086031 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090905 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.090905 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090905 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.090905 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27794.558572 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27794.558572 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37358.786955 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37358.786955 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12407.770094 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12407.770094 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29905.364633 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 29905.364633 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29905.364633 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 29905.364633 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209322.613210 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209322.613210 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212255.638707 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212255.638707 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211027.151918 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211027.151918 # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 397643 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 397643 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 397643 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 397643 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074455 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1074455 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304297 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304297 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17282 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17282 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1378752 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1378752 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1378752 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1378752 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9620 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 9620 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16550 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 16550 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29867395000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 29867395000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11355989000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11355989000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214737500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214737500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41223384000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 41223384000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41223384000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 41223384000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450621500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450621500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2041589000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2041589000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3492210500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3492210500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119175 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119175 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049476 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049476 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086409 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086409 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090909 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.090909 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090909 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.090909 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27797.716051 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27797.716051 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37318.767520 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37318.767520 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12425.500521 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12425.500521 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29899.056538 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 29899.056538 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29899.056538 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 29899.056538 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209324.891775 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209324.891775 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212223.388773 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212223.388773 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211009.697885 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211009.697885 # average overall mshr uncacheable latency
601,609c600,608
< system.cpu.icache.tags.replacements 1459012 # number of replacements
< system.cpu.icache.tags.tagsinuse 509.459740 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 18968780 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1459523 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 12.996561 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 33609211500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 509.459740 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.995039 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.995039 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 1459068 # number of replacements
> system.cpu.icache.tags.tagsinuse 509.460685 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 18942908 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1459579 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 12.978337 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 33609235500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 509.460685 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.995040 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.995040 # Average percentage of cache occupancy
612,613c611,612
< system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 401 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id
615,652c614,651
< system.cpu.icache.tags.tag_accesses 21888175 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 21888175 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 18968783 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 18968783 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 18968783 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 18968783 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 18968783 # number of overall hits
< system.cpu.icache.overall_hits::total 18968783 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1459696 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1459696 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1459696 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1459696 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1459696 # number of overall misses
< system.cpu.icache.overall_misses::total 1459696 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 20145975000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 20145975000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 20145975000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 20145975000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 20145975000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 20145975000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 20428479 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 20428479 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 20428479 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 20428479 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 20428479 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 20428479 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071454 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.071454 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.071454 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.071454 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.071454 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.071454 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.486748 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13801.486748 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.486748 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13801.486748 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.486748 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13801.486748 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 21862421 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 21862421 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 18942911 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 18942911 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 18942911 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 18942911 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 18942911 # number of overall hits
> system.cpu.icache.overall_hits::total 18942911 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1459755 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1459755 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1459755 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1459755 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1459755 # number of overall misses
> system.cpu.icache.overall_misses::total 1459755 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 20136698000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 20136698000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 20136698000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 20136698000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 20136698000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 20136698000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 20402666 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 20402666 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 20402666 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 20402666 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 20402666 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 20402666 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071547 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.071547 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.071547 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.071547 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.071547 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.071547 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13794.573747 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13794.573747 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13794.573747 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13794.573747 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13794.573747 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13794.573747 # average overall miss latency
661,684c660,683
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459696 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1459696 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1459696 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1459696 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1459696 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1459696 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18686279000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 18686279000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18686279000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 18686279000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18686279000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 18686279000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071454 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071454 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071454 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.071454 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071454 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.071454 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12801.486748 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12801.486748 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12801.486748 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12801.486748 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12801.486748 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12801.486748 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459755 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1459755 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1459755 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1459755 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1459755 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1459755 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18676943000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 18676943000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18676943000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 18676943000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18676943000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 18676943000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071547 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071547 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071547 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.071547 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071547 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.071547 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12794.573747 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12794.573747 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12794.573747 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12794.573747 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12794.573747 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12794.573747 # average overall mshr miss latency
686,690c685,689
< system.cpu.l2cache.tags.replacements 339196 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65318.328839 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4996938 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 404358 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 12.357708 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 339197 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65316.861882 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4997134 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 404357 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 12.358223 # Average number of references to valid blocks.
692,700c691,699
< system.cpu.l2cache.tags.occ_blocks::writebacks 54387.720391 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 5865.311953 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5065.296495 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.829891 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.089498 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.077290 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996679 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 54372.711085 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 5866.673832 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5077.476965 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.829662 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.089518 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.077476 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996656 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65160 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
702,709c701,708
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5169 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2809 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55538 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 46373741 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 46373741 # Number of data accesses
< system.cpu.l2cache.Writeback_hits::writebacks 838228 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 838228 # number of Writeback hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5171 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2816 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55529 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994263 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 46375417 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 46375417 # Number of data accesses
> system.cpu.l2cache.Writeback_hits::writebacks 838310 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 838310 # number of Writeback hits
712,733c711,732
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187768 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187768 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1443233 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1443233 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819477 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 819477 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 1443233 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1007245 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2450478 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 1443233 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1007245 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2450478 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116534 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116534 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16403 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 16403 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272179 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 272179 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 16403 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 388713 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187763 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187763 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1443287 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1443287 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819540 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 819540 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 1443287 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1007303 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2450590 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 1443287 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1007303 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2450590 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116544 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116544 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16406 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 16406 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272166 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 272166 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 16406 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 388710 # number of demand (read+write) misses
735,736c734,735
< system.cpu.l2cache.overall_misses::cpu.inst 16403 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 388713 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.inst 16406 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 388710 # number of overall misses
740,795c739,794
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8935872000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8935872000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1324497500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 1324497500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19726651500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 19726651500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1324497500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 28662523500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 29987021000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1324497500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 28662523500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 29987021000 # number of overall miss cycles
< system.cpu.l2cache.Writeback_accesses::writebacks 838228 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 838228 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 304302 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304302 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1459636 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1459636 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091656 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1091656 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1459636 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1395958 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2855594 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1459636 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1395958 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2855594 # number of overall (read+write) accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800000 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382955 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.382955 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011238 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011238 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249327 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249327 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011238 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.278456 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.141868 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011238 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.278456 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.141868 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15812.500000 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15812.500000 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76680.385124 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76680.385124 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80747.271841 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80747.271841 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72476.757942 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72476.757942 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80747.271841 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73736.982041 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74020.826134 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80747.271841 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73736.982041 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74020.826134 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8923529500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8923529500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1314713000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 1314713000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19729862500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 19729862500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1314713000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 28653392000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 29968105000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1314713000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 28653392000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 29968105000 # number of overall miss cycles
> system.cpu.l2cache.Writeback_accesses::writebacks 838310 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 838310 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 304307 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304307 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1459693 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1459693 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091706 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1091706 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1459693 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1396013 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2855706 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1459693 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1396013 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2855706 # number of overall (read+write) accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.809524 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382982 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.382982 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011239 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011239 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249303 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249303 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011239 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.278443 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.141862 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011239 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.278443 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.141862 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14882.352941 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14882.352941 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76567.901393 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76567.901393 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80136.108741 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80136.108741 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72492.017739 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72492.017739 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80136.108741 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73714.059324 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73974.133335 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80136.108741 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73714.059324 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73974.133335 # average overall miss latency
804,805c803,804
< system.cpu.l2cache.writebacks::writebacks 76513 # number of writebacks
< system.cpu.l2cache.writebacks::total 76513 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 76511 # number of writebacks
> system.cpu.l2cache.writebacks::total 76511 # number of writebacks
808,817c807,816
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116534 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116534 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16403 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16403 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272179 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272179 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 16403 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 388713 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116544 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116544 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16406 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16406 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272166 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272166 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 16406 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 388710 # number of demand (read+write) MSHR misses
819,820c818,819
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 16403 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 388713 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 16406 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 388710 # number of overall MSHR misses
822,847c821,846
< system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 431000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 431000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7770532000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7770532000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1160467500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1160467500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17006826000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17006826000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1160467500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24777358000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 25937825500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1160467500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24777358000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 25937825500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364748500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364748500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1931469000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1931469000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3296217500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3296217500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9620 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9620 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16550 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16550 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 453499 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 453499 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7758089500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7758089500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1150653000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1150653000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17010167000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17010167000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1150653000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24768256500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 25918909500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1150653000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24768256500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 25918909500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363977000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363977000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1930958000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1930958000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3294935000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3294935000 # number of overall MSHR uncacheable cycles
850,883c849,882
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382955 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382955 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011238 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249327 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249327 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.141868 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.141868 # mshr miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26937.500000 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26937.500000 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66680.385124 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66680.385124 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70747.271841 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70747.271841 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62483.975619 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62483.975619 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196819.800981 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196819.800981 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200755.534768 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200755.534768 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199107.067351 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199107.067351 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382982 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382982 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011239 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249303 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249303 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.141862 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.141862 # mshr miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26676.411765 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26676.411765 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66567.901393 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66567.901393 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70136.108741 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70136.108741 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62499.235761 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62499.235761 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196822.077922 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196822.077922 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200723.284823 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200723.284823 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199089.728097 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199089.728097 # average overall mshr uncacheable latency
885,896c884,895
< system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2558426 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 956270 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 2277118 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459696 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091829 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2558531 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 9620 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 9620 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 956362 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 2277135 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 304307 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 304307 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459755 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091879 # Transaction distribution
899,906c898,905
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377747 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219297 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8597044 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93416704 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041221 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 236457925 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 422839 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 6149292 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377903 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219455 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8597358 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93420352 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143049956 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 236470308 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 422854 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 6149527 # Request fanout histogram
908c907
< system.cpu.toL2Bus.snoop_fanout::stdev 0.252990 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::stdev 0.252989 # Request fanout histogram
911,912c910,911
< system.cpu.toL2Bus.snoop_fanout::1 5726669 93.13% 93.13% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 422623 6.87% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 5726891 93.13% 93.13% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 422636 6.87% 100.00% # Request fanout histogram
916,917c915,916
< system.cpu.toL2Bus.snoop_fanout::total 6149292 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3706373000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 6149527 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3706565999 # Layer occupancy (ticks)
921c920
< system.cpu.toL2Bus.respLayer0.occupancy 2189771045 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2189850563 # Layer occupancy (ticks)
923c922
< system.cpu.toL2Bus.respLayer1.occupancy 2105677995 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2105755497 # Layer occupancy (ticks)
937,941c936,940
< system.iobus.trans_dist::ReadReq 7107 # Transaction distribution
< system.iobus.trans_dist::ReadResp 7107 # Transaction distribution
< system.iobus.trans_dist::WriteReq 51173 # Transaction distribution
< system.iobus.trans_dist::WriteResp 51173 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5104 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
> system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
> system.iobus.trans_dist::WriteReq 51172 # Transaction distribution
> system.iobus.trans_dist::WriteResp 51172 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5096 # Packet count per connected master and slave (bytes)
948c947
< system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
953c952
< system.iobus.pkt_count_system.bridge.master::total 33110 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 33100 # Packet count per connected master and slave (bytes)
956,957c955,956
< system.iobus.pkt_count::total 116560 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20416 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 116550 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20384 # Cumulative packet size per connected master and slave (bytes)
964c963
< system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
969c968
< system.iobus.pkt_size_system.bridge.master::total 44357 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 44324 # Cumulative packet size per connected master and slave (bytes)
972,973c971,972
< system.iobus.pkt_size::total 2705965 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 4712000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2705932 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 4707000 # Layer occupancy (ticks)
987c986
< system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
995c994
< system.iobus.reqLayer29.occupancy 216063756 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 216043265 # Layer occupancy (ticks)
999c998
< system.iobus.respLayer0.occupancy 23489000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 23480000 # Layer occupancy (ticks)
1004c1003
< system.iocache.tags.tagsinuse 1.294607 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.302220 # Cycle average of tags in use
1008,1011c1007,1010
< system.iocache.tags.warmup_cycle 1729988854000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.294607 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.080913 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.080913 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1729987199000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.302220 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.081389 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.081389 # Average percentage of cache occupancy
1027,1028c1026,1027
< system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907200873 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4907200873 # number of WriteLineReq miss cycles
---
> system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908791382 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4908791382 # number of WriteLineReq miss cycles
1051,1052c1050,1051
< system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118097.826170 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118097.826170 # average WriteLineReq miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118136.103725 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 118136.103725 # average WriteLineReq miss latency
1057c1056
< system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked
1059c1058
< system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
1061c1060
< system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
1077,1078c1076,1077
< system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829600873 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2829600873 # number of WriteLineReq MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831191382 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2831191382 # number of WriteLineReq MSHR miss cycles
1093,1094c1092,1093
< system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68097.826170 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68097.826170 # average WriteLineReq mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68136.103725 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68136.103725 # average WriteLineReq mshr miss latency
1100,1110c1099,1109
< system.membus.trans_dist::ReadReq 6934 # Transaction distribution
< system.membus.trans_dist::ReadResp 295673 # Transaction distribution
< system.membus.trans_dist::WriteReq 9621 # Transaction distribution
< system.membus.trans_dist::WriteResp 9621 # Transaction distribution
< system.membus.trans_dist::Writeback 118025 # Transaction distribution
< system.membus.trans_dist::CleanEvict 262175 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 156 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 156 # Transaction distribution
< system.membus.trans_dist::ReadExReq 116394 # Transaction distribution
< system.membus.trans_dist::ReadExResp 116394 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 288755 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 6930 # Transaction distribution
> system.membus.trans_dist::ReadResp 295659 # Transaction distribution
> system.membus.trans_dist::WriteReq 9620 # Transaction distribution
> system.membus.trans_dist::WriteResp 9620 # Transaction distribution
> system.membus.trans_dist::Writeback 118023 # Transaction distribution
> system.membus.trans_dist::CleanEvict 262178 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 157 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 157 # Transaction distribution
> system.membus.trans_dist::ReadExReq 116404 # Transaction distribution
> system.membus.trans_dist::ReadExResp 116404 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution
1114,1115c1113,1114
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33110 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148632 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33100 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148635 # Packet count per connected master and slave (bytes)
1117c1116
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181774 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181767 # Packet count per connected master and slave (bytes)
1120,1123c1119,1122
< system.membus.pkt_count::total 1306591 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44357 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796800 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30841157 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1306584 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44324 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796672 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30840996 # Cumulative packet size per connected master and slave (bytes)
1126c1125
< system.membus.pkt_size::total 33498885 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 33498724 # Cumulative packet size per connected master and slave (bytes)
1128c1127
< system.membus.snoop_fanout::samples 843789 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 843798 # Request fanout histogram
1133c1132
< system.membus.snoop_fanout::1 843789 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 843798 100.00% 100.00% # Request fanout histogram
1138,1139c1137,1138
< system.membus.snoop_fanout::total 843789 # Request fanout histogram
< system.membus.reqLayer0.occupancy 29576000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 843798 # Request fanout histogram
> system.membus.reqLayer0.occupancy 29290000 # Layer occupancy (ticks)
1141c1140
< system.membus.reqLayer1.occupancy 1318697936 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1318757186 # Layer occupancy (ticks)
1145c1144
< system.membus.respLayer1.occupancy 2160007596 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2160035845 # Layer occupancy (ticks)
1147c1146
< system.membus.respLayer2.occupancy 72031934 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 72019946 # Layer occupancy (ticks)