7,11c7,11
< host_inst_rate 275099 # Simulator instruction rate (inst/s)
< host_op_rate 275099 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 9249537203 # Simulator tick rate (ticks/s)
< host_mem_usage 373576 # Number of bytes of host memory used
< host_seconds 204.03 # Real time elapsed on the host
---
> host_inst_rate 272052 # Simulator instruction rate (inst/s)
> host_op_rate 272052 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9147074399 # Simulator tick rate (ticks/s)
> host_mem_usage 373996 # Number of bytes of host memory used
> host_seconds 206.32 # Real time elapsed on the host
49c49
< system.physmem.bytesWritten 8556800 # Total number of bytes written to DRAM
---
> system.physmem.bytesWritten 8555840 # Total number of bytes written to DRAM
53,54c53,54
< system.physmem.mergedWrBursts 25922 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write
---
> system.physmem.mergedWrBursts 25937 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 159 # Number of requests that are neither read nor write
73,74c73,74
< system.physmem.perBankWrBursts::2 9125 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8822 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 9134 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8817 # Per bank write bursts
78c78
< system.physmem.perBankWrBursts::7 7379 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 7380 # Per bank write bursts
82,84c82,84
< system.physmem.perBankWrBursts::11 7873 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8188 # Per bank write bursts
< system.physmem.perBankWrBursts::13 9058 # Per bank write bursts
---
> system.physmem.perBankWrBursts::11 7871 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8181 # Per bank write bursts
> system.physmem.perBankWrBursts::13 9046 # Per bank write bursts
86c86
< system.physmem.perBankWrBursts::15 8879 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 8880 # Per bank write bursts
88c88
< system.physmem.numWrRetry 49 # Number of times write queue was full causing retry
---
> system.physmem.numWrRetry 48 # Number of times write queue was full causing retry
152,188c152,188
< system.physmem.wrQLenPdf::16 1823 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5859 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5540 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5570 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5709 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5633 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5486 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 5467 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5625 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5831 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 6839 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6092 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6407 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7561 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6547 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6436 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5994 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 769 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 1207 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 1362 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 1280 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 845 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1622 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 1798 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1564 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1800 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1975 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1915 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 2152 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 2564 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 2779 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 2158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 1660 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 1251 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 773 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::16 1878 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5779 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5566 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5580 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5645 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5477 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5437 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5641 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5825 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 6756 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6161 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6363 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7635 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6502 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6461 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5991 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1224 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 780 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 1384 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 1265 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 883 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1555 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 1873 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1560 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1827 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1983 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1921 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 2157 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 2541 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 2774 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 2169 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 1666 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 1329 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 1241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 764 # What write queue length does an incoming req see
190,196c190,196
< system.physmem.wrQLenPdf::54 298 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 240 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 268 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 209 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 154 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::54 299 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 261 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 161 # What write queue length does an incoming req see
198,199c198,199
< system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see
201,203c201,203
< system.physmem.bytesPerActivate::mean 531.935916 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 325.040765 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 415.485108 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::mean 531.921099 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 325.032687 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 415.479352 # Bytes accessed per row activation
205c205
< system.physmem.bytesPerActivate::128-255 10955 16.91% 39.59% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::128-255 10956 16.91% 39.59% # Bytes accessed per row activation
207,211c207,211
< system.physmem.bytesPerActivate::384-511 3097 4.78% 52.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2483 3.83% 56.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1877 2.90% 59.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1493 2.30% 61.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1431 2.21% 64.04% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::384-511 3096 4.78% 52.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2482 3.83% 56.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1882 2.90% 59.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1491 2.30% 61.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1429 2.21% 64.04% # Bytes accessed per row activation
223,225c223,225
< system.physmem.wrPerTurnAround::mean 27.285714 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.337905 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 63.692079 # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::mean 27.282653 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.334547 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 63.863816 # Writes before turning the bus around for reads
228,234c228,234
< system.physmem.wrPerTurnAround::64-95 11 0.22% 96.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-127 6 0.12% 96.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-159 26 0.53% 97.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-191 25 0.51% 97.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-223 16 0.33% 98.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-255 2 0.04% 98.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-287 6 0.12% 98.16% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::64-95 12 0.24% 96.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-127 6 0.12% 96.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-159 26 0.53% 97.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-191 25 0.51% 97.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-223 16 0.33% 98.02% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-255 3 0.06% 98.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-287 4 0.08% 98.16% # Writes before turning the bus around for reads
237,242c237,242
< system.physmem.wrPerTurnAround::352-383 21 0.43% 99.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::384-415 2 0.04% 99.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::448-479 6 0.12% 99.35% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::480-511 7 0.14% 99.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::512-543 9 0.18% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::544-575 5 0.10% 99.78% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::352-383 20 0.41% 99.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-415 2 0.04% 99.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::448-479 6 0.12% 99.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-511 7 0.14% 99.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-543 9 0.18% 99.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::544-575 6 0.12% 99.78% # Writes before turning the bus around for reads
247,248c247,248
< system.physmem.totQLat 2145870750 # Total ticks spent queuing
< system.physmem.totMemAccLat 9735908250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2145936500 # Total ticks spent queuing
> system.physmem.totMemAccLat 9735974000 # Total ticks spent from burst creation until serviced by the DRAM
250c250
< system.physmem.avgQLat 5301.04 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5301.20 # Average queueing delay per DRAM burst
252c252
< system.physmem.avgMemAccLat 24051.04 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 24051.20 # Average memory access latency per DRAM burst
264c264
< system.physmem.writeRowHits 110090 # Number of row buffer hits during writes
---
> system.physmem.writeRowHits 110075 # Number of row buffer hits during writes
269,270c269,270
< system.physmem_0.actEnergy 238971600 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 130391250 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.actEnergy 238979160 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 130395375 # Energy for precharge commands per rank (pJ)
272c272
< system.physmem_0.writeEnergy 431114400 # Energy for write commands per rank (pJ)
---
> system.physmem_0.writeEnergy 431146800 # Energy for write commands per rank (pJ)
274,278c274,278
< system.physmem_0.actBackEnergy 60578040195 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1079167578750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1265384866875 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.517315 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1795079554966 # Time in different power states
---
> system.physmem_0.actBackEnergy 60577818750 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1079167773000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1265384883765 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.517324 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1795079851716 # Time in different power states
281c281
< system.physmem_0.memoryStateTime::ACT 29080496284 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 29080199534 # Time in different power states
283,284c283,284
< system.physmem_1.actEnergy 250840800 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 136867500 # Energy for precharge commands per rank (pJ)
---
> system.physmem_1.actEnergy 250833240 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 136863375 # Energy for precharge commands per rank (pJ)
286c286
< system.physmem_1.writeEnergy 435261600 # Energy for write commands per rank (pJ)
---
> system.physmem_1.writeEnergy 435132000 # Energy for write commands per rank (pJ)
288,292c288,292
< system.physmem_1.actBackEnergy 61601133195 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1078270137000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1265535350775 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.597050 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1793586337716 # Time in different power states
---
> system.physmem_1.actBackEnergy 61600331205 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1078270840500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1265535111000 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.596923 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1793587329216 # Time in different power states
295c295
< system.physmem_1.memoryStateTime::ACT 30573727284 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 30572735784 # Time in different power states
297c297
< system.cpu.branchPred.lookups 15007831 # Number of BP lookups
---
> system.cpu.branchPred.lookups 15007833 # Number of BP lookups
300c300
< system.cpu.branchPred.BTBLookups 9968114 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 9968116 # Number of BTB lookups
303c303
< system.cpu.branchPred.BTBHitPct 52.204971 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 52.204960 # BTB Hit Percentage
311c311
< system.cpu.dtb.read_hits 9242509 # DTB read hits
---
> system.cpu.dtb.read_hits 9242504 # DTB read hits
315c315
< system.cpu.dtb.write_hits 6385998 # DTB write hits
---
> system.cpu.dtb.write_hits 6386002 # DTB write hits
319c319
< system.cpu.dtb.data_hits 15628507 # DTB hits
---
> system.cpu.dtb.data_hits 15628506 # DTB hits
339c339
< system.cpu.numCycles 180833283 # number of cpu cycles simulated
---
> system.cpu.numCycles 180833533 # number of cpu cycles simulated
344c344
< system.cpu.discardedOps 2493053 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 2493054 # Number of ops (including micro ops) which were discarded before commit
346,347c346,347
< system.cpu.quiesceCycles 3593535643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 3.221772 # CPI: cycles per instruction
---
> system.cpu.quiesceCycles 3593535393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 3.221776 # CPI: cycles per instruction
362c362
< system.cpu.kern.ipl_ticks::0 1834551091000 97.21% 97.21% # number of cycles we spent at this ipl
---
> system.cpu.kern.ipl_ticks::0 1834551053500 97.21% 97.21% # number of cycles we spent at this ipl
365c365
< system.cpu.kern.ipl_ticks::31 51875728000 2.75% 100.00% # number of cycles we spent at this ipl
---
> system.cpu.kern.ipl_ticks::31 51875765500 2.75% 100.00% # number of cycles we spent at this ipl
430,432c430,432
< system.cpu.kern.mode_ticks::kernel 36591764000 1.94% 1.94% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 4134630500 0.22% 2.16% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1846457071000 97.84% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_ticks::kernel 36591863000 1.94% 1.94% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 4134622500 0.22% 2.16% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1846456980000 97.84% 100.00% # number of ticks spent at the given mode
434,436c434,436
< system.cpu.tickCycles 84552258 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 96281025 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 1395325 # number of replacements
---
> system.cpu.tickCycles 84552243 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 96281290 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 1395323 # number of replacements
438,440c438,440
< system.cpu.dcache.tags.total_refs 13774282 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1395837 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 9.868116 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 13774277 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1395835 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 9.868127 # Average number of references to valid blocks.
450,453c450,453
< system.cpu.dcache.tags.tag_accesses 63660758 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63660758 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 7815437 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7815437 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 63660728 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63660728 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 7815432 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7815432 # number of ReadReq hits
460,465c460,465
< system.cpu.dcache.demand_hits::cpu.data 13392432 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13392432 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13392432 # number of overall hits
< system.cpu.dcache.overall_hits::total 13392432 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1201539 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1201539 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 13392427 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13392427 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13392427 # number of overall hits
> system.cpu.dcache.overall_hits::total 13392427 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1201537 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1201537 # number of ReadReq misses
470,477c470,477
< system.cpu.dcache.demand_misses::cpu.data 1774788 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1774788 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1774788 # number of overall misses
< system.cpu.dcache.overall_misses::total 1774788 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999838250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 32999838250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461596052 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 22461596052 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 1774786 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1774786 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1774786 # number of overall misses
> system.cpu.dcache.overall_misses::total 1774786 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999736250 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 32999736250 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461890056 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 22461890056 # number of WriteReq miss cycles
480,485c480,485
< system.cpu.dcache.demand_miss_latency::cpu.data 55461434302 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 55461434302 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 55461434302 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 55461434302 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 9016976 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9016976 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 55461626306 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 55461626306 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 55461626306 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 55461626306 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 9016969 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9016969 # number of ReadReq accesses(hits+misses)
492,495c492,495
< system.cpu.dcache.demand_accesses::cpu.data 15167220 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15167220 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15167220 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15167220 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 15167213 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15167213 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15167213 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15167213 # number of overall (read+write) accesses
506,509c506,509
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.641805 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.641805 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39182.965957 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 39182.965957 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.602630 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.602630 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39183.478830 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 39183.478830 # average WriteReq miss latency
512,515c512,515
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 31249.610828 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 31249.610828 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 31249.754227 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 31249.754227 # average overall miss latency
536,537c536,537
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074431 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1074431 # number of ReadReq MSHR misses
---
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074429 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses
542,549c542,555
< system.cpu.dcache.demand_mshr_misses::cpu.data 1378684 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1378684 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1378684 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1378684 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29341442500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 29341442500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11237495843 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11237495843 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 1378682 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1378682 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1378682 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1378682 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29341393000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 29341393000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11237642841 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11237642841 # number of WriteReq MSHR miss cycles
552,555c558,561
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40578938343 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 40578938343 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40578938343 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 40578938343 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40579035841 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 40579035841 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40579035841 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 40579035841 # number of overall MSHR miss cycles
558,561c564,567
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2018255500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2018255500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3451560000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3451560000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2018260000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2018260000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3451564500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3451564500 # number of overall MSHR uncacheable cycles
572,575c578,581
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27308.819738 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27308.819738 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36934.708427 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36934.708427 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27308.824501 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27308.824501 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36935.191571 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36935.191571 # average WriteReq mshr miss latency
578,587c584,593
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29433.095868 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 29433.095868 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29433.095868 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 29433.095868 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29433.209283 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 29433.209283 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29433.209283 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 29433.209283 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206826.046176 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206826.046176 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209820.147624 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209820.147624 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208566.348420 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208566.348420 # average overall mshr uncacheable latency
617,622c623,628
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 20155087658 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 20155087658 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 20155087658 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 20155087658 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 20155087658 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 20155087658 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 20155075408 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 20155075408 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 20155075408 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 20155075408 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 20155075408 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 20155075408 # number of overall miss cycles
635,640c641,646
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13807.039099 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13807.039099 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13807.039099 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13807.039099 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13807.039099 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13807.039099 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13807.030707 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13807.030707 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13807.030707 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13807.030707 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13807.030707 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13807.030707 # average overall miss latency
655,660c661,666
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17958185842 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 17958185842 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17958185842 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 17958185842 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17958185842 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 17958185842 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17958174092 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 17958174092 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17958174092 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 17958174092 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17958174092 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 17958174092 # number of overall MSHR miss cycles
667,672c673,678
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12302.073713 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12302.073713 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12302.073713 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12302.073713 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12302.073713 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12302.073713 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12302.065664 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12302.065664 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12302.065664 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12302.065664 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12302.065664 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12302.065664 # average overall mshr miss latency
675,676c681,682
< system.cpu.l2cache.tags.tagsinuse 65314.689309 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2982707 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 65314.689332 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2982705 # Total number of references to valid blocks.
678c684
< system.cpu.l2cache.tags.avg_refs 7.372828 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 7.372823 # Average number of references to valid blocks.
680,681c686,687
< system.cpu.l2cache.tags.occ_blocks::writebacks 54416.774547 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 5825.207065 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 54416.774568 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 5825.207067 # Average occupied blocks per requestor
694,695c700,701
< system.cpu.l2cache.tags.tag_accesses 30259084 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 30259084 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 30259068 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 30259068 # Number of data accesses
697,698c703,704
< system.cpu.l2cache.ReadReq_hits::cpu.data 819387 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2262647 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.data 819385 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2262645 # number of ReadReq hits
703,704c709,710
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187599 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187599 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187597 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187597 # number of ReadExReq hits
706,707c712,713
< system.cpu.l2cache.demand_hits::cpu.data 1006986 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2450246 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 1006982 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2450242 # number of demand (read+write) hits
709,710c715,716
< system.cpu.l2cache.overall_hits::cpu.data 1006986 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2450246 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 1006982 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2450242 # number of overall hits
716,717c722,723
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116658 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116658 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116660 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116660 # number of ReadExReq misses
719,720c725,726
< system.cpu.l2cache.demand_misses::cpu.data 388868 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 405312 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 388870 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 405314 # number of demand (read+write) misses
722,726c728,732
< system.cpu.l2cache.overall_misses::cpu.data 388868 # number of overall misses
< system.cpu.l2cache.overall_misses::total 405312 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1322916250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19744352250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 21067268500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.data 388870 # number of overall misses
> system.cpu.l2cache.overall_misses::total 405314 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1322904500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19744325250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 21067229750 # number of ReadReq miss cycles
729,736c735,742
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8959337611 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8959337611 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1322916250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 28703689861 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 30026606111 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1322916250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 28703689861 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 30026606111 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8959505609 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8959505609 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1322904500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 28703830859 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 30026735359 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1322904500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 28703830859 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 30026735359 # number of overall miss cycles
738,739c744,745
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1091597 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2551301 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1091595 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2551299 # number of ReadReq accesses(hits+misses)
747,748c753,754
< system.cpu.l2cache.demand_accesses::cpu.data 1395854 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2855558 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.data 1395852 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2855556 # number of demand (read+write) accesses
750,751c756,757
< system.cpu.l2cache.overall_accesses::cpu.data 1395854 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2855558 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.data 1395852 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2855556 # number of overall (read+write) accesses
757,758c763,764
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383419 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383419 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383426 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383426 # miss rate for ReadExReq accesses
760,761c766,767
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.278588 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.141938 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.278590 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.141939 # miss rate for demand accesses
763,767c769,773
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.278588 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.141938 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80449.784116 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72533.530179 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 72984.502207 # average ReadReq miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.278590 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.141939 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80449.069569 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72533.430991 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72984.367963 # average ReadReq miss latency
770,777c776,783
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76800.027525 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76800.027525 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80449.784116 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73813.453051 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74082.697061 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80449.784116 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73813.453051 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74082.697061 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76800.150943 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76800.150943 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80449.069569 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73813.436004 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74082.650387 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80449.069569 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73813.436004 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74082.650387 # average overall miss latency
793,794c799,800
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116658 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116658 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116660 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116660 # number of ReadExReq MSHR misses
796,797c802,803
< system.cpu.l2cache.demand_mshr_misses::cpu.data 388868 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 405312 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 388870 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 405314 # number of demand (read+write) MSHR misses
799,803c805,815
< system.cpu.l2cache.overall_mshr_misses::cpu.data 388868 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 405312 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1116961750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16343103250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17460065000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 388870 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 405314 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9619 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9619 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16549 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16549 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1116950000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16343076250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17460026250 # number of ReadReq MSHR miss cycles
806,813c818,825
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7500878889 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7500878889 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1116961750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23843982139 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 24960943889 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1116961750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23843982139 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 24960943889 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7501019891 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7501019891 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1116950000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23844096141 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 24961046141 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1116950000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23844096141 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 24961046141 # number of overall MSHR miss cycles
816,819c828,831
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893208000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893208000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229474500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229474500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893212500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893212500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229479000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229479000 # number of overall MSHR uncacheable cycles
825,826c837,838
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383419 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383419 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383426 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383426 # mshr miss rate for ReadExReq accesses
828,829c840,841
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.141938 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.141939 # mshr miss rate for demand accesses
831,835c843,847
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.141938 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67925.185478 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.585100 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.867828 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278590 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.141939 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67924.470932 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.485912 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.733584 # average ReadReq mshr miss latency
838,851c850,863
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.024045 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.024045 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.130387 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.130387 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67924.470932 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.368300 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.465725 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192823.448773 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192823.448773 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196820.095644 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196820.095644 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195146.474107 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195146.474107 # average overall mshr uncacheable latency
853,854c865,866
< system.cpu.toL2Bus.trans_dist::ReadReq 2558469 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2558436 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2558467 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2558434 # Transaction distribution
858c870
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41593 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41592 # Transaction distribution
865,866c877,878
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663181 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 6582654 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663177 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 6582650 # Packet count per connected master and slave (bytes)
868,873c880,885
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030876 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 236451932 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 41987 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3735584 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.011181 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.105146 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030748 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 236451804 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 41986 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3752130 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.011131 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.104915 # Request fanout histogram
876,877c888,889
< system.cpu.toL2Bus.snoop_fanout::1 3693818 98.88% 98.88% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 41766 1.12% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 3710365 98.89% 98.89% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 41765 1.11% 100.00% # Request fanout histogram
881,882c893,894
< system.cpu.toL2Bus.snoop_fanout::total 3735584 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2698164499 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 3752130 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2698163499 # Layer occupancy (ticks)
886c898
< system.cpu.toL2Bus.respLayer0.occupancy 2193277658 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2193277408 # Layer occupancy (ticks)
888c900
< system.cpu.toL2Bus.respLayer1.occupancy 2194690407 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2194687409 # Layer occupancy (ticks)
961c973
< system.iobus.reqLayer29.occupancy 242093194 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 242092694 # Layer occupancy (ticks)
993,994c1005,1006
< system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8777958811 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 8777958811 # number of WriteInvalidateReq miss cycles
---
> system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775999311 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 8775999311 # number of WriteInvalidateReq miss cycles
1017,1018c1029,1030
< system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211252.378008 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 211252.378008 # average WriteInvalidateReq miss latency
---
> system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211205.220230 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 211205.220230 # average WriteInvalidateReq miss latency
1023c1035
< system.iocache.blocked_cycles::no_mshrs 73082 # number of cycles access was blocked
---
> system.iocache.blocked_cycles::no_mshrs 73059 # number of cycles access was blocked
1025c1037
< system.iocache.blocked::no_mshrs 10004 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 10002 # number of cycles access was blocked
1027c1039
< system.iocache.avg_blocked_cycles::no_mshrs 7.305278 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 7.304439 # average number of cycles each access was blocked
1043,1044c1055,1056
< system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6617254811 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6617254811 # number of WriteInvalidateReq MSHR miss cycles
---
> system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6615295311 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6615295311 # number of WriteInvalidateReq MSHR miss cycles
1059,1060c1071,1072
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159252.378008 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159252.378008 # average WriteInvalidateReq mshr miss latency
---
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159205.220230 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159205.220230 # average WriteInvalidateReq mshr miss latency
1073,1074c1085,1086
< system.membus.trans_dist::UpgradeReq 159 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 159 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 161 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 161 # Transaction distribution
1079c1091
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886945 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886949 # Packet count per connected master and slave (bytes)
1081c1093
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920075 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920079 # Packet count per connected master and slave (bytes)
1084c1096
< system.membus.pkt_count::total 1044879 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1044883 # Packet count per connected master and slave (bytes)
1092c1104
< system.membus.snoop_fanout::samples 565206 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 581756 # Request fanout histogram
1097c1109
< system.membus.snoop_fanout::1 565206 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 581756 100.00% 100.00% # Request fanout histogram
1102,1103c1114,1115
< system.membus.snoop_fanout::total 565206 # Request fanout histogram
< system.membus.reqLayer0.occupancy 30238000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 581756 # Request fanout histogram
> system.membus.reqLayer0.occupancy 30242500 # Layer occupancy (ticks)
1105c1117
< system.membus.reqLayer1.occupancy 1230315562 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1230317312 # Layer occupancy (ticks)
1107c1119
< system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 21000 # Layer occupancy (ticks)
1109c1121
< system.membus.respLayer1.occupancy 2160768093 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2160772841 # Layer occupancy (ticks)