3,5c3,5
< sim_seconds 1.883224 # Number of seconds simulated
< sim_ticks 1883224346500 # Number of ticks simulated
< final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.884241 # Number of seconds simulated
> sim_ticks 1884241273000 # Number of ticks simulated
> final_tick 1884241273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 279379 # Simulator instruction rate (inst/s)
< host_op_rate 279379 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 9375076807 # Simulator tick rate (ticks/s)
< host_mem_usage 311380 # Number of bytes of host memory used
< host_seconds 200.88 # Real time elapsed on the host
< sim_insts 56120453 # Number of instructions simulated
< sim_ops 56120453 # Number of ops (including micro ops) simulated
---
> host_inst_rate 193195 # Simulator instruction rate (inst/s)
> host_op_rate 193195 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 6486085343 # Simulator tick rate (ticks/s)
> host_mem_usage 317148 # Number of bytes of host memory used
> host_seconds 290.51 # Real time elapsed on the host
> sim_insts 56124126 # Number of instructions simulated
> sim_ops 56124126 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::cpu.inst 25931648 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 25914944 # Number of bytes read from this memory
18,24c18,23
< system.physmem.bytes_read::total 25932608 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4903936 # Number of bytes written to this memory
< system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7563264 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 405182 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25915904 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1052928 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1052928 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7561408 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7561408 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 404921 # Number of read requests responded to by this memory
26,59c25,56
< system.physmem.num_reads::total 405197 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 76624 # Number of write requests responded to by this memory
< system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 118176 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 13769813 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 13770323 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 559041 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 559041 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2604011 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::tsunami.ide 1412114 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4016125 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2604011 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 13769813 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 17786448 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 405197 # Number of read requests accepted
< system.physmem.writeReqs 118176 # Number of write requests accepted
< system.physmem.readBursts 405197 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 118176 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25920704 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 11904 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7562112 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25932608 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7563264 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 186 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 25484 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25740 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25857 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25788 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25237 # Per bank write bursts
< system.physmem.perBankRdBursts::5 24959 # Per bank write bursts
---
> system.physmem.num_reads::total 404936 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 118147 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 118147 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 13753517 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 13754026 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 558807 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 558807 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4012972 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4012972 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4012972 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 13753517 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 17766999 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 404936 # Number of read requests accepted
> system.physmem.writeReqs 159699 # Number of write requests accepted
> system.physmem.readBursts 404936 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 159699 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25909568 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue
> system.physmem.bytesWritten 10083392 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25915904 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 10220736 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2126 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 153 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 25482 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25742 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25842 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25776 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25226 # Per bank write bursts
> system.physmem.perBankRdBursts::5 24953 # Per bank write bursts
61,85c58,82
< system.physmem.perBankRdBursts::7 24586 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25127 # Per bank write bursts
< system.physmem.perBankRdBursts::9 25284 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25531 # Per bank write bursts
< system.physmem.perBankRdBursts::11 24857 # Per bank write bursts
< system.physmem.perBankRdBursts::12 24549 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25592 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25866 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25740 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7812 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7680 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8067 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7745 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7320 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6957 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6792 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6401 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7236 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6892 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7391 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6866 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7045 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8010 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7989 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7955 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 24563 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25102 # Per bank write bursts
> system.physmem.perBankRdBursts::9 25273 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25528 # Per bank write bursts
> system.physmem.perBankRdBursts::11 24851 # Per bank write bursts
> system.physmem.perBankRdBursts::12 24526 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25574 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25842 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25743 # Per bank write bursts
> system.physmem.perBankWrBursts::0 10288 # Per bank write bursts
> system.physmem.perBankWrBursts::1 10037 # Per bank write bursts
> system.physmem.perBankWrBursts::2 10678 # Per bank write bursts
> system.physmem.perBankWrBursts::3 10053 # Per bank write bursts
> system.physmem.perBankWrBursts::4 9806 # Per bank write bursts
> system.physmem.perBankWrBursts::5 9437 # Per bank write bursts
> system.physmem.perBankWrBursts::6 9137 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8750 # Per bank write bursts
> system.physmem.perBankWrBursts::8 9885 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8937 # Per bank write bursts
> system.physmem.perBankWrBursts::10 9881 # Per bank write bursts
> system.physmem.perBankWrBursts::11 9301 # Per bank write bursts
> system.physmem.perBankWrBursts::12 9770 # Per bank write bursts
> system.physmem.perBankWrBursts::13 10691 # Per bank write bursts
> system.physmem.perBankWrBursts::14 10395 # Per bank write bursts
> system.physmem.perBankWrBursts::15 10507 # Per bank write bursts
87,88c84,85
< system.physmem.numWrRetry 7 # Number of times write queue was full causing retry
< system.physmem.totGap 1883215617500 # Total gap between requests
---
> system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
> system.physmem.totGap 1884232486500 # Total gap between requests
95c92
< system.physmem.readPktSize::6 405197 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 404936 # Read request sizes (log2)
102,105c99,102
< system.physmem.writePktSize::6 118176 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 402689 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2242 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 159699 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 402545 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2209 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see
150,217c147,214
< system.physmem.wrQLenPdf::15 1502 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2155 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5922 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6116 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8341 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8743 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8450 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8575 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6692 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5817 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5536 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5545 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5502 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 184 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 186 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 152 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 96 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 94 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 63140 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 530.294837 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 322.585016 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 415.640457 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14650 23.20% 23.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 10589 16.77% 39.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5075 8.04% 48.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3003 4.76% 52.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2370 3.75% 56.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2105 3.33% 59.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1364 2.16% 62.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1607 2.55% 64.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 22377 35.44% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63140 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5316 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 76.186983 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2896.748549 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5313 99.94% 99.94% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1884 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3925 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 8041 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 9181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 9850 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 10687 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 11113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 12053 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 11634 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 11766 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 10716 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9987 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8498 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 8067 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6879 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6438 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6292 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 397 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 371 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 339 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 278 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 254 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 248 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 226 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 219 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 65749 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 547.429771 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 335.789885 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 418.130322 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14719 22.39% 22.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 10714 16.30% 38.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4807 7.31% 45.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3176 4.83% 50.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2550 3.88% 54.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1953 2.97% 57.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1437 2.19% 59.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1697 2.58% 62.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 24696 37.56% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 65749 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5738 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 70.553154 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2788.767091 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5735 99.95% 99.95% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes
220,265c217,257
< system.physmem.rdPerTurnAround::total 5316 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5316 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.226862 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.933757 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 20.590348 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 4662 87.70% 87.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 15 0.28% 87.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 21 0.40% 88.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 225 4.23% 92.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 46 0.87% 93.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 10 0.19% 93.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 7 0.13% 93.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 7 0.13% 93.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 19 0.36% 94.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 3 0.06% 94.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 2 0.04% 94.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 2 0.04% 94.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 12 0.23% 94.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 1 0.02% 94.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 6 0.11% 94.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 29 0.55% 95.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 14 0.26% 95.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 2 0.04% 95.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 12 0.23% 95.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 164 3.09% 98.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 5 0.09% 99.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.02% 99.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.04% 99.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 3 0.06% 99.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.02% 99.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 4 0.08% 99.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 3 0.06% 99.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 8 0.15% 99.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 6 0.11% 99.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 12 0.23% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.02% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 3 0.06% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.02% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-171 1 0.02% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 3 0.06% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5316 # Writes before turning the bus around for reads
< system.physmem.totQLat 2156220500 # Total ticks spent queuing
< system.physmem.totMemAccLat 9750176750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2025055000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 5323.86 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5738 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5738 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 27.457825 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 20.746842 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 34.017596 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-23 4693 81.79% 81.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-31 187 3.26% 85.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-39 275 4.79% 89.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-47 67 1.17% 91.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-55 92 1.60% 92.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-63 47 0.82% 93.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-71 24 0.42% 93.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-79 11 0.19% 94.04% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-87 19 0.33% 94.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-95 7 0.12% 94.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-103 14 0.24% 94.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-111 6 0.10% 94.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-119 7 0.12% 94.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-127 4 0.07% 95.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-135 17 0.30% 95.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-143 47 0.82% 96.15% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-151 17 0.30% 96.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-159 17 0.30% 96.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-167 79 1.38% 98.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-175 32 0.56% 98.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-183 20 0.35% 99.02% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-191 19 0.33% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-199 15 0.26% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::200-207 7 0.12% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-215 4 0.07% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::216-223 3 0.05% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-231 1 0.02% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::232-239 3 0.05% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5738 # Writes before turning the bus around for reads
> system.physmem.totQLat 2167079250 # Total ticks spent queuing
> system.physmem.totMemAccLat 9757773000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2024185000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 5352.97 # Average queueing delay per DRAM burst
267,271c259,263
< system.physmem.avgMemAccLat 24073.86 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 4.02 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24102.97 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.75 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 5.35 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.75 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 5.42 # Average system write bandwidth in MiByte/s
273c265
< system.physmem.busUtil 0.14 # Data bus utilization in percentage
---
> system.physmem.busUtil 0.15 # Data bus utilization in percentage
275c267
< system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
---
> system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
277,285c269,277
< system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing
< system.physmem.readRowHits 364400 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95629 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.97 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes
< system.physmem.avgGap 3598228.45 # Average gap between requests
< system.physmem.pageHitRate 87.93 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 1774012993500 # Time in different power states
< system.physmem.memoryStateTime::REF 62884900000 # Time in different power states
---
> system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing
> system.physmem.readRowHits 364185 # Number of row buffer hits during reads
> system.physmem.writeRowHits 132456 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.96 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 84.06 # Row buffer hit rate for writes
> system.physmem.avgGap 3337080.57 # Average gap between requests
> system.physmem.pageHitRate 88.31 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 1774592996500 # Time in different power states
> system.physmem.memoryStateTime::REF 62918700000 # Time in different power states
287c279
< system.physmem.memoryStateTime::ACT 46323736500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 46722146000 # Time in different power states
289,455c281,303
< system.physmem.actEnergy::0 232613640 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 244724760 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 126922125 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 133530375 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 1579227000 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 1579858800 # Energy for read commands per rank (pJ)
< system.physmem.writeEnergy::0 380855520 # Energy for write commands per rank (pJ)
< system.physmem.writeEnergy::1 384808320 # Energy for write commands per rank (pJ)
< system.physmem.refreshEnergy::0 123002864400 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 123002864400 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 59595719580 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 60657122565 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1077656022750 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1076724967500 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1262574225015 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1262727876720 # Total energy per rank (pJ)
< system.physmem.averagePower::0 670.433163 # Core power per rank (mW)
< system.physmem.averagePower::1 670.514753 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 295760 # Transaction distribution
< system.membus.trans_dist::ReadResp 295744 # Transaction distribution
< system.membus.trans_dist::WriteReq 9618 # Transaction distribution
< system.membus.trans_dist::WriteResp 9618 # Transaction distribution
< system.membus.trans_dist::Writeback 76624 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 154 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 154 # Transaction distribution
< system.membus.trans_dist::ReadExReq 116541 # Transaction distribution
< system.membus.trans_dist::ReadExResp 116541 # Transaction distribution
< system.membus.trans_dist::BadAddressError 16 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887296 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920424 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1003716 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30835584 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30879892 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 33540180 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 158 # Total snoops (count)
< system.membus.snoop_fanout::samples 523708 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 523708 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
< system.membus.snoop_fanout::max_value 1 # Request fanout histogram
< system.membus.snoop_fanout::total 523708 # Request fanout histogram
< system.membus.reqLayer0.occupancy 30927500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer1.occupancy 1547261750 # Layer occupancy (ticks)
< system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
< system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks)
< system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3825161596 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
< system.membus.respLayer2.occupancy 43114249 # Layer occupancy (ticks)
< system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
< system.iocache.tags.replacements 41685 # number of replacements
< system.iocache.tags.tagsinuse 1.288180 # Cycle average of tags in use
< system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
< system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
< system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
< system.iocache.tags.warmup_cycle 1728025257000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.288180 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.080511 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.080511 # Average percentage of cache occupancy
< system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
< system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
< system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
< system.iocache.tags.tag_accesses 375525 # Number of tag accesses
< system.iocache.tags.data_accesses 375525 # Number of data accesses
< system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
< system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
< system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
< system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
< system.iocache.demand_misses::total 173 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
< system.iocache.overall_misses::total 173 # number of overall misses
< system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
< system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
< system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
< system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
< system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
< system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
< system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
< system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.iocache.blocked::no_targets 0 # number of cycles access was blocked
< system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.iocache.fast_writes 41552 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
< system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
< system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512658057 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512658057 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
< system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
< system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
< system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
< system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
< system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
< system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
< system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
< system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
< system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
< system.disk0.dma_write_txs 395 # Number of DMA write transactions.
< system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
< system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
< system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
< system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
< system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
< system.disk2.dma_write_txs 1 # Number of DMA write transactions.
< system.cpu.branchPred.lookups 14964931 # Number of BP lookups
< system.cpu.branchPred.condPredicted 12983118 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 374694 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9691016 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 5184483 # Number of BTB hits
---
> system.physmem.actEnergy::0 242668440 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 254394000 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 132408375 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 138806250 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 1578704400 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 1579024200 # Energy for read commands per rank (pJ)
> system.physmem.writeEnergy::0 506645280 # Energy for write commands per rank (pJ)
> system.physmem.writeEnergy::1 514298160 # Energy for write commands per rank (pJ)
> system.physmem.refreshEnergy::0 123068977200 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 123068977200 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 59931006120 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 60719870160 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1077969239250 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1077277253250 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1263429649065 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1263552623220 # Total energy per rank (pJ)
> system.physmem.averagePower::0 670.526996 # Core power per rank (mW)
> system.physmem.averagePower::1 670.592261 # Core power per rank (mW)
> system.cpu.branchPred.lookups 15011318 # Number of BP lookups
> system.cpu.branchPred.condPredicted 13019220 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 376037 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9980368 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 5204970 # Number of BTB hits
457,459c305,307
< system.cpu.branchPred.BTBHitPct 53.497827 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 807557 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 32108 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 52.152085 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 808971 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 32603 # Number of incorrect RAS predictions.
465,466c313,314
< system.cpu.dtb.read_hits 9237824 # DTB read hits
< system.cpu.dtb.read_misses 17804 # DTB read misses
---
> system.cpu.dtb.read_hits 9241438 # DTB read hits
> system.cpu.dtb.read_misses 17791 # DTB read misses
468,470c316,318
< system.cpu.dtb.read_accesses 766148 # DTB read accesses
< system.cpu.dtb.write_hits 6384867 # DTB write hits
< system.cpu.dtb.write_misses 2306 # DTB write misses
---
> system.cpu.dtb.read_accesses 766265 # DTB read accesses
> system.cpu.dtb.write_hits 6385998 # DTB write hits
> system.cpu.dtb.write_misses 2317 # DTB write misses
472,474c320,322
< system.cpu.dtb.write_accesses 298467 # DTB write accesses
< system.cpu.dtb.data_hits 15622691 # DTB hits
< system.cpu.dtb.data_misses 20110 # DTB misses
---
> system.cpu.dtb.write_accesses 298404 # DTB write accesses
> system.cpu.dtb.data_hits 15627436 # DTB hits
> system.cpu.dtb.data_misses 20108 # DTB misses
476,480c324,328
< system.cpu.dtb.data_accesses 1064615 # DTB accesses
< system.cpu.itb.fetch_hits 3999749 # ITB hits
< system.cpu.itb.fetch_misses 6851 # ITB misses
< system.cpu.itb.fetch_acv 647 # ITB acv
< system.cpu.itb.fetch_accesses 4006600 # ITB accesses
---
> system.cpu.dtb.data_accesses 1064669 # DTB accesses
> system.cpu.itb.fetch_hits 4019003 # ITB hits
> system.cpu.itb.fetch_misses 6884 # ITB misses
> system.cpu.itb.fetch_acv 661 # ITB acv
> system.cpu.itb.fetch_accesses 4025887 # ITB accesses
493c341
< system.cpu.numCycles 174888375 # number of cpu cycles simulated
---
> system.cpu.numCycles 175285694 # number of cpu cycles simulated
496,502c344,350
< system.cpu.committedInsts 56120453 # Number of instructions committed
< system.cpu.committedOps 56120453 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 2530516 # Number of ops (including micro ops) which were discarded before commit
< system.cpu.numFetchSuspends 5527 # Number of times Execute suspended instruction fetching
< system.cpu.quiesceCycles 3591560318 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 3.116304 # CPI: cycles per instruction
< system.cpu.ipc 0.320893 # IPC: instructions per cycle
---
> system.cpu.committedInsts 56124126 # Number of instructions committed
> system.cpu.committedOps 56124126 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 2495853 # Number of ops (including micro ops) which were discarded before commit
> system.cpu.numFetchSuspends 5575 # Number of times Execute suspended instruction fetching
> system.cpu.quiesceCycles 3593196852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 3.123179 # CPI: cycles per instruction
> system.cpu.ipc 0.320187 # IPC: instructions per cycle
504,506c352,354
< system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211459 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 211480 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74791 40.94% 40.94% # number of times we switched to this ipl
508,511c356,359
< system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 105855 57.95% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182673 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 105868 57.95% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182691 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73424 49.32% 49.32% # number of times we switched to this ipl from a different ipl
513,521c361,369
< system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 148871 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1832868777500 97.33% 97.33% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 80360500 0.00% 97.33% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 672864500 0.04% 97.37% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 49601349000 2.63% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1883223351500 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73424 49.32% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 148880 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1833816082000 97.32% 97.32% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 80474500 0.00% 97.33% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 673053000 0.04% 97.36% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 49670669500 2.64% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1884240279000 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl
524,525c372,373
< system.cpu.kern.ipl_used::31 0.693590 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814959 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.693543 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814928 # fraction of swpipl calls that actually changed the ipl
561c409
< system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
---
> system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
564,566c412,414
< system.cpu.kern.callpal::swpipl 175516 91.23% 93.43% # number of callpals executed
< system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed
< system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175532 91.22% 93.43% # number of callpals executed
> system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed
> system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
570c418
< system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed
---
> system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed
573,575c421,423
< system.cpu.kern.callpal::total 192398 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5867 # number of protection mode switches
< system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
---
> system.cpu.kern.callpal::total 192418 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5870 # number of protection mode switches
> system.cpu.kern.mode_switch::user 1743 # number of protection mode switches
577,580c425,428
< system.cpu.kern.mode_good::kernel 1910
< system.cpu.kern.mode_good::user 1741
< system.cpu.kern.mode_good::idle 169
< system.cpu.kern.mode_switch_good::kernel 0.325550 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_good::kernel 1913
> system.cpu.kern.mode_good::user 1743
> system.cpu.kern.mode_good::idle 170
> system.cpu.kern.mode_switch_good::kernel 0.325894 # fraction of useful protection mode switches
582,620c430,871
< system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 36222818500 1.92% 1.92% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 4061127000 0.22% 2.14% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1842939396000 97.86% 100.00% # number of ticks spent at the given mode
< system.cpu.kern.swap_context 4175 # number of times the context was actually changed
< system.cpu.tickCycles 83840328 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 91048047 # Total number of cycles that the object has spent stopped
< system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
< system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
< system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
< system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
< system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
< system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
< system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
< system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
< system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
< system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
< system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
< system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
< system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
< system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
< system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
< system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
< system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
< system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
< system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
< system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
< system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
< system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
< system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
< system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
< system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
< system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
< system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
< system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
< system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
< system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
< system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
---
> system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.393986 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 36270859500 1.92% 1.92% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 4083023000 0.22% 2.14% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1843886386500 97.86% 100.00% # number of ticks spent at the given mode
> system.cpu.kern.swap_context 4177 # number of times the context was actually changed
> system.cpu.tickCycles 84485847 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 90799847 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 1395229 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.982334 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 13773041 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1395741 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 9.867906 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982334 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 63657366 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63657366 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 7814636 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7814636 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 5576637 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5576637 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182736 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 182736 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.inst 198999 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.inst 13391273 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13391273 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 13391273 # number of overall hits
> system.cpu.dcache.overall_hits::total 13391273 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.inst 1201532 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1201532 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.inst 573582 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 573582 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17284 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17284 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.inst 1775114 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1775114 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 1775114 # number of overall misses
> system.cpu.dcache.overall_misses::total 1775114 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31036730750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 31036730750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20700048539 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 20700048539 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231020000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 231020000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 51736779289 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 51736779289 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 51736779289 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 51736779289 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 9016168 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9016168 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.inst 6150219 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6150219 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200020 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200020 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198999 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.inst 15166387 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15166387 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 15166387 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15166387 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133264 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.133264 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093262 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.093262 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086411 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086411 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.117043 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.117043 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.117043 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.117043 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25830.964760 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 25830.964760 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36089.083233 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 36089.083233 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13366.118954 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.118954 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29145.609403 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29145.609403 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29145.609403 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 29145.609403 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 838115 # number of writebacks
> system.cpu.dcache.writebacks::total 838115 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127210 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 127210 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269406 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 269406 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.inst 396616 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 396616 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 396616 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 396616 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074322 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1074322 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304176 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304176 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17281 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17281 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.inst 1378498 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1378498 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.inst 1378498 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1378498 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26919627250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 26919627250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10259801597 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10259801597 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196291500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196291500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179428847 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 37179428847 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179428847 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 37179428847 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423887000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423887000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002910000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002910000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426797000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426797000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119155 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119155 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049458 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049458 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086396 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086396 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090892 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.090892 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090892 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.090892 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25057.317313 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25057.317313 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33729.819568 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33729.819568 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11358.804467 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11358.804467 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26970.970467 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26970.970467 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26970.970467 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26970.970467 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.icache.tags.replacements 1458001 # number of replacements
> system.cpu.icache.tags.tagsinuse 509.626489 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 18970775 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1458512 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 13.006938 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 31607473250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 509.626489 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.995364 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.995364 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 21888154 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 21888154 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 18970778 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 18970778 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 18970778 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 18970778 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 18970778 # number of overall hits
> system.cpu.icache.overall_hits::total 18970778 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1458688 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1458688 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1458688 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1458688 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1458688 # number of overall misses
> system.cpu.icache.overall_misses::total 1458688 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 20029373869 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 20029373869 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 20029373869 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 20029373869 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 20029373869 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 20029373869 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 20429466 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 20429466 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 20429466 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 20429466 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 20429466 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 20429466 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071401 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.071401 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.071401 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.071401 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.071401 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.071401 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13731.088395 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13731.088395 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13731.088395 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13731.088395 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13731.088395 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13731.088395 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.icache.fast_writes 0 # number of fast writes performed
> system.cpu.icache.cache_copies 0 # number of cache copies performed
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458688 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1458688 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1458688 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1458688 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1458688 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1458688 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17104729131 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 17104729131 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17104729131 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 17104729131 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17104729131 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 17104729131 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071401 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.071401 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.071401 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11726.105330 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11726.105330 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11726.105330 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11726.105330 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11726.105330 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11726.105330 # average overall mshr miss latency
> system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.l2cache.tags.replacements 339435 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65326.200893 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2981535 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 404597 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 7.369148 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 5873248750 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 54494.769777 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 10831.431116 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.831524 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165275 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996799 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1458 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5147 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2791 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55536 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 30249203 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 30249203 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 2261508 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2261508 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 838115 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 838115 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.inst 187530 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187530 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 2449038 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2449038 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 2449038 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2449038 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 288693 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 288693 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.inst 116655 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116655 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 405348 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 405348 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 405348 # number of overall misses
> system.cpu.l2cache.overall_misses::total 405348 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18932535000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 18932535000 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 214497 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 214497 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8075894612 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8075894612 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27008429612 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 27008429612 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27008429612 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 27008429612 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 2550201 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2550201 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 838115 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 838115 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304185 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304185 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 2854386 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2854386 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 2854386 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2854386 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113204 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.113204 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383500 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383500 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142009 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.142009 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142009 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.142009 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65580.166474 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 65580.166474 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 12617.470588 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12617.470588 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69228.876705 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69228.876705 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66630.227883 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 66630.227883 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66630.227883 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 66630.227883 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.l2cache.fast_writes 0 # number of fast writes performed
> system.cpu.l2cache.cache_copies 0 # number of cache copies performed
> system.cpu.l2cache.writebacks::writebacks 76635 # number of writebacks
> system.cpu.l2cache.writebacks::total 76635 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288693 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 288693 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116655 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116655 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 405348 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 405348 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 405348 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 405348 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15323296500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15323296500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 271014 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271014 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6608324888 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6608324888 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21931621388 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 21931621388 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21931621388 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 21931621388 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333779000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333779000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887481500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887481500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221260500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221260500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113204 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113204 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383500 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383500 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.142009 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.142009 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53078.171275 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53078.171275 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15942 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56648.449599 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56648.449599 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54105.660785 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54105.660785 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54105.660785 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54105.660785 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.toL2Bus.trans_dist::ReadReq 2557364 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2557331 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 838115 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 304185 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 304185 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917316 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662927 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 6580243 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352192 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143021148 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 236373340 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 41941 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3734307 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.011173 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.105112 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3692582 98.88% 98.88% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 41725 1.12% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3734307 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2697490998 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
> system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 2191666369 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 2194528153 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
> system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
> system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
> system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
> system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
> system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
> system.disk0.dma_write_txs 395 # Number of DMA write transactions.
> system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
> system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
> system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
> system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
> system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
> system.disk2.dma_write_txs 1 # Number of DMA write transactions.
623,625c874,877
< system.iobus.trans_dist::WriteReq 51170 # Transaction distribution
< system.iobus.trans_dist::WriteResp 51170 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::WriteReq 51171 # Transaction distribution
> system.iobus.trans_dist::WriteResp 9619 # Transaction distribution
> system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes)
637c889
< system.iobus.pkt_count_system.bridge.master::total 33096 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes)
640,641c892,893
< system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes)
653c905
< system.iobus.pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes)
656,657c908,909
< system.iobus.pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks)
679c931
< system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 406196790 # Layer occupancy (ticks)
683c935
< system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks)
685c937
< system.iobus.respLayer1.occupancy 42013751 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks)
687,1108c939,1113
< system.cpu.icache.tags.replacements 1457910 # number of replacements
< system.cpu.icache.tags.tagsinuse 509.626980 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 18940924 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1458421 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 12.987281 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 31560714250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 509.626980 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.995365 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.995365 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 21858119 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 21858119 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 18940927 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 18940927 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 18940927 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 18940927 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 18940927 # number of overall hits
< system.cpu.icache.overall_hits::total 18940927 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1458596 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1458596 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1458596 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1458596 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1458596 # number of overall misses
< system.cpu.icache.overall_misses::total 1458596 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 20022164568 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 20022164568 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 20022164568 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 20022164568 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 20022164568 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 20022164568 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 20399523 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 20399523 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 20399523 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 20399523 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 20399523 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 20399523 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071501 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.071501 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.071501 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.071501 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.071501 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.071501 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.011844 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13727.011844 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13727.011844 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13727.011844 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458596 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1458596 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1458596 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1458596 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1458596 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1458596 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097663432 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 17097663432 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097663432 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 17097663432 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097663432 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 17097663432 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071501 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.071501 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.071501 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.000768 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.000768 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.toL2Bus.trans_dist::ReadReq 2557139 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2557106 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 838111 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 304253 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 304253 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917133 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662791 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 6579924 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93346368 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143016724 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 236363092 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 41947 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3734153 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.011176 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.105123 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 3692421 98.88% 98.88% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 41732 1.12% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 3734153 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2697404999 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
< system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 2191548568 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 2194491404 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
< system.cpu.l2cache.tags.replacements 339424 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65327.181695 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2981337 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 404586 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 7.368859 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 54492.967363 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 10834.214332 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.831497 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165317 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996814 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1457 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5166 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2781 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 30247978 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 30247978 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 2261320 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2261320 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 838111 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 838111 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.inst 187575 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187575 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 2448895 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2448895 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 2448895 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2448895 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 288657 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 288657 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.inst 116678 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116678 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 405335 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 405335 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 405335 # number of overall misses
< system.cpu.l2cache.overall_misses::total 405335 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18918279000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 18918279000 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 115495 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 115495 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8105432113 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8105432113 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 27023711113 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 27023711113 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 27023711113 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 27023711113 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 2549977 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2549977 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 838111 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 838111 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304253 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304253 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 2854230 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2854230 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 2854230 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2854230 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113200 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.113200 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383490 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383490 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142012 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.142012 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142012 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.142012 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65538.958002 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 65538.958002 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 6793.823529 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6793.823529 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69468.384040 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69468.384040 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 66670.065780 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 66670.065780 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
< system.cpu.l2cache.writebacks::writebacks 76624 # number of writebacks
< system.cpu.l2cache.writebacks::total 76624 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288657 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 288657 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116678 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116678 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 405335 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 405335 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 405335 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 405335 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15309425000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15309425000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 170516 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 170516 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6604759387 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6604759387 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21914184387 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 21914184387 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21914184387 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 21914184387 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333304000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333304000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1888377500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1888377500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221681500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221681500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113200 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113200 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383490 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383490 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.142012 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.142012 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53036.735641 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53036.735641 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10030.352941 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.352941 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56606.724378 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56606.724378 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.dcache.tags.replacements 1395163 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.982303 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 13764370 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1395675 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 9.862160 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982303 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 63622669 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63622669 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 7806418 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7806418 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 5576177 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5576177 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182756 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 182756 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.inst 198986 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 198986 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.inst 13382595 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13382595 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 13382595 # number of overall hits
< system.cpu.dcache.overall_hits::total 13382595 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.inst 1201460 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1201460 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.inst 573699 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 573699 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17252 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17252 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.inst 1775159 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1775159 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 1775159 # number of overall misses
< system.cpu.dcache.overall_misses::total 1775159 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31026314750 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 31026314750 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20775588791 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 20775588791 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 230892000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 230892000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 51801903541 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 51801903541 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 51801903541 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 51801903541 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 9007878 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9007878 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.inst 6149876 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6149876 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200008 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200008 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198986 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 198986 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.inst 15157754 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15157754 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 15157754 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15157754 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133379 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.133379 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093286 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.093286 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086257 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086257 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.117112 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.117112 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.117112 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.117112 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25823.843282 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 25823.843282 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36213.395511 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 36213.395511 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13383.491769 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13383.491769 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29181.556999 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 29181.556999 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 838111 # number of writebacks
< system.cpu.dcache.writebacks::total 838111 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127232 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 127232 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269462 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 269462 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.inst 396694 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 396694 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 396694 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 396694 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074228 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1074228 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304237 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304237 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17249 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.inst 1378465 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1378465 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.inst 1378465 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1378465 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26911701750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 26911701750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10289625346 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10289625346 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196226500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196226500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37201327096 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 37201327096 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37201327096 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 37201327096 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423395500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423395500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2003794000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2003794000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3427189500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3427189500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119254 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119254 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049470 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086242 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086242 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.090941 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.090941 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25052.132089 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25052.132089 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33821.084700 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33821.084700 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11376.108760 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.108760 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.tags.replacements 41685 # number of replacements
> system.iocache.tags.tagsinuse 1.296059 # Cycle average of tags in use
> system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
> system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
> system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
> system.iocache.tags.warmup_cycle 1728026020000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.296059 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.081004 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.081004 # Average percentage of cache occupancy
> system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
> system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
> system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
> system.iocache.tags.tag_accesses 375525 # Number of tag accesses
> system.iocache.tags.data_accesses 375525 # Number of data accesses
> system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
> system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
> system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
> system.iocache.demand_misses::total 173 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
> system.iocache.overall_misses::total 173 # number of overall misses
> system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635314907 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 13635314907 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
> system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
> system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
> system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
> system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
> system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
> system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
> system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328150.628297 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 328150.628297 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 206297 # number of cycles access was blocked
> system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.iocache.blocked::no_mshrs 23564 # number of cycles access was blocked
> system.iocache.blocked::no_targets 0 # number of cycles access was blocked
> system.iocache.avg_blocked_cycles::no_mshrs 8.754753 # average number of cycles each access was blocked
> system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.iocache.fast_writes 0 # number of fast writes performed
> system.iocache.cache_copies 0 # number of cache copies performed
> system.iocache.writebacks::writebacks 41512 # number of writebacks
> system.iocache.writebacks::total 41512 # number of writebacks
> system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
> system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
> system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
> system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474610907 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474610907 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
> system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
> system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
> system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
> system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
> system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
> system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276150.628297 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276150.628297 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
> system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.membus.trans_dist::ReadReq 295796 # Transaction distribution
> system.membus.trans_dist::ReadResp 295780 # Transaction distribution
> system.membus.trans_dist::WriteReq 9619 # Transaction distribution
> system.membus.trans_dist::WriteResp 9619 # Transaction distribution
> system.membus.trans_dist::Writeback 118147 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 155 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 155 # Transaction distribution
> system.membus.trans_dist::ReadExReq 116517 # Transaction distribution
> system.membus.trans_dist::ReadExResp 116517 # Transaction distribution
> system.membus.trans_dist::BadAddressError 16 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887058 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920188 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1044992 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819584 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30863900 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 36180956 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 433 # Total snoops (count)
> system.membus.snoop_fanout::samples 565237 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 565237 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 565237 # Request fanout histogram
> system.membus.reqLayer0.occupancy 30298500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer1.occupancy 1878232500 # Layer occupancy (ticks)
> system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
> system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks)
> system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer1.occupancy 3792450097 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
> system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks)
> system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
> system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
> system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
> system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
> system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
> system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
> system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
> system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
> system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
> system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
> system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
> system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
> system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
> system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
> system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
> system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
> system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
> system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
> system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
> system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
> system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
> system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
> system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
> system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
> system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
> system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
> system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
> system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
> system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
> system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
> system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
> system.tsunami.ethernet.droppedPackets 0 # number of packets dropped