7,11c7,11
< host_inst_rate 293967 # Simulator instruction rate (inst/s)
< host_op_rate 293967 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 9864607727 # Simulator tick rate (ticks/s)
< host_mem_usage 317632 # Number of bytes of host memory used
< host_seconds 190.91 # Real time elapsed on the host
---
> host_inst_rate 279379 # Simulator instruction rate (inst/s)
> host_op_rate 279379 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9375076807 # Simulator tick rate (ticks/s)
> host_mem_usage 311380 # Number of bytes of host memory used
> host_seconds 200.88 # Real time elapsed on the host
412,413d411
< system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
< system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
428,429d425
< system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
436,437c432,433
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60470.207379 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60470.207379 # average WriteInvalidateReq mshr miss latency
---
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency