4,5c4,5
< sim_ticks 1883223940000 # Number of ticks simulated
< final_tick 1883223940000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 1883224346500 # Number of ticks simulated
> final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 180615 # Simulator instruction rate (inst/s)
< host_op_rate 180615 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 6060637883 # Simulator tick rate (ticks/s)
< host_mem_usage 316396 # Number of bytes of host memory used
< host_seconds 310.73 # Real time elapsed on the host
< sim_insts 56122642 # Number of instructions simulated
< sim_ops 56122642 # Number of ops (including micro ops) simulated
---
> host_inst_rate 283997 # Simulator instruction rate (inst/s)
> host_op_rate 283997 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9530044697 # Simulator tick rate (ticks/s)
> host_mem_usage 369276 # Number of bytes of host memory used
> host_seconds 197.61 # Real time elapsed on the host
> sim_insts 56120453 # Number of instructions simulated
> sim_ops 56120453 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::cpu.inst 25930944 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 25931648 # Number of bytes read from this memory
18,21c18,21
< system.physmem.bytes_read::total 25931904 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4902720 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 25932608 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4903936 # Number of bytes written to this memory
23,24c23,24
< system.physmem.bytes_written::total 7562048 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 405171 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 7563264 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 405182 # Number of read requests responded to by this memory
26,27c26,27
< system.physmem.num_reads::total 405186 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 76605 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 405197 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 76624 # Number of write requests responded to by this memory
29,30c29,30
< system.physmem.num_writes::total 118157 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 13769443 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 118176 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 13769813 # Total read bandwidth from this memory (bytes/s)
32,39c32,39
< system.physmem.bw_read::total 13769952 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 558905 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 558905 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2603365 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::tsunami.ide 1412115 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4015480 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2603365 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 13769443 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 13770323 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 559041 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 559041 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2604011 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::tsunami.ide 1412114 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4016125 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2604011 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 13769813 # Total bandwidth to/from this memory (bytes/s)
41,51c41,51
< system.physmem.bw_total::total 17785432 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 405186 # Number of read requests accepted
< system.physmem.writeReqs 118157 # Number of write requests accepted
< system.physmem.readBursts 405186 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 118157 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25919424 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7560064 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25931904 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7562048 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 17786448 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 405197 # Number of read requests accepted
> system.physmem.writeReqs 118176 # Number of write requests accepted
> system.physmem.readBursts 405197 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 118176 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25920704 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 11904 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7562112 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25932608 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7563264 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 186 # Number of DRAM read bursts serviced by the write queue
53,56c53,56
< system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 25480 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25741 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25855 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 25484 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25740 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25857 # Per bank write bursts
58,60c58,60
< system.physmem.perBankRdBursts::4 25233 # Per bank write bursts
< system.physmem.perBankRdBursts::5 24956 # Per bank write bursts
< system.physmem.perBankRdBursts::6 24811 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 25237 # Per bank write bursts
> system.physmem.perBankRdBursts::5 24959 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24814 # Per bank write bursts
63,64c63,64
< system.physmem.perBankRdBursts::9 25280 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25532 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 25284 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25531 # Per bank write bursts
66,68c66,68
< system.physmem.perBankRdBursts::12 24547 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25588 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25870 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 24549 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25592 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25866 # Per bank write bursts
71c71
< system.physmem.perBankWrBursts::1 7677 # Per bank write bursts
---
> system.physmem.perBankWrBursts::1 7680 # Per bank write bursts
73,81c73,81
< system.physmem.perBankWrBursts::3 7744 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7318 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6954 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6788 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6406 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7235 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6889 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7393 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6865 # Per bank write bursts
---
> system.physmem.perBankWrBursts::3 7745 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7320 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6957 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6792 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6401 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7236 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6892 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7391 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6866 # Per bank write bursts
83c83
< system.physmem.perBankWrBursts::13 8007 # Per bank write bursts
---
> system.physmem.perBankWrBursts::13 8010 # Per bank write bursts
85c85
< system.physmem.perBankWrBursts::15 7937 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 7955 # Per bank write bursts
87,88c87,88
< system.physmem.numWrRetry 5 # Number of times write queue was full causing retry
< system.physmem.totGap 1883215178500 # Total gap between requests
---
> system.physmem.numWrRetry 7 # Number of times write queue was full causing retry
> system.physmem.totGap 1883215617500 # Total gap between requests
95c95
< system.physmem.readPktSize::6 405186 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 405197 # Read request sizes (log2)
102,105c102,105
< system.physmem.writePktSize::6 118157 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 402670 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2243 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 118176 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 402689 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2242 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see
150,216c150,216
< system.physmem.wrQLenPdf::15 1541 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2210 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5693 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5920 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6144 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6907 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7208 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8700 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8384 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8515 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7009 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6582 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5776 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5533 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5557 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5513 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 225 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 112 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 178 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 193 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 184 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 173 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 123 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 108 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 62955 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 531.800302 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 324.503879 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 415.177975 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14434 22.93% 22.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 10626 16.88% 39.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4984 7.92% 47.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3035 4.82% 52.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2479 3.94% 56.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2063 3.28% 59.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1365 2.17% 61.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1615 2.57% 64.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 22354 35.51% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 62955 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5310 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 76.265725 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2898.384419 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5307 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1502 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2155 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5922 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8341 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 8743 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8450 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8575 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6692 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5817 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5536 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5545 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5502 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 186 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 168 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 96 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 94 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 125 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 63140 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 530.294837 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 322.585016 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 415.640457 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14650 23.20% 23.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 10589 16.77% 39.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5075 8.04% 48.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3003 4.76% 52.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2370 3.75% 56.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2105 3.33% 59.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1364 2.16% 62.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1607 2.55% 64.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 22377 35.44% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63140 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5316 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 76.186983 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2896.748549 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5313 99.94% 99.94% # Reads before turning the bus around for writes
220,258c220,259
< system.physmem.rdPerTurnAround::total 5310 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5310 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.245951 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.963647 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 20.434666 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 4660 87.76% 87.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 16 0.30% 88.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 15 0.28% 88.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 227 4.27% 92.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 38 0.72% 93.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 5 0.09% 93.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 8 0.15% 93.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 6 0.11% 93.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 26 0.49% 94.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 4 0.08% 94.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 5 0.09% 94.35% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 14 0.26% 94.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 2 0.04% 94.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 5 0.09% 94.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 26 0.49% 95.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 9 0.17% 95.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 5 0.09% 95.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 6 0.11% 95.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 182 3.43% 99.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 6 0.11% 99.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.02% 99.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.04% 99.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 3 0.06% 99.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 6 0.11% 99.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 5 0.09% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 4 0.08% 99.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 2 0.04% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 7 0.13% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.02% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 5 0.09% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 2 0.04% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 5316 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5316 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.226862 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.933757 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 20.590348 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 4662 87.70% 87.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 15 0.28% 87.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 21 0.40% 88.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 225 4.23% 92.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 46 0.87% 93.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 10 0.19% 93.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 7 0.13% 93.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 7 0.13% 93.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 19 0.36% 94.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 3 0.06% 94.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 2 0.04% 94.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 2 0.04% 94.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 12 0.23% 94.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 1 0.02% 94.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 6 0.11% 94.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 29 0.55% 95.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 14 0.26% 95.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 2 0.04% 95.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 12 0.23% 95.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 164 3.09% 98.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 5 0.09% 99.02% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.02% 99.04% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 2 0.04% 99.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 3 0.06% 99.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.02% 99.15% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 4 0.08% 99.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 3 0.06% 99.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 8 0.15% 99.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 6 0.11% 99.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 12 0.23% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 1 0.02% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 3 0.06% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 1 0.02% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-171 1 0.02% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 3 0.06% 99.94% # Writes before turning the bus around for reads
260,264c261,265
< system.physmem.wrPerTurnAround::total 5310 # Writes before turning the bus around for reads
< system.physmem.totQLat 2131293750 # Total ticks spent queuing
< system.physmem.totMemAccLat 9724875000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2024955000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 5262.57 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 5316 # Writes before turning the bus around for reads
> system.physmem.totQLat 2156220500 # Total ticks spent queuing
> system.physmem.totMemAccLat 9750176750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2025055000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 5323.86 # Average queueing delay per DRAM burst
266c267
< system.physmem.avgMemAccLat 24012.57 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 24073.86 # Average memory access latency per DRAM burst
268c269
< system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s
---
> system.physmem.avgWrBW 4.02 # Average achieved write bandwidth in MiByte/s
276,283c277,284
< system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing
< system.physmem.readRowHits 364467 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95695 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.99 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 80.99 # Row buffer hit rate for writes
< system.physmem.avgGap 3598433.87 # Average gap between requests
< system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 1774121817500 # Time in different power states
---
> system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing
> system.physmem.readRowHits 364400 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95629 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.97 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes
> system.physmem.avgGap 3598228.45 # Average gap between requests
> system.physmem.pageHitRate 87.93 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 1774012993500 # Time in different power states
286c287
< system.physmem.memoryStateTime::ACT 46214912500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 46323736500 # Time in different power states
288,290c289,290
< system.membus.throughput 17814330 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 295751 # Transaction distribution
< system.membus.trans_dist::ReadResp 295735 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 295760 # Transaction distribution
> system.membus.trans_dist::ReadResp 295744 # Transaction distribution
293c293
< system.membus.trans_dist::Writeback 76605 # Transaction distribution
---
> system.membus.trans_dist::Writeback 76624 # Transaction distribution
296,299c296,299
< system.membus.trans_dist::UpgradeReq 157 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 157 # Transaction distribution
< system.membus.trans_dist::ReadExReq 116539 # Transaction distribution
< system.membus.trans_dist::ReadExResp 116539 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 154 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 154 # Transaction distribution
> system.membus.trans_dist::ReadExReq 116541 # Transaction distribution
> system.membus.trans_dist::ReadExResp 116541 # Transaction distribution
302c302
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887261 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887296 # Packet count per connected master and slave (bytes)
304c304
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920389 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920424 # Packet count per connected master and slave (bytes)
307,316c307,326
< system.membus.pkt_count::total 1003681 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30833664 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30877972 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 33538260 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 33538260 # Total data (bytes)
< system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 29840000 # Layer occupancy (ticks)
---
> system.membus.pkt_count::total 1003716 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30835584 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30879892 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 33540180 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 158 # Total snoops (count)
> system.membus.snoop_fanout::samples 523708 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 523708 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 523708 # Request fanout histogram
> system.membus.reqLayer0.occupancy 30927500 # Layer occupancy (ticks)
318c328
< system.membus.reqLayer1.occupancy 1547069500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1547261750 # Layer occupancy (ticks)
320c330
< system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks)
322c332
< system.membus.respLayer1.occupancy 3825068843 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 3825161596 # Layer occupancy (ticks)
324c334
< system.membus.respLayer2.occupancy 43112000 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 43114249 # Layer occupancy (ticks)
327c337
< system.iocache.tags.tagsinuse 1.288165 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.288180 # Cycle average of tags in use
331,334c341,344
< system.iocache.tags.warmup_cycle 1728026235000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.288165 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.080510 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.080510 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1728025257000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.288180 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.080511 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.080511 # Average percentage of cache occupancy
338,339c348,349
< system.iocache.tags.tag_accesses 375533 # Number of tag accesses
< system.iocache.tags.data_accesses 375533 # Number of data accesses
---
> system.iocache.tags.tag_accesses 375525 # Number of tag accesses
> system.iocache.tags.data_accesses 375525 # Number of data accesses
344,345d353
< system.iocache.WriteInvalidateReq_misses::tsunami.ide 1 # number of WriteInvalidateReq misses
< system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses
350,355c358,363
< system.iocache.ReadReq_miss_latency::tsunami.ide 21132383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21132383 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 21132383 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21132383 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21132383 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21132383 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
358,359c366,367
< system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41553 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::total 41553 # number of WriteInvalidateReq accesses(hits+misses)
---
> system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
366,367d373
< system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000024 # miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_miss_rate::total 0.000024 # miss rate for WriteInvalidateReq accesses
372,377c378,383
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122152.502890 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 122152.502890 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 122152.502890 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 122152.502890 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
394,401c400,407
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12135383 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12135383 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2514597305 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2514597305 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 12135383 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 12135383 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 12135383 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 12135383 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512658057 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512658057 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
404,405c410,411
< system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999976 # mshr miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999976 # mshr miss rate for WriteInvalidateReq accesses
---
> system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
410,417c416,423
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 70146.722543 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60516.877768 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60516.877768 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60470.207379 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60470.207379 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
431,435c437,441
< system.cpu.branchPred.lookups 14964215 # Number of BP lookups
< system.cpu.branchPred.condPredicted 12981470 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 376025 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 10003487 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 5188980 # Number of BTB hits
---
> system.cpu.branchPred.lookups 14964931 # Number of BP lookups
> system.cpu.branchPred.condPredicted 12983118 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 374694 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9691016 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 5184483 # Number of BTB hits
437,439c443,445
< system.cpu.branchPred.BTBHitPct 51.871712 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 807651 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 32040 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 53.497827 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 807557 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 32108 # Number of incorrect RAS predictions.
445,446c451,452
< system.cpu.dtb.read_hits 9238395 # DTB read hits
< system.cpu.dtb.read_misses 17814 # DTB read misses
---
> system.cpu.dtb.read_hits 9237824 # DTB read hits
> system.cpu.dtb.read_misses 17804 # DTB read misses
448,450c454,456
< system.cpu.dtb.read_accesses 766068 # DTB read accesses
< system.cpu.dtb.write_hits 6385066 # DTB write hits
< system.cpu.dtb.write_misses 2311 # DTB write misses
---
> system.cpu.dtb.read_accesses 766148 # DTB read accesses
> system.cpu.dtb.write_hits 6384867 # DTB write hits
> system.cpu.dtb.write_misses 2306 # DTB write misses
452,454c458,460
< system.cpu.dtb.write_accesses 298441 # DTB write accesses
< system.cpu.dtb.data_hits 15623461 # DTB hits
< system.cpu.dtb.data_misses 20125 # DTB misses
---
> system.cpu.dtb.write_accesses 298467 # DTB write accesses
> system.cpu.dtb.data_hits 15622691 # DTB hits
> system.cpu.dtb.data_misses 20110 # DTB misses
456,460c462,466
< system.cpu.dtb.data_accesses 1064509 # DTB accesses
< system.cpu.itb.fetch_hits 4000795 # ITB hits
< system.cpu.itb.fetch_misses 6874 # ITB misses
< system.cpu.itb.fetch_acv 703 # ITB acv
< system.cpu.itb.fetch_accesses 4007669 # ITB accesses
---
> system.cpu.dtb.data_accesses 1064615 # DTB accesses
> system.cpu.itb.fetch_hits 3999749 # ITB hits
> system.cpu.itb.fetch_misses 6851 # ITB misses
> system.cpu.itb.fetch_acv 647 # ITB acv
> system.cpu.itb.fetch_accesses 4006600 # ITB accesses
473c479
< system.cpu.numCycles 176776474 # number of cpu cycles simulated
---
> system.cpu.numCycles 174888375 # number of cpu cycles simulated
476,482c482,488
< system.cpu.committedInsts 56122642 # Number of instructions committed
< system.cpu.committedOps 56122642 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 2532635 # Number of ops (including micro ops) which were discarded before commit
< system.cpu.numFetchSuspends 5494 # Number of times Execute suspended instruction fetching
< system.cpu.quiesceCycles 3591582755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 3.149825 # CPI: cycles per instruction
< system.cpu.ipc 0.317478 # IPC: instructions per cycle
---
> system.cpu.committedInsts 56120453 # Number of instructions committed
> system.cpu.committedOps 56120453 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 2530516 # Number of ops (including micro ops) which were discarded before commit
> system.cpu.numFetchSuspends 5527 # Number of times Execute suspended instruction fetching
> system.cpu.quiesceCycles 3591560318 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 3.116304 # CPI: cycles per instruction
> system.cpu.ipc 0.320893 # IPC: instructions per cycle
484,486c490,492
< system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211451 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74783 40.94% 40.94% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 211459 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl
489,491c495,497
< system.cpu.kern.ipl_count::31 105851 57.95% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182665 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73416 49.32% 49.32% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::31 105855 57.95% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182673 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl
494,501c500,507
< system.cpu.kern.ipl_good::31 73416 49.32% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1832860357500 97.33% 97.33% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 80169000 0.00% 97.33% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 672803000 0.04% 97.37% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 49609630000 2.63% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1883222959500 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 148871 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1832868777500 97.33% 97.33% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 80360500 0.00% 97.33% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 672864500 0.04% 97.37% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 49601349000 2.63% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1883223351500 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl
504,505c510,511
< system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814951 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.693590 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814959 # fraction of swpipl calls that actually changed the ipl
544c550
< system.cpu.kern.callpal::swpipl 175508 91.23% 93.43% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175516 91.23% 93.43% # number of callpals executed
553,554c559,560
< system.cpu.kern.callpal::total 192390 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5869 # number of protection mode switches
---
> system.cpu.kern.callpal::total 192398 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5867 # number of protection mode switches
556c562
< system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
---
> system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
560c566
< system.cpu.kern.mode_switch_good::kernel 0.325439 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch_good::kernel 0.325550 # fraction of useful protection mode switches
562c568
< system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches
564,566c570,572
< system.cpu.kern.mode_ticks::kernel 36245351000 1.92% 1.92% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 4057630500 0.22% 2.14% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1842919968000 97.86% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_ticks::kernel 36222818500 1.92% 1.92% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 4061127000 0.22% 2.14% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1842939396000 97.86% 100.00% # number of ticks spent at the given mode
568,569c574,575
< system.cpu.tickCycles 85798616 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 90977858 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 83840328 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 91048047 # Total number of cycles that the object has spent stopped
601d606
< system.iobus.throughput 1436853 # Throughput (bytes/s)
604c609
< system.iobus.trans_dist::WriteReq 51169 # Transaction distribution
---
> system.iobus.trans_dist::WriteReq 51170 # Transaction distribution
606d610
< system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution
623,639c627,642
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 2705916 # Total data (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes)
662c665
< system.iobus.reqLayer29.occupancy 374409688 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks)
668c671
< system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 42013751 # Layer occupancy (ticks)
670,676c673,679
< system.cpu.icache.tags.replacements 1458007 # number of replacements
< system.cpu.icache.tags.tagsinuse 509.627041 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 18950160 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1458518 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 12.992750 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 31562091250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 509.627041 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.replacements 1457910 # number of replacements
> system.cpu.icache.tags.tagsinuse 509.626980 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 18940924 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1458421 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 12.987281 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 31560714250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 509.626980 # Average occupied blocks per requestor
680,682c683,685
< system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id
684,721c687,724
< system.cpu.icache.tags.tag_accesses 21867553 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 21867553 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 18950163 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 18950163 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 18950163 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 18950163 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 18950163 # number of overall hits
< system.cpu.icache.overall_hits::total 18950163 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1458695 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1458695 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1458695 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1458695 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1458695 # number of overall misses
< system.cpu.icache.overall_misses::total 1458695 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 20021954296 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 20021954296 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 20021954296 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 20021954296 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 20021954296 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 20021954296 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 20408858 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 20408858 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 20408858 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 20408858 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 20408858 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 20408858 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071474 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.071474 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.071474 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.071474 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.071474 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.071474 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.936057 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13725.936057 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13725.936057 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13725.936057 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 21858119 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 21858119 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 18940927 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 18940927 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 18940927 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 18940927 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 18940927 # number of overall hits
> system.cpu.icache.overall_hits::total 18940927 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1458596 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1458596 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1458596 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1458596 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1458596 # number of overall misses
> system.cpu.icache.overall_misses::total 1458596 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 20022164568 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 20022164568 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 20022164568 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 20022164568 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 20022164568 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 20022164568 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 20399523 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 20399523 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 20399523 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 20399523 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 20399523 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 20399523 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071501 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.071501 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.071501 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.071501 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.071501 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.071501 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.011844 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13727.011844 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13727.011844 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13727.011844 # average overall miss latency
730,753c733,756
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458695 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1458695 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1458695 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1458695 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1458695 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1458695 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097209704 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 17097209704 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097209704 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 17097209704 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097209704 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 17097209704 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071474 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.071474 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.071474 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11720.894158 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11720.894158 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458596 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1458596 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1458596 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1458596 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1458596 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1458596 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097663432 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 17097663432 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097663432 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 17097663432 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097663432 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 17097663432 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071501 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.071501 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.071501 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.000768 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.000768 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency
755,757c758,759
< system.cpu.toL2Bus.throughput 126942050 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 2557486 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2557452 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2557139 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2557106 # Transaction distribution
760,765c762,767
< system.cpu.toL2Bus.trans_dist::Writeback 838282 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41557 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 304264 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 304264 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 838111 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 304253 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 304253 # Transaction distribution
767,775c769,787
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917328 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663485 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 6580813 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352512 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143044180 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 236396692 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 236386772 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 2673536 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 2697842997 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917133 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662791 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 6579924 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93346368 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143016724 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 236363092 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 41947 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3734153 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.011176 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.105123 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3692421 98.88% 98.88% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 41732 1.12% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3734153 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2697404999 # Layer occupancy (ticks)
777c789
< system.cpu.toL2Bus.snoopLayer0.occupancy 232500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
779c791
< system.cpu.toL2Bus.respLayer0.occupancy 2191719796 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2191548568 # Layer occupancy (ticks)
781c793
< system.cpu.toL2Bus.respLayer1.occupancy 2194901157 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2194491404 # Layer occupancy (ticks)
783,787c795,799
< system.cpu.l2cache.tags.replacements 339412 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65326.749870 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2981869 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 404575 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 7.370374 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 339424 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65327.181695 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2981337 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 404586 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 7.368859 # Average number of references to valid blocks.
789,796c801,808
< system.cpu.l2cache.tags.occ_blocks::writebacks 54484.622776 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 10842.127094 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.831369 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165438 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996807 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1459 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 54492.967363 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 10834.214332 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.831497 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165317 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996814 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1457 # Occupied blocks per task id
798,806c810,818
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2777 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 30252211 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 30252211 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 2261673 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2261673 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 838282 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 838282 # number of Writeback hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2781 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 30247978 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 30247978 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 2261320 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2261320 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 838111 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 838111 # number of Writeback hits
809,826c821,838
< system.cpu.l2cache.ReadExReq_hits::cpu.inst 187588 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187588 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 2449261 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2449261 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 2449261 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2449261 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 288648 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 288648 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.inst 20 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.inst 116676 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116676 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 405324 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 405324 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 405324 # number of overall misses
< system.cpu.l2cache.overall_misses::total 405324 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18909912500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 18909912500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadExReq_hits::cpu.inst 187575 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187575 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 2448895 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2448895 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 2448895 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2448895 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 288657 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 288657 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.inst 116678 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116678 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 405335 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 405335 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 405335 # number of overall misses
> system.cpu.l2cache.overall_misses::total 405335 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18918279000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 18918279000 # number of ReadReq miss cycles
829,866c841,878
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8088441363 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8088441363 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 26998353863 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 26998353863 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 26998353863 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 26998353863 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 2550321 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2550321 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 838282 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 838282 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 24 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304264 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304264 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 2854585 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2854585 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 2854585 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2854585 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113181 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.113181 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.833333 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.833333 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383470 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383470 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141991 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.141991 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141991 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.141991 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65512.016366 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 65512.016366 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 5774.750000 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5774.750000 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69323.951481 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69323.951481 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66609.314679 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 66609.314679 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66609.314679 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 66609.314679 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8105432113 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8105432113 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27023711113 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 27023711113 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27023711113 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 27023711113 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 2549977 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2549977 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 838111 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 838111 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304253 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304253 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 2854230 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2854230 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 2854230 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2854230 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113200 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.113200 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383490 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383490 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142012 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.142012 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142012 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.142012 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65538.958002 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 65538.958002 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 6793.823529 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6793.823529 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69468.384040 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69468.384040 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 66670.065780 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 66670.065780 # average overall miss latency
875,922c887,934
< system.cpu.l2cache.writebacks::writebacks 76605 # number of writebacks
< system.cpu.l2cache.writebacks::total 76605 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288648 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 288648 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 20 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116676 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116676 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 405324 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 405324 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 405324 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 405324 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15301161000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15301161000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 201018 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 201018 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6587763637 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6587763637 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21888924637 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 21888924637 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21888924637 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 21888924637 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333222000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333222000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887374000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887374000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3220596000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3220596000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113181 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113181 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.833333 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383470 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383470 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141991 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.141991 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141991 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.141991 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53009.759292 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53009.759292 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10050.900000 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10050.900000 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56462.028498 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56462.028498 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54003.524679 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54003.524679 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54003.524679 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54003.524679 # average overall mshr miss latency
---
> system.cpu.l2cache.writebacks::writebacks 76624 # number of writebacks
> system.cpu.l2cache.writebacks::total 76624 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288657 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 288657 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116678 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116678 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 405335 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 405335 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 405335 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 405335 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15309425000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15309425000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 170516 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 170516 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6604759387 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6604759387 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21914184387 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 21914184387 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21914184387 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 21914184387 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333304000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333304000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1888377500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1888377500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221681500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221681500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113200 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113200 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383490 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383490 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.142012 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.142012 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53036.735641 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53036.735641 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10030.352941 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.352941 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56606.724378 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56606.724378 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency
930c942
< system.cpu.dcache.tags.replacements 1395422 # number of replacements
---
> system.cpu.dcache.tags.replacements 1395163 # number of replacements
932,934c944,946
< system.cpu.dcache.tags.total_refs 13764943 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1395934 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 9.860741 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 13764370 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1395675 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 9.862160 # Average number of references to valid blocks.
940,941c952,953
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
944,959c956,971
< system.cpu.dcache.tags.tag_accesses 63626016 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63626016 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 7806784 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7806784 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 5576432 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5576432 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182707 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 182707 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.inst 198983 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 198983 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.inst 13383216 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13383216 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 13383216 # number of overall hits
< system.cpu.dcache.overall_hits::total 13383216 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.inst 1201616 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1201616 # number of ReadReq misses
---
> system.cpu.dcache.tags.tag_accesses 63622669 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63622669 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 7806418 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7806418 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 5576177 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5576177 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182756 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 182756 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.inst 198986 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 198986 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.inst 13382595 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13382595 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 13382595 # number of overall hits
> system.cpu.dcache.overall_hits::total 13382595 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.inst 1201460 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1201460 # number of ReadReq misses
962,1009c974,1021
< system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17299 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17299 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.inst 1775315 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1775315 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 1775315 # number of overall misses
< system.cpu.dcache.overall_misses::total 1775315 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31018318500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 31018318500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20748316044 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 20748316044 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231689250 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 231689250 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 51766634544 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 51766634544 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 51766634544 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 51766634544 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 9008400 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9008400 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.inst 6150131 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6150131 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200006 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200006 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198983 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 198983 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.inst 15158531 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15158531 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 15158531 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15158531 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133388 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.133388 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093282 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.093282 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086492 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086492 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.117117 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.117117 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.117117 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.117117 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25813.836117 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 25813.836117 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36165.857085 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 36165.857085 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13393.216371 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13393.216371 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29159.126433 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 29159.126433 # average overall miss latency
---
> system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17252 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17252 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.inst 1775159 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1775159 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 1775159 # number of overall misses
> system.cpu.dcache.overall_misses::total 1775159 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31026314750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 31026314750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20775588791 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 20775588791 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 230892000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 230892000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 51801903541 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 51801903541 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 51801903541 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 51801903541 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 9007878 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9007878 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.inst 6149876 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6149876 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200008 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200008 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198986 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 198986 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.inst 15157754 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15157754 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 15157754 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15157754 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133379 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.133379 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093286 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.093286 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086257 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086257 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.117112 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.117112 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.117112 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.117112 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25823.843282 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 25823.843282 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36213.395511 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 36213.395511 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13383.491769 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13383.491769 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29181.556999 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 29181.556999 # average overall miss latency
1018,1023c1030,1035
< system.cpu.dcache.writebacks::writebacks 838282 # number of writebacks
< system.cpu.dcache.writebacks::total 838282 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127187 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 127187 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269448 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 269448 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 838111 # number of writebacks
> system.cpu.dcache.writebacks::total 838111 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127232 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 127232 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269462 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 269462 # number of WriteReq MSHR hits
1026,1075c1038,1087
< system.cpu.dcache.demand_mshr_hits::cpu.inst 396635 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 396635 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 396635 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 396635 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074429 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304251 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304251 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17296 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17296 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.inst 1378680 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1378680 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.inst 1378680 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1378680 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26906996250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 26906996250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10272860843 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10272860843 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196930250 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196930250 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179857093 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 37179857093 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179857093 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 37179857093 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423313500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423313500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002790500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002790500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426104000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426104000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119270 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119270 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049471 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086477 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086477 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.090951 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.090951 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25043.065898 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.065898 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33764.427538 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33764.427538 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11385.884019 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11385.884019 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_hits::cpu.inst 396694 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 396694 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 396694 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 396694 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074228 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1074228 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304237 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304237 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17249 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.inst 1378465 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1378465 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.inst 1378465 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1378465 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26911701750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 26911701750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10289625346 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10289625346 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196226500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196226500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37201327096 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 37201327096 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37201327096 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 37201327096 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423395500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423395500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2003794000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2003794000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3427189500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3427189500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119254 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119254 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049470 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086242 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086242 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.090941 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.090941 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25052.132089 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25052.132089 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33821.084700 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33821.084700 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11376.108760 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.108760 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency