1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.907083 # Number of seconds simulated
4sim_ticks 1907083088000 # Number of ticks simulated
5final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.907083 # Number of seconds simulated
4sim_ticks 1907083088000 # Number of ticks simulated
5final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 20030 # Simulator instruction rate (inst/s)
8host_op_rate 20030 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 680419212 # Simulator tick rate (ticks/s)
| 7host_inst_rate 20979 # Simulator instruction rate (inst/s)
8host_op_rate 20979 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 712669715 # Simulator tick rate (ticks/s)
|
10host_mem_usage 389460 # Number of bytes of host memory used
| 10host_mem_usage 389460 # Number of bytes of host memory used
|
11host_seconds 2802.81 # Real time elapsed on the host
| 11host_seconds 2675.97 # Real time elapsed on the host
|
12sim_insts 56139550 # Number of instructions simulated
13sim_ops 56139550 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 1045632 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24852608 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::total 25899200 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 1045632 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 1045632 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 7558144 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7558144 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 16338 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 388322 # Number of read requests responded to by this memory
26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 404675 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 118096 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 118096 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 548289 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 13031738 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 13580530 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 548289 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 548289 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 3963196 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 3963196 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 3963196 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 548289 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 13031738 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 17543726 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 404675 # Number of read requests accepted
44system.physmem.writeReqs 118096 # Number of write requests accepted
45system.physmem.readBursts 404675 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 118096 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 25892096 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
49system.physmem.bytesWritten 7556352 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 25899200 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 7558144 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 25475 # Per bank write bursts
56system.physmem.perBankRdBursts::1 25702 # Per bank write bursts
57system.physmem.perBankRdBursts::2 25824 # Per bank write bursts
58system.physmem.perBankRdBursts::3 25771 # Per bank write bursts
59system.physmem.perBankRdBursts::4 25094 # Per bank write bursts
60system.physmem.perBankRdBursts::5 25022 # Per bank write bursts
61system.physmem.perBankRdBursts::6 24642 # Per bank write bursts
62system.physmem.perBankRdBursts::7 24532 # Per bank write bursts
63system.physmem.perBankRdBursts::8 25301 # Per bank write bursts
64system.physmem.perBankRdBursts::9 25195 # Per bank write bursts
65system.physmem.perBankRdBursts::10 25365 # Per bank write bursts
66system.physmem.perBankRdBursts::11 25031 # Per bank write bursts
67system.physmem.perBankRdBursts::12 24528 # Per bank write bursts
68system.physmem.perBankRdBursts::13 25559 # Per bank write bursts
69system.physmem.perBankRdBursts::14 25792 # Per bank write bursts
70system.physmem.perBankRdBursts::15 25731 # Per bank write bursts
71system.physmem.perBankWrBursts::0 7824 # Per bank write bursts
72system.physmem.perBankWrBursts::1 7667 # Per bank write bursts
73system.physmem.perBankWrBursts::2 8078 # Per bank write bursts
74system.physmem.perBankWrBursts::3 7735 # Per bank write bursts
75system.physmem.perBankWrBursts::4 7199 # Per bank write bursts
76system.physmem.perBankWrBursts::5 7011 # Per bank write bursts
77system.physmem.perBankWrBursts::6 6644 # Per bank write bursts
78system.physmem.perBankWrBursts::7 6403 # Per bank write bursts
79system.physmem.perBankWrBursts::8 7407 # Per bank write bursts
80system.physmem.perBankWrBursts::9 6813 # Per bank write bursts
81system.physmem.perBankWrBursts::10 7251 # Per bank write bursts
82system.physmem.perBankWrBursts::11 7009 # Per bank write bursts
83system.physmem.perBankWrBursts::12 7080 # Per bank write bursts
84system.physmem.perBankWrBursts::13 8008 # Per bank write bursts
85system.physmem.perBankWrBursts::14 7995 # Per bank write bursts
86system.physmem.perBankWrBursts::15 7944 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
89system.physmem.totGap 1907074301500 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 404675 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 118096 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 402295 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 2190 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 1480 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 2865 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 7261 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 5935 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 6910 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 6065 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 5979 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 6478 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 6947 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 6490 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 8391 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 8689 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 7302 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 7698 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 6991 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 7145 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 5952 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 5549 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 210 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 174 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 118 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 106 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 199 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 118 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 164 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 131 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 191 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 172 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 207 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 158 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 161 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 116 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 113 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 76 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 114 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 91 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 64552 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 518.162845 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 316.762326 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 407.336965 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 15022 23.27% 23.27% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 11126 17.24% 40.51% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 5008 7.76% 48.26% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 3170 4.91% 53.18% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 2578 3.99% 57.17% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 1854 2.87% 60.04% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 4219 6.54% 66.58% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 1366 2.12% 68.69% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 20209 31.31% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 64552 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 5276 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 76.676839 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::stdev 2890.632458 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::0-8191 5273 99.94% 99.94% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::total 5276 # Reads before turning the bus around for writes
222system.physmem.wrPerTurnAround::samples 5276 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::mean 22.378317 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::gmean 19.075849 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::stdev 20.638302 # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::16-23 4671 88.53% 88.53% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::24-31 37 0.70% 89.23% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::32-39 29 0.55% 89.78% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::40-47 43 0.82% 90.60% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::48-55 200 3.79% 94.39% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::56-63 11 0.21% 94.60% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::64-71 10 0.19% 94.79% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::72-79 32 0.61% 95.39% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::80-87 177 3.35% 98.75% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::88-95 7 0.13% 98.88% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::96-103 14 0.27% 99.15% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::104-111 4 0.08% 99.22% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::128-135 4 0.08% 99.32% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::152-159 1 0.02% 99.43% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::160-167 3 0.06% 99.49% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::168-175 6 0.11% 99.60% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::176-183 5 0.09% 99.70% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::184-191 5 0.09% 99.79% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::192-199 1 0.02% 99.81% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::200-207 3 0.06% 99.87% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::208-215 4 0.08% 99.94% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::256-263 3 0.06% 100.00% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::total 5276 # Writes before turning the bus around for reads
252system.physmem.totQLat 2650883750 # Total ticks spent queuing
253system.physmem.totMemAccLat 10236458750 # Total ticks spent from burst creation until serviced by the DRAM
254system.physmem.totBusLat 2022820000 # Total ticks spent in databus transfers
255system.physmem.avgQLat 6552.45 # Average queueing delay per DRAM burst
256system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
257system.physmem.avgMemAccLat 25302.45 # Average memory access latency per DRAM burst
258system.physmem.avgRdBW 13.58 # Average DRAM read bandwidth in MiByte/s
259system.physmem.avgWrBW 3.96 # Average achieved write bandwidth in MiByte/s
260system.physmem.avgRdBWSys 13.58 # Average system read bandwidth in MiByte/s
261system.physmem.avgWrBWSys 3.96 # Average system write bandwidth in MiByte/s
262system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
263system.physmem.busUtil 0.14 # Data bus utilization in percentage
264system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
265system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
266system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
267system.physmem.avgWrQLen 21.50 # Average write queue length when enqueuing
268system.physmem.readRowHits 362672 # Number of row buffer hits during reads
269system.physmem.writeRowHits 95408 # Number of row buffer hits during writes
270system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads
271system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes
272system.physmem.avgGap 3648010.89 # Average gap between requests
273system.physmem.pageHitRate 87.64 # Row buffer hit rate, read and write combined
274system.physmem_0.actEnergy 238359240 # Energy for activate commands per rank (pJ)
275system.physmem_0.preEnergy 130057125 # Energy for precharge commands per rank (pJ)
276system.physmem_0.readEnergy 1576083600 # Energy for read commands per rank (pJ)
277system.physmem_0.writeEnergy 379475280 # Energy for write commands per rank (pJ)
278system.physmem_0.refreshEnergy 124561092240 # Energy for refresh commands per rank (pJ)
279system.physmem_0.actBackEnergy 67798389510 # Energy for active background per rank (pJ)
280system.physmem_0.preBackEnergy 1084774932000 # Energy for precharge background per rank (pJ)
281system.physmem_0.totalEnergy 1279458388995 # Total energy per rank (pJ)
282system.physmem_0.averagePower 670.899637 # Core power per rank (mW)
283system.physmem_0.memoryStateTime::IDLE 1804362652750 # Time in different power states
284system.physmem_0.memoryStateTime::REF 63681540000 # Time in different power states
285system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
286system.physmem_0.memoryStateTime::ACT 39034493500 # Time in different power states
287system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
288system.physmem_1.actEnergy 249653880 # Energy for activate commands per rank (pJ)
289system.physmem_1.preEnergy 136219875 # Energy for precharge commands per rank (pJ)
290system.physmem_1.readEnergy 1579515600 # Energy for read commands per rank (pJ)
291system.physmem_1.writeEnergy 385605360 # Energy for write commands per rank (pJ)
292system.physmem_1.refreshEnergy 124561092240 # Energy for refresh commands per rank (pJ)
293system.physmem_1.actBackEnergy 68553947025 # Energy for active background per rank (pJ)
294system.physmem_1.preBackEnergy 1084112170500 # Energy for precharge background per rank (pJ)
295system.physmem_1.totalEnergy 1279578204480 # Total energy per rank (pJ)
296system.physmem_1.averagePower 670.962459 # Core power per rank (mW)
297system.physmem_1.memoryStateTime::IDLE 1803261638750 # Time in different power states
298system.physmem_1.memoryStateTime::REF 63681540000 # Time in different power states
299system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
300system.physmem_1.memoryStateTime::ACT 40135521250 # Time in different power states
301system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
302system.cpu.branchPred.lookups 15213605 # Number of BP lookups
303system.cpu.branchPred.condPredicted 13089935 # Number of conditional branches predicted
304system.cpu.branchPred.condIncorrect 512661 # Number of conditional branches incorrect
305system.cpu.branchPred.BTBLookups 11946485 # Number of BTB lookups
306system.cpu.branchPred.BTBHits 4550663 # Number of BTB hits
307system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
308system.cpu.branchPred.BTBHitPct 38.092066 # BTB Hit Percentage
309system.cpu.branchPred.usedRAS 861069 # Number of times the RAS was used to get a target.
310system.cpu.branchPred.RASInCorrect 32299 # Number of incorrect RAS predictions.
311system.cpu.branchPred.indirectLookups 6536873 # Number of indirect predictor lookups.
312system.cpu.branchPred.indirectHits 544356 # Number of indirect target hits.
313system.cpu.branchPred.indirectMisses 5992517 # Number of indirect misses.
314system.cpu.branchPredindirectMispredicted 219108 # Number of mispredicted indirect branches.
315system.cpu_clk_domain.clock 500 # Clock period in ticks
316system.cpu.dtb.fetch_hits 0 # ITB hits
317system.cpu.dtb.fetch_misses 0 # ITB misses
318system.cpu.dtb.fetch_acv 0 # ITB acv
319system.cpu.dtb.fetch_accesses 0 # ITB accesses
320system.cpu.dtb.read_hits 9320625 # DTB read hits
321system.cpu.dtb.read_misses 17559 # DTB read misses
322system.cpu.dtb.read_acv 211 # DTB read access violations
323system.cpu.dtb.read_accesses 766669 # DTB read accesses
324system.cpu.dtb.write_hits 6392876 # DTB write hits
325system.cpu.dtb.write_misses 2428 # DTB write misses
326system.cpu.dtb.write_acv 159 # DTB write access violations
327system.cpu.dtb.write_accesses 298894 # DTB write accesses
328system.cpu.dtb.data_hits 15713501 # DTB hits
329system.cpu.dtb.data_misses 19987 # DTB misses
330system.cpu.dtb.data_acv 370 # DTB access violations
331system.cpu.dtb.data_accesses 1065563 # DTB accesses
332system.cpu.itb.fetch_hits 4013626 # ITB hits
333system.cpu.itb.fetch_misses 6348 # ITB misses
334system.cpu.itb.fetch_acv 677 # ITB acv
335system.cpu.itb.fetch_accesses 4019974 # ITB accesses
336system.cpu.itb.read_hits 0 # DTB read hits
337system.cpu.itb.read_misses 0 # DTB read misses
338system.cpu.itb.read_acv 0 # DTB read access violations
339system.cpu.itb.read_accesses 0 # DTB read accesses
340system.cpu.itb.write_hits 0 # DTB write hits
341system.cpu.itb.write_misses 0 # DTB write misses
342system.cpu.itb.write_acv 0 # DTB write access violations
343system.cpu.itb.write_accesses 0 # DTB write accesses
344system.cpu.itb.data_hits 0 # DTB hits
345system.cpu.itb.data_misses 0 # DTB misses
346system.cpu.itb.data_acv 0 # DTB access violations
347system.cpu.itb.data_accesses 0 # DTB accesses
348system.cpu.numCycles 223105667 # number of cpu cycles simulated
349system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
350system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
351system.cpu.committedInsts 56139550 # Number of instructions committed
352system.cpu.committedOps 56139550 # Number of ops (including micro ops) committed
353system.cpu.discardedOps 2984225 # Number of ops (including micro ops) which were discarded before commit
354system.cpu.numFetchSuspends 5570 # Number of times Execute suspended instruction fetching
355system.cpu.quiesceCycles 3591060509 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
356system.cpu.cpi 3.974126 # CPI: cycles per instruction
357system.cpu.ipc 0.251628 # IPC: instructions per cycle
358system.cpu.op_class_0::No_OpClass 3199335 5.70% 5.70% # Class of committed instruction
359system.cpu.op_class_0::IntAlu 36193553 64.47% 70.17% # Class of committed instruction
360system.cpu.op_class_0::IntMult 60844 0.11% 70.28% # Class of committed instruction
361system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction
362system.cpu.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction
363system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
364system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
365system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
366system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
367system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
368system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
369system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
370system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
371system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
372system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
373system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
374system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
375system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
376system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
377system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
378system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
379system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
380system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
381system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
382system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
383system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
384system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
385system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
386system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
387system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
388system.cpu.op_class_0::MemRead 9319847 16.60% 86.95% # Class of committed instruction
389system.cpu.op_class_0::MemWrite 6372583 11.35% 98.30% # Class of committed instruction
390system.cpu.op_class_0::IprAccess 951665 1.70% 100.00% # Class of committed instruction
391system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
392system.cpu.op_class_0::total 56139550 # Class of committed instruction
393system.cpu.kern.inst.arm 0 # number of arm instructions executed
394system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
395system.cpu.kern.inst.hwrei 211602 # number of hwrei instructions executed
396system.cpu.kern.ipl_count::0 74817 40.93% 40.93% # number of times we switched to this ipl
397system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
398system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl
399system.cpu.kern.ipl_count::31 105924 57.95% 100.00% # number of times we switched to this ipl
400system.cpu.kern.ipl_count::total 182777 # number of times we switched to this ipl
401system.cpu.kern.ipl_good::0 73450 49.32% 49.32% # number of times we switched to this ipl from a different ipl
402system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
403system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl
404system.cpu.kern.ipl_good::31 73450 49.32% 100.00% # number of times we switched to this ipl from a different ipl
405system.cpu.kern.ipl_good::total 148936 # number of times we switched to this ipl from a different ipl
406system.cpu.kern.ipl_ticks::0 1838095236500 96.38% 96.38% # number of cycles we spent at this ipl
407system.cpu.kern.ipl_ticks::21 85937000 0.00% 96.39% # number of cycles we spent at this ipl
408system.cpu.kern.ipl_ticks::22 709530500 0.04% 96.42% # number of cycles we spent at this ipl
409system.cpu.kern.ipl_ticks::31 68191372500 3.58% 100.00% # number of cycles we spent at this ipl
410system.cpu.kern.ipl_ticks::total 1907082076500 # number of cycles we spent at this ipl
411system.cpu.kern.ipl_used::0 0.981729 # fraction of swpipl calls that actually changed the ipl
412system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
413system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
414system.cpu.kern.ipl_used::31 0.693422 # fraction of swpipl calls that actually changed the ipl
415system.cpu.kern.ipl_used::total 0.814851 # fraction of swpipl calls that actually changed the ipl
416system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
417system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
418system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
419system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
420system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
421system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
422system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
423system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
424system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
425system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
426system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
427system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
428system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
429system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
430system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
431system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
432system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
433system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
434system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
435system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
436system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
437system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
438system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
439system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
440system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
441system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
442system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
443system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
444system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
445system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
446system.cpu.kern.syscall::total 326 # number of syscalls executed
447system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
448system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
449system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
450system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
451system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
452system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
453system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
454system.cpu.kern.callpal::swpipl 175610 91.22% 93.43% # number of callpals executed
455system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed
456system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
457system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
458system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
459system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
460system.cpu.kern.callpal::rti 5130 2.66% 99.64% # number of callpals executed
461system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
462system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
463system.cpu.kern.callpal::total 192505 # number of callpals executed
464system.cpu.kern.mode_switch::kernel 5879 # number of protection mode switches
465system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
466system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
467system.cpu.kern.mode_good::kernel 1907
468system.cpu.kern.mode_good::user 1738
469system.cpu.kern.mode_good::idle 169
470system.cpu.kern.mode_switch_good::kernel 0.324375 # fraction of useful protection mode switches
471system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
472system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
473system.cpu.kern.mode_switch_good::total 0.392750 # fraction of useful protection mode switches
474system.cpu.kern.mode_ticks::kernel 38852804500 2.04% 2.04% # number of ticks spent at the given mode
475system.cpu.kern.mode_ticks::user 4558296500 0.24% 2.28% # number of ticks spent at the given mode
476system.cpu.kern.mode_ticks::idle 1863670965500 97.72% 100.00% # number of ticks spent at the given mode
477system.cpu.kern.swap_context 4178 # number of times the context was actually changed
478system.cpu.tickCycles 85299333 # Number of cycles that the object actually ticked
479system.cpu.idleCycles 137806334 # Total number of cycles that the object has spent stopped
480system.cpu.dcache.tags.replacements 1394573 # number of replacements
481system.cpu.dcache.tags.tagsinuse 511.976747 # Cycle average of tags in use
482system.cpu.dcache.tags.total_refs 13828974 # Total number of references to valid blocks.
483system.cpu.dcache.tags.sampled_refs 1395085 # Sample count of references to valid blocks.
484system.cpu.dcache.tags.avg_refs 9.912639 # Average number of references to valid blocks.
485system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit.
486system.cpu.dcache.tags.occ_blocks::cpu.data 511.976747 # Average occupied blocks per requestor
487system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy
488system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy
489system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
490system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
491system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
492system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
493system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
494system.cpu.dcache.tags.tag_accesses 63880747 # Number of tag accesses
495system.cpu.dcache.tags.data_accesses 63880747 # Number of data accesses
496system.cpu.dcache.ReadReq_hits::cpu.data 7869575 # number of ReadReq hits
497system.cpu.dcache.ReadReq_hits::total 7869575 # number of ReadReq hits
498system.cpu.dcache.WriteReq_hits::cpu.data 5576818 # number of WriteReq hits
499system.cpu.dcache.WriteReq_hits::total 5576818 # number of WriteReq hits
500system.cpu.dcache.LoadLockedReq_hits::cpu.data 183500 # number of LoadLockedReq hits
501system.cpu.dcache.LoadLockedReq_hits::total 183500 # number of LoadLockedReq hits
502system.cpu.dcache.StoreCondReq_hits::cpu.data 199049 # number of StoreCondReq hits
503system.cpu.dcache.StoreCondReq_hits::total 199049 # number of StoreCondReq hits
504system.cpu.dcache.demand_hits::cpu.data 13446393 # number of demand (read+write) hits
505system.cpu.dcache.demand_hits::total 13446393 # number of demand (read+write) hits
506system.cpu.dcache.overall_hits::cpu.data 13446393 # number of overall hits
507system.cpu.dcache.overall_hits::total 13446393 # number of overall hits
508system.cpu.dcache.ReadReq_misses::cpu.data 1201253 # number of ReadReq misses
509system.cpu.dcache.ReadReq_misses::total 1201253 # number of ReadReq misses
510system.cpu.dcache.WriteReq_misses::cpu.data 574650 # number of WriteReq misses
511system.cpu.dcache.WriteReq_misses::total 574650 # number of WriteReq misses
512system.cpu.dcache.LoadLockedReq_misses::cpu.data 16570 # number of LoadLockedReq misses
513system.cpu.dcache.LoadLockedReq_misses::total 16570 # number of LoadLockedReq misses
514system.cpu.dcache.demand_misses::cpu.data 1775903 # number of demand (read+write) misses
515system.cpu.dcache.demand_misses::total 1775903 # number of demand (read+write) misses
516system.cpu.dcache.overall_misses::cpu.data 1775903 # number of overall misses
517system.cpu.dcache.overall_misses::total 1775903 # number of overall misses
518system.cpu.dcache.ReadReq_miss_latency::cpu.data 46959686500 # number of ReadReq miss cycles
519system.cpu.dcache.ReadReq_miss_latency::total 46959686500 # number of ReadReq miss cycles
520system.cpu.dcache.WriteReq_miss_latency::cpu.data 33959629000 # number of WriteReq miss cycles
521system.cpu.dcache.WriteReq_miss_latency::total 33959629000 # number of WriteReq miss cycles
522system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 226795500 # number of LoadLockedReq miss cycles
523system.cpu.dcache.LoadLockedReq_miss_latency::total 226795500 # number of LoadLockedReq miss cycles
524system.cpu.dcache.demand_miss_latency::cpu.data 80919315500 # number of demand (read+write) miss cycles
525system.cpu.dcache.demand_miss_latency::total 80919315500 # number of demand (read+write) miss cycles
526system.cpu.dcache.overall_miss_latency::cpu.data 80919315500 # number of overall miss cycles
527system.cpu.dcache.overall_miss_latency::total 80919315500 # number of overall miss cycles
528system.cpu.dcache.ReadReq_accesses::cpu.data 9070828 # number of ReadReq accesses(hits+misses)
529system.cpu.dcache.ReadReq_accesses::total 9070828 # number of ReadReq accesses(hits+misses)
530system.cpu.dcache.WriteReq_accesses::cpu.data 6151468 # number of WriteReq accesses(hits+misses)
531system.cpu.dcache.WriteReq_accesses::total 6151468 # number of WriteReq accesses(hits+misses)
532system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200070 # number of LoadLockedReq accesses(hits+misses)
533system.cpu.dcache.LoadLockedReq_accesses::total 200070 # number of LoadLockedReq accesses(hits+misses)
534system.cpu.dcache.StoreCondReq_accesses::cpu.data 199049 # number of StoreCondReq accesses(hits+misses)
535system.cpu.dcache.StoreCondReq_accesses::total 199049 # number of StoreCondReq accesses(hits+misses)
536system.cpu.dcache.demand_accesses::cpu.data 15222296 # number of demand (read+write) accesses
537system.cpu.dcache.demand_accesses::total 15222296 # number of demand (read+write) accesses
538system.cpu.dcache.overall_accesses::cpu.data 15222296 # number of overall (read+write) accesses
539system.cpu.dcache.overall_accesses::total 15222296 # number of overall (read+write) accesses
540system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132430 # miss rate for ReadReq accesses
541system.cpu.dcache.ReadReq_miss_rate::total 0.132430 # miss rate for ReadReq accesses
542system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093417 # miss rate for WriteReq accesses
543system.cpu.dcache.WriteReq_miss_rate::total 0.093417 # miss rate for WriteReq accesses
544system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082821 # miss rate for LoadLockedReq accesses
545system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082821 # miss rate for LoadLockedReq accesses
546system.cpu.dcache.demand_miss_rate::cpu.data 0.116665 # miss rate for demand accesses
547system.cpu.dcache.demand_miss_rate::total 0.116665 # miss rate for demand accesses
548system.cpu.dcache.overall_miss_rate::cpu.data 0.116665 # miss rate for overall accesses
549system.cpu.dcache.overall_miss_rate::total 0.116665 # miss rate for overall accesses
550system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.253256 # average ReadReq miss latency
551system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.253256 # average ReadReq miss latency
552system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59096.195945 # average WriteReq miss latency
553system.cpu.dcache.WriteReq_avg_miss_latency::total 59096.195945 # average WriteReq miss latency
554system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13687.115269 # average LoadLockedReq miss latency
555system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13687.115269 # average LoadLockedReq miss latency
556system.cpu.dcache.demand_avg_miss_latency::cpu.data 45565.166284 # average overall miss latency
557system.cpu.dcache.demand_avg_miss_latency::total 45565.166284 # average overall miss latency
558system.cpu.dcache.overall_avg_miss_latency::cpu.data 45565.166284 # average overall miss latency
559system.cpu.dcache.overall_avg_miss_latency::total 45565.166284 # average overall miss latency
560system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
561system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
562system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
563system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
564system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
565system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
| 12sim_insts 56139550 # Number of instructions simulated
13sim_ops 56139550 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 1045632 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24852608 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::total 25899200 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 1045632 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 1045632 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 7558144 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7558144 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 16338 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 388322 # Number of read requests responded to by this memory
26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 404675 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 118096 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 118096 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 548289 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 13031738 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 13580530 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 548289 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 548289 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 3963196 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 3963196 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 3963196 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 548289 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 13031738 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 17543726 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 404675 # Number of read requests accepted
44system.physmem.writeReqs 118096 # Number of write requests accepted
45system.physmem.readBursts 404675 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 118096 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 25892096 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
49system.physmem.bytesWritten 7556352 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 25899200 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 7558144 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 25475 # Per bank write bursts
56system.physmem.perBankRdBursts::1 25702 # Per bank write bursts
57system.physmem.perBankRdBursts::2 25824 # Per bank write bursts
58system.physmem.perBankRdBursts::3 25771 # Per bank write bursts
59system.physmem.perBankRdBursts::4 25094 # Per bank write bursts
60system.physmem.perBankRdBursts::5 25022 # Per bank write bursts
61system.physmem.perBankRdBursts::6 24642 # Per bank write bursts
62system.physmem.perBankRdBursts::7 24532 # Per bank write bursts
63system.physmem.perBankRdBursts::8 25301 # Per bank write bursts
64system.physmem.perBankRdBursts::9 25195 # Per bank write bursts
65system.physmem.perBankRdBursts::10 25365 # Per bank write bursts
66system.physmem.perBankRdBursts::11 25031 # Per bank write bursts
67system.physmem.perBankRdBursts::12 24528 # Per bank write bursts
68system.physmem.perBankRdBursts::13 25559 # Per bank write bursts
69system.physmem.perBankRdBursts::14 25792 # Per bank write bursts
70system.physmem.perBankRdBursts::15 25731 # Per bank write bursts
71system.physmem.perBankWrBursts::0 7824 # Per bank write bursts
72system.physmem.perBankWrBursts::1 7667 # Per bank write bursts
73system.physmem.perBankWrBursts::2 8078 # Per bank write bursts
74system.physmem.perBankWrBursts::3 7735 # Per bank write bursts
75system.physmem.perBankWrBursts::4 7199 # Per bank write bursts
76system.physmem.perBankWrBursts::5 7011 # Per bank write bursts
77system.physmem.perBankWrBursts::6 6644 # Per bank write bursts
78system.physmem.perBankWrBursts::7 6403 # Per bank write bursts
79system.physmem.perBankWrBursts::8 7407 # Per bank write bursts
80system.physmem.perBankWrBursts::9 6813 # Per bank write bursts
81system.physmem.perBankWrBursts::10 7251 # Per bank write bursts
82system.physmem.perBankWrBursts::11 7009 # Per bank write bursts
83system.physmem.perBankWrBursts::12 7080 # Per bank write bursts
84system.physmem.perBankWrBursts::13 8008 # Per bank write bursts
85system.physmem.perBankWrBursts::14 7995 # Per bank write bursts
86system.physmem.perBankWrBursts::15 7944 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
89system.physmem.totGap 1907074301500 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 404675 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 118096 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 402295 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 2190 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 1480 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 2865 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 7261 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 5935 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 6910 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 6065 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 5979 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 6478 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 6947 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 6490 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 8391 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 8689 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 7302 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 7698 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 6991 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 7145 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 5952 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 5549 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 210 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 174 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 118 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 106 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 199 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 118 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 164 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 131 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 191 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 172 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 207 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 158 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 161 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 116 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 113 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 76 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 114 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 91 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 64552 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 518.162845 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 316.762326 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 407.336965 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 15022 23.27% 23.27% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 11126 17.24% 40.51% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 5008 7.76% 48.26% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 3170 4.91% 53.18% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 2578 3.99% 57.17% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 1854 2.87% 60.04% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 4219 6.54% 66.58% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 1366 2.12% 68.69% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 20209 31.31% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 64552 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 5276 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 76.676839 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::stdev 2890.632458 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::0-8191 5273 99.94% 99.94% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::total 5276 # Reads before turning the bus around for writes
222system.physmem.wrPerTurnAround::samples 5276 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::mean 22.378317 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::gmean 19.075849 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::stdev 20.638302 # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::16-23 4671 88.53% 88.53% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::24-31 37 0.70% 89.23% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::32-39 29 0.55% 89.78% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::40-47 43 0.82% 90.60% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::48-55 200 3.79% 94.39% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::56-63 11 0.21% 94.60% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::64-71 10 0.19% 94.79% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::72-79 32 0.61% 95.39% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::80-87 177 3.35% 98.75% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::88-95 7 0.13% 98.88% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::96-103 14 0.27% 99.15% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::104-111 4 0.08% 99.22% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::128-135 4 0.08% 99.32% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::152-159 1 0.02% 99.43% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::160-167 3 0.06% 99.49% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::168-175 6 0.11% 99.60% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::176-183 5 0.09% 99.70% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::184-191 5 0.09% 99.79% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::192-199 1 0.02% 99.81% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::200-207 3 0.06% 99.87% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::208-215 4 0.08% 99.94% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::256-263 3 0.06% 100.00% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::total 5276 # Writes before turning the bus around for reads
252system.physmem.totQLat 2650883750 # Total ticks spent queuing
253system.physmem.totMemAccLat 10236458750 # Total ticks spent from burst creation until serviced by the DRAM
254system.physmem.totBusLat 2022820000 # Total ticks spent in databus transfers
255system.physmem.avgQLat 6552.45 # Average queueing delay per DRAM burst
256system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
257system.physmem.avgMemAccLat 25302.45 # Average memory access latency per DRAM burst
258system.physmem.avgRdBW 13.58 # Average DRAM read bandwidth in MiByte/s
259system.physmem.avgWrBW 3.96 # Average achieved write bandwidth in MiByte/s
260system.physmem.avgRdBWSys 13.58 # Average system read bandwidth in MiByte/s
261system.physmem.avgWrBWSys 3.96 # Average system write bandwidth in MiByte/s
262system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
263system.physmem.busUtil 0.14 # Data bus utilization in percentage
264system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
265system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
266system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
267system.physmem.avgWrQLen 21.50 # Average write queue length when enqueuing
268system.physmem.readRowHits 362672 # Number of row buffer hits during reads
269system.physmem.writeRowHits 95408 # Number of row buffer hits during writes
270system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads
271system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes
272system.physmem.avgGap 3648010.89 # Average gap between requests
273system.physmem.pageHitRate 87.64 # Row buffer hit rate, read and write combined
274system.physmem_0.actEnergy 238359240 # Energy for activate commands per rank (pJ)
275system.physmem_0.preEnergy 130057125 # Energy for precharge commands per rank (pJ)
276system.physmem_0.readEnergy 1576083600 # Energy for read commands per rank (pJ)
277system.physmem_0.writeEnergy 379475280 # Energy for write commands per rank (pJ)
278system.physmem_0.refreshEnergy 124561092240 # Energy for refresh commands per rank (pJ)
279system.physmem_0.actBackEnergy 67798389510 # Energy for active background per rank (pJ)
280system.physmem_0.preBackEnergy 1084774932000 # Energy for precharge background per rank (pJ)
281system.physmem_0.totalEnergy 1279458388995 # Total energy per rank (pJ)
282system.physmem_0.averagePower 670.899637 # Core power per rank (mW)
283system.physmem_0.memoryStateTime::IDLE 1804362652750 # Time in different power states
284system.physmem_0.memoryStateTime::REF 63681540000 # Time in different power states
285system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
286system.physmem_0.memoryStateTime::ACT 39034493500 # Time in different power states
287system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
288system.physmem_1.actEnergy 249653880 # Energy for activate commands per rank (pJ)
289system.physmem_1.preEnergy 136219875 # Energy for precharge commands per rank (pJ)
290system.physmem_1.readEnergy 1579515600 # Energy for read commands per rank (pJ)
291system.physmem_1.writeEnergy 385605360 # Energy for write commands per rank (pJ)
292system.physmem_1.refreshEnergy 124561092240 # Energy for refresh commands per rank (pJ)
293system.physmem_1.actBackEnergy 68553947025 # Energy for active background per rank (pJ)
294system.physmem_1.preBackEnergy 1084112170500 # Energy for precharge background per rank (pJ)
295system.physmem_1.totalEnergy 1279578204480 # Total energy per rank (pJ)
296system.physmem_1.averagePower 670.962459 # Core power per rank (mW)
297system.physmem_1.memoryStateTime::IDLE 1803261638750 # Time in different power states
298system.physmem_1.memoryStateTime::REF 63681540000 # Time in different power states
299system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
300system.physmem_1.memoryStateTime::ACT 40135521250 # Time in different power states
301system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
302system.cpu.branchPred.lookups 15213605 # Number of BP lookups
303system.cpu.branchPred.condPredicted 13089935 # Number of conditional branches predicted
304system.cpu.branchPred.condIncorrect 512661 # Number of conditional branches incorrect
305system.cpu.branchPred.BTBLookups 11946485 # Number of BTB lookups
306system.cpu.branchPred.BTBHits 4550663 # Number of BTB hits
307system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
308system.cpu.branchPred.BTBHitPct 38.092066 # BTB Hit Percentage
309system.cpu.branchPred.usedRAS 861069 # Number of times the RAS was used to get a target.
310system.cpu.branchPred.RASInCorrect 32299 # Number of incorrect RAS predictions.
311system.cpu.branchPred.indirectLookups 6536873 # Number of indirect predictor lookups.
312system.cpu.branchPred.indirectHits 544356 # Number of indirect target hits.
313system.cpu.branchPred.indirectMisses 5992517 # Number of indirect misses.
314system.cpu.branchPredindirectMispredicted 219108 # Number of mispredicted indirect branches.
315system.cpu_clk_domain.clock 500 # Clock period in ticks
316system.cpu.dtb.fetch_hits 0 # ITB hits
317system.cpu.dtb.fetch_misses 0 # ITB misses
318system.cpu.dtb.fetch_acv 0 # ITB acv
319system.cpu.dtb.fetch_accesses 0 # ITB accesses
320system.cpu.dtb.read_hits 9320625 # DTB read hits
321system.cpu.dtb.read_misses 17559 # DTB read misses
322system.cpu.dtb.read_acv 211 # DTB read access violations
323system.cpu.dtb.read_accesses 766669 # DTB read accesses
324system.cpu.dtb.write_hits 6392876 # DTB write hits
325system.cpu.dtb.write_misses 2428 # DTB write misses
326system.cpu.dtb.write_acv 159 # DTB write access violations
327system.cpu.dtb.write_accesses 298894 # DTB write accesses
328system.cpu.dtb.data_hits 15713501 # DTB hits
329system.cpu.dtb.data_misses 19987 # DTB misses
330system.cpu.dtb.data_acv 370 # DTB access violations
331system.cpu.dtb.data_accesses 1065563 # DTB accesses
332system.cpu.itb.fetch_hits 4013626 # ITB hits
333system.cpu.itb.fetch_misses 6348 # ITB misses
334system.cpu.itb.fetch_acv 677 # ITB acv
335system.cpu.itb.fetch_accesses 4019974 # ITB accesses
336system.cpu.itb.read_hits 0 # DTB read hits
337system.cpu.itb.read_misses 0 # DTB read misses
338system.cpu.itb.read_acv 0 # DTB read access violations
339system.cpu.itb.read_accesses 0 # DTB read accesses
340system.cpu.itb.write_hits 0 # DTB write hits
341system.cpu.itb.write_misses 0 # DTB write misses
342system.cpu.itb.write_acv 0 # DTB write access violations
343system.cpu.itb.write_accesses 0 # DTB write accesses
344system.cpu.itb.data_hits 0 # DTB hits
345system.cpu.itb.data_misses 0 # DTB misses
346system.cpu.itb.data_acv 0 # DTB access violations
347system.cpu.itb.data_accesses 0 # DTB accesses
348system.cpu.numCycles 223105667 # number of cpu cycles simulated
349system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
350system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
351system.cpu.committedInsts 56139550 # Number of instructions committed
352system.cpu.committedOps 56139550 # Number of ops (including micro ops) committed
353system.cpu.discardedOps 2984225 # Number of ops (including micro ops) which were discarded before commit
354system.cpu.numFetchSuspends 5570 # Number of times Execute suspended instruction fetching
355system.cpu.quiesceCycles 3591060509 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
356system.cpu.cpi 3.974126 # CPI: cycles per instruction
357system.cpu.ipc 0.251628 # IPC: instructions per cycle
358system.cpu.op_class_0::No_OpClass 3199335 5.70% 5.70% # Class of committed instruction
359system.cpu.op_class_0::IntAlu 36193553 64.47% 70.17% # Class of committed instruction
360system.cpu.op_class_0::IntMult 60844 0.11% 70.28% # Class of committed instruction
361system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction
362system.cpu.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction
363system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
364system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
365system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
366system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
367system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
368system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
369system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
370system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
371system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
372system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
373system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
374system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
375system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
376system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
377system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
378system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
379system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
380system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
381system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
382system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
383system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
384system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
385system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
386system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
387system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
388system.cpu.op_class_0::MemRead 9319847 16.60% 86.95% # Class of committed instruction
389system.cpu.op_class_0::MemWrite 6372583 11.35% 98.30% # Class of committed instruction
390system.cpu.op_class_0::IprAccess 951665 1.70% 100.00% # Class of committed instruction
391system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
392system.cpu.op_class_0::total 56139550 # Class of committed instruction
393system.cpu.kern.inst.arm 0 # number of arm instructions executed
394system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
395system.cpu.kern.inst.hwrei 211602 # number of hwrei instructions executed
396system.cpu.kern.ipl_count::0 74817 40.93% 40.93% # number of times we switched to this ipl
397system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
398system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl
399system.cpu.kern.ipl_count::31 105924 57.95% 100.00% # number of times we switched to this ipl
400system.cpu.kern.ipl_count::total 182777 # number of times we switched to this ipl
401system.cpu.kern.ipl_good::0 73450 49.32% 49.32% # number of times we switched to this ipl from a different ipl
402system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
403system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl
404system.cpu.kern.ipl_good::31 73450 49.32% 100.00% # number of times we switched to this ipl from a different ipl
405system.cpu.kern.ipl_good::total 148936 # number of times we switched to this ipl from a different ipl
406system.cpu.kern.ipl_ticks::0 1838095236500 96.38% 96.38% # number of cycles we spent at this ipl
407system.cpu.kern.ipl_ticks::21 85937000 0.00% 96.39% # number of cycles we spent at this ipl
408system.cpu.kern.ipl_ticks::22 709530500 0.04% 96.42% # number of cycles we spent at this ipl
409system.cpu.kern.ipl_ticks::31 68191372500 3.58% 100.00% # number of cycles we spent at this ipl
410system.cpu.kern.ipl_ticks::total 1907082076500 # number of cycles we spent at this ipl
411system.cpu.kern.ipl_used::0 0.981729 # fraction of swpipl calls that actually changed the ipl
412system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
413system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
414system.cpu.kern.ipl_used::31 0.693422 # fraction of swpipl calls that actually changed the ipl
415system.cpu.kern.ipl_used::total 0.814851 # fraction of swpipl calls that actually changed the ipl
416system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
417system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
418system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
419system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
420system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
421system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
422system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
423system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
424system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
425system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
426system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
427system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
428system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
429system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
430system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
431system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
432system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
433system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
434system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
435system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
436system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
437system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
438system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
439system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
440system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
441system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
442system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
443system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
444system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
445system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
446system.cpu.kern.syscall::total 326 # number of syscalls executed
447system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
448system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
449system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
450system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
451system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
452system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
453system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
454system.cpu.kern.callpal::swpipl 175610 91.22% 93.43% # number of callpals executed
455system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed
456system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
457system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
458system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
459system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
460system.cpu.kern.callpal::rti 5130 2.66% 99.64% # number of callpals executed
461system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
462system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
463system.cpu.kern.callpal::total 192505 # number of callpals executed
464system.cpu.kern.mode_switch::kernel 5879 # number of protection mode switches
465system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
466system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
467system.cpu.kern.mode_good::kernel 1907
468system.cpu.kern.mode_good::user 1738
469system.cpu.kern.mode_good::idle 169
470system.cpu.kern.mode_switch_good::kernel 0.324375 # fraction of useful protection mode switches
471system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
472system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
473system.cpu.kern.mode_switch_good::total 0.392750 # fraction of useful protection mode switches
474system.cpu.kern.mode_ticks::kernel 38852804500 2.04% 2.04% # number of ticks spent at the given mode
475system.cpu.kern.mode_ticks::user 4558296500 0.24% 2.28% # number of ticks spent at the given mode
476system.cpu.kern.mode_ticks::idle 1863670965500 97.72% 100.00% # number of ticks spent at the given mode
477system.cpu.kern.swap_context 4178 # number of times the context was actually changed
478system.cpu.tickCycles 85299333 # Number of cycles that the object actually ticked
479system.cpu.idleCycles 137806334 # Total number of cycles that the object has spent stopped
480system.cpu.dcache.tags.replacements 1394573 # number of replacements
481system.cpu.dcache.tags.tagsinuse 511.976747 # Cycle average of tags in use
482system.cpu.dcache.tags.total_refs 13828974 # Total number of references to valid blocks.
483system.cpu.dcache.tags.sampled_refs 1395085 # Sample count of references to valid blocks.
484system.cpu.dcache.tags.avg_refs 9.912639 # Average number of references to valid blocks.
485system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit.
486system.cpu.dcache.tags.occ_blocks::cpu.data 511.976747 # Average occupied blocks per requestor
487system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy
488system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy
489system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
490system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
491system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
492system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
493system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
494system.cpu.dcache.tags.tag_accesses 63880747 # Number of tag accesses
495system.cpu.dcache.tags.data_accesses 63880747 # Number of data accesses
496system.cpu.dcache.ReadReq_hits::cpu.data 7869575 # number of ReadReq hits
497system.cpu.dcache.ReadReq_hits::total 7869575 # number of ReadReq hits
498system.cpu.dcache.WriteReq_hits::cpu.data 5576818 # number of WriteReq hits
499system.cpu.dcache.WriteReq_hits::total 5576818 # number of WriteReq hits
500system.cpu.dcache.LoadLockedReq_hits::cpu.data 183500 # number of LoadLockedReq hits
501system.cpu.dcache.LoadLockedReq_hits::total 183500 # number of LoadLockedReq hits
502system.cpu.dcache.StoreCondReq_hits::cpu.data 199049 # number of StoreCondReq hits
503system.cpu.dcache.StoreCondReq_hits::total 199049 # number of StoreCondReq hits
504system.cpu.dcache.demand_hits::cpu.data 13446393 # number of demand (read+write) hits
505system.cpu.dcache.demand_hits::total 13446393 # number of demand (read+write) hits
506system.cpu.dcache.overall_hits::cpu.data 13446393 # number of overall hits
507system.cpu.dcache.overall_hits::total 13446393 # number of overall hits
508system.cpu.dcache.ReadReq_misses::cpu.data 1201253 # number of ReadReq misses
509system.cpu.dcache.ReadReq_misses::total 1201253 # number of ReadReq misses
510system.cpu.dcache.WriteReq_misses::cpu.data 574650 # number of WriteReq misses
511system.cpu.dcache.WriteReq_misses::total 574650 # number of WriteReq misses
512system.cpu.dcache.LoadLockedReq_misses::cpu.data 16570 # number of LoadLockedReq misses
513system.cpu.dcache.LoadLockedReq_misses::total 16570 # number of LoadLockedReq misses
514system.cpu.dcache.demand_misses::cpu.data 1775903 # number of demand (read+write) misses
515system.cpu.dcache.demand_misses::total 1775903 # number of demand (read+write) misses
516system.cpu.dcache.overall_misses::cpu.data 1775903 # number of overall misses
517system.cpu.dcache.overall_misses::total 1775903 # number of overall misses
518system.cpu.dcache.ReadReq_miss_latency::cpu.data 46959686500 # number of ReadReq miss cycles
519system.cpu.dcache.ReadReq_miss_latency::total 46959686500 # number of ReadReq miss cycles
520system.cpu.dcache.WriteReq_miss_latency::cpu.data 33959629000 # number of WriteReq miss cycles
521system.cpu.dcache.WriteReq_miss_latency::total 33959629000 # number of WriteReq miss cycles
522system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 226795500 # number of LoadLockedReq miss cycles
523system.cpu.dcache.LoadLockedReq_miss_latency::total 226795500 # number of LoadLockedReq miss cycles
524system.cpu.dcache.demand_miss_latency::cpu.data 80919315500 # number of demand (read+write) miss cycles
525system.cpu.dcache.demand_miss_latency::total 80919315500 # number of demand (read+write) miss cycles
526system.cpu.dcache.overall_miss_latency::cpu.data 80919315500 # number of overall miss cycles
527system.cpu.dcache.overall_miss_latency::total 80919315500 # number of overall miss cycles
528system.cpu.dcache.ReadReq_accesses::cpu.data 9070828 # number of ReadReq accesses(hits+misses)
529system.cpu.dcache.ReadReq_accesses::total 9070828 # number of ReadReq accesses(hits+misses)
530system.cpu.dcache.WriteReq_accesses::cpu.data 6151468 # number of WriteReq accesses(hits+misses)
531system.cpu.dcache.WriteReq_accesses::total 6151468 # number of WriteReq accesses(hits+misses)
532system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200070 # number of LoadLockedReq accesses(hits+misses)
533system.cpu.dcache.LoadLockedReq_accesses::total 200070 # number of LoadLockedReq accesses(hits+misses)
534system.cpu.dcache.StoreCondReq_accesses::cpu.data 199049 # number of StoreCondReq accesses(hits+misses)
535system.cpu.dcache.StoreCondReq_accesses::total 199049 # number of StoreCondReq accesses(hits+misses)
536system.cpu.dcache.demand_accesses::cpu.data 15222296 # number of demand (read+write) accesses
537system.cpu.dcache.demand_accesses::total 15222296 # number of demand (read+write) accesses
538system.cpu.dcache.overall_accesses::cpu.data 15222296 # number of overall (read+write) accesses
539system.cpu.dcache.overall_accesses::total 15222296 # number of overall (read+write) accesses
540system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132430 # miss rate for ReadReq accesses
541system.cpu.dcache.ReadReq_miss_rate::total 0.132430 # miss rate for ReadReq accesses
542system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093417 # miss rate for WriteReq accesses
543system.cpu.dcache.WriteReq_miss_rate::total 0.093417 # miss rate for WriteReq accesses
544system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082821 # miss rate for LoadLockedReq accesses
545system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082821 # miss rate for LoadLockedReq accesses
546system.cpu.dcache.demand_miss_rate::cpu.data 0.116665 # miss rate for demand accesses
547system.cpu.dcache.demand_miss_rate::total 0.116665 # miss rate for demand accesses
548system.cpu.dcache.overall_miss_rate::cpu.data 0.116665 # miss rate for overall accesses
549system.cpu.dcache.overall_miss_rate::total 0.116665 # miss rate for overall accesses
550system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.253256 # average ReadReq miss latency
551system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.253256 # average ReadReq miss latency
552system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59096.195945 # average WriteReq miss latency
553system.cpu.dcache.WriteReq_avg_miss_latency::total 59096.195945 # average WriteReq miss latency
554system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13687.115269 # average LoadLockedReq miss latency
555system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13687.115269 # average LoadLockedReq miss latency
556system.cpu.dcache.demand_avg_miss_latency::cpu.data 45565.166284 # average overall miss latency
557system.cpu.dcache.demand_avg_miss_latency::total 45565.166284 # average overall miss latency
558system.cpu.dcache.overall_avg_miss_latency::cpu.data 45565.166284 # average overall miss latency
559system.cpu.dcache.overall_avg_miss_latency::total 45565.166284 # average overall miss latency
560system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
561system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
562system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
563system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
564system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
565system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
566system.cpu.dcache.fast_writes 0 # number of fast writes performed
567system.cpu.dcache.cache_copies 0 # number of cache copies performed
| |
568system.cpu.dcache.writebacks::writebacks 837991 # number of writebacks
569system.cpu.dcache.writebacks::total 837991 # number of writebacks
570system.cpu.dcache.ReadReq_mshr_hits::cpu.data 126783 # number of ReadReq MSHR hits
571system.cpu.dcache.ReadReq_mshr_hits::total 126783 # number of ReadReq MSHR hits
572system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270556 # number of WriteReq MSHR hits
573system.cpu.dcache.WriteReq_mshr_hits::total 270556 # number of WriteReq MSHR hits
574system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
575system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
576system.cpu.dcache.demand_mshr_hits::cpu.data 397339 # number of demand (read+write) MSHR hits
577system.cpu.dcache.demand_mshr_hits::total 397339 # number of demand (read+write) MSHR hits
578system.cpu.dcache.overall_mshr_hits::cpu.data 397339 # number of overall MSHR hits
579system.cpu.dcache.overall_mshr_hits::total 397339 # number of overall MSHR hits
580system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074470 # number of ReadReq MSHR misses
581system.cpu.dcache.ReadReq_mshr_misses::total 1074470 # number of ReadReq MSHR misses
582system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304094 # number of WriteReq MSHR misses
583system.cpu.dcache.WriteReq_mshr_misses::total 304094 # number of WriteReq MSHR misses
584system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16567 # number of LoadLockedReq MSHR misses
585system.cpu.dcache.LoadLockedReq_mshr_misses::total 16567 # number of LoadLockedReq MSHR misses
586system.cpu.dcache.demand_mshr_misses::cpu.data 1378564 # number of demand (read+write) MSHR misses
587system.cpu.dcache.demand_mshr_misses::total 1378564 # number of demand (read+write) MSHR misses
588system.cpu.dcache.overall_mshr_misses::cpu.data 1378564 # number of overall MSHR misses
589system.cpu.dcache.overall_mshr_misses::total 1378564 # number of overall MSHR misses
590system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
591system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
592system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable
593system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable
594system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses
595system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses
596system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43809627000 # number of ReadReq MSHR miss cycles
597system.cpu.dcache.ReadReq_mshr_miss_latency::total 43809627000 # number of ReadReq MSHR miss cycles
598system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17274972500 # number of WriteReq MSHR miss cycles
599system.cpu.dcache.WriteReq_mshr_miss_latency::total 17274972500 # number of WriteReq MSHR miss cycles
600system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 209962500 # number of LoadLockedReq MSHR miss cycles
601system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 209962500 # number of LoadLockedReq MSHR miss cycles
602system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61084599500 # number of demand (read+write) MSHR miss cycles
603system.cpu.dcache.demand_mshr_miss_latency::total 61084599500 # number of demand (read+write) MSHR miss cycles
604system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61084599500 # number of overall MSHR miss cycles
605system.cpu.dcache.overall_mshr_miss_latency::total 61084599500 # number of overall MSHR miss cycles
606system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528608000 # number of ReadReq MSHR uncacheable cycles
607system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528608000 # number of ReadReq MSHR uncacheable cycles
| 566system.cpu.dcache.writebacks::writebacks 837991 # number of writebacks
567system.cpu.dcache.writebacks::total 837991 # number of writebacks
568system.cpu.dcache.ReadReq_mshr_hits::cpu.data 126783 # number of ReadReq MSHR hits
569system.cpu.dcache.ReadReq_mshr_hits::total 126783 # number of ReadReq MSHR hits
570system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270556 # number of WriteReq MSHR hits
571system.cpu.dcache.WriteReq_mshr_hits::total 270556 # number of WriteReq MSHR hits
572system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
573system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
574system.cpu.dcache.demand_mshr_hits::cpu.data 397339 # number of demand (read+write) MSHR hits
575system.cpu.dcache.demand_mshr_hits::total 397339 # number of demand (read+write) MSHR hits
576system.cpu.dcache.overall_mshr_hits::cpu.data 397339 # number of overall MSHR hits
577system.cpu.dcache.overall_mshr_hits::total 397339 # number of overall MSHR hits
578system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074470 # number of ReadReq MSHR misses
579system.cpu.dcache.ReadReq_mshr_misses::total 1074470 # number of ReadReq MSHR misses
580system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304094 # number of WriteReq MSHR misses
581system.cpu.dcache.WriteReq_mshr_misses::total 304094 # number of WriteReq MSHR misses
582system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16567 # number of LoadLockedReq MSHR misses
583system.cpu.dcache.LoadLockedReq_mshr_misses::total 16567 # number of LoadLockedReq MSHR misses
584system.cpu.dcache.demand_mshr_misses::cpu.data 1378564 # number of demand (read+write) MSHR misses
585system.cpu.dcache.demand_mshr_misses::total 1378564 # number of demand (read+write) MSHR misses
586system.cpu.dcache.overall_mshr_misses::cpu.data 1378564 # number of overall MSHR misses
587system.cpu.dcache.overall_mshr_misses::total 1378564 # number of overall MSHR misses
588system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
589system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
590system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable
591system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable
592system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses
593system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses
594system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43809627000 # number of ReadReq MSHR miss cycles
595system.cpu.dcache.ReadReq_mshr_miss_latency::total 43809627000 # number of ReadReq MSHR miss cycles
596system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17274972500 # number of WriteReq MSHR miss cycles
597system.cpu.dcache.WriteReq_mshr_miss_latency::total 17274972500 # number of WriteReq MSHR miss cycles
598system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 209962500 # number of LoadLockedReq MSHR miss cycles
599system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 209962500 # number of LoadLockedReq MSHR miss cycles
600system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61084599500 # number of demand (read+write) MSHR miss cycles
601system.cpu.dcache.demand_mshr_miss_latency::total 61084599500 # number of demand (read+write) MSHR miss cycles
602system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61084599500 # number of overall MSHR miss cycles
603system.cpu.dcache.overall_mshr_miss_latency::total 61084599500 # number of overall MSHR miss cycles
604system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528608000 # number of ReadReq MSHR uncacheable cycles
605system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528608000 # number of ReadReq MSHR uncacheable cycles
|
608system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2161966000 # number of WriteReq MSHR uncacheable cycles
609system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2161966000 # number of WriteReq MSHR uncacheable cycles
610system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3690574000 # number of overall MSHR uncacheable cycles
611system.cpu.dcache.overall_mshr_uncacheable_latency::total 3690574000 # number of overall MSHR uncacheable cycles
| 606system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528608000 # number of overall MSHR uncacheable cycles
607system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528608000 # number of overall MSHR uncacheable cycles
|
612system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118453 # mshr miss rate for ReadReq accesses
613system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118453 # mshr miss rate for ReadReq accesses
614system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049434 # mshr miss rate for WriteReq accesses
615system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049434 # mshr miss rate for WriteReq accesses
616system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082806 # mshr miss rate for LoadLockedReq accesses
617system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082806 # mshr miss rate for LoadLockedReq accesses
618system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090562 # mshr miss rate for demand accesses
619system.cpu.dcache.demand_mshr_miss_rate::total 0.090562 # mshr miss rate for demand accesses
620system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090562 # mshr miss rate for overall accesses
621system.cpu.dcache.overall_mshr_miss_rate::total 0.090562 # mshr miss rate for overall accesses
622system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40773.243553 # average ReadReq mshr miss latency
623system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40773.243553 # average ReadReq mshr miss latency
624system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56808.001802 # average WriteReq mshr miss latency
625system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56808.001802 # average WriteReq mshr miss latency
626system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12673.537756 # average LoadLockedReq mshr miss latency
627system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12673.537756 # average LoadLockedReq mshr miss latency
628system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency
629system.cpu.dcache.demand_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency
630system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency
631system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency
632system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978 # average ReadReq mshr uncacheable latency
633system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency
| 608system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118453 # mshr miss rate for ReadReq accesses
609system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118453 # mshr miss rate for ReadReq accesses
610system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049434 # mshr miss rate for WriteReq accesses
611system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049434 # mshr miss rate for WriteReq accesses
612system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082806 # mshr miss rate for LoadLockedReq accesses
613system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082806 # mshr miss rate for LoadLockedReq accesses
614system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090562 # mshr miss rate for demand accesses
615system.cpu.dcache.demand_mshr_miss_rate::total 0.090562 # mshr miss rate for demand accesses
616system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090562 # mshr miss rate for overall accesses
617system.cpu.dcache.overall_mshr_miss_rate::total 0.090562 # mshr miss rate for overall accesses
618system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40773.243553 # average ReadReq mshr miss latency
619system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40773.243553 # average ReadReq mshr miss latency
620system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56808.001802 # average WriteReq mshr miss latency
621system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56808.001802 # average WriteReq mshr miss latency
622system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12673.537756 # average LoadLockedReq mshr miss latency
623system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12673.537756 # average LoadLockedReq mshr miss latency
624system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency
625system.cpu.dcache.demand_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency
626system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency
627system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency
628system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978 # average ReadReq mshr uncacheable latency
629system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency
|
634system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224666.528110 # average WriteReq mshr uncacheable latency
635system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224666.528110 # average WriteReq mshr uncacheable latency
636system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222954.993053 # average overall mshr uncacheable latency
637system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222954.993053 # average overall mshr uncacheable latency
638system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 630system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641 # average overall mshr uncacheable latency
631system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641 # average overall mshr uncacheable latency
|
639system.cpu.icache.tags.replacements 1471396 # number of replacements
640system.cpu.icache.tags.tagsinuse 508.107952 # Cycle average of tags in use
641system.cpu.icache.tags.total_refs 19138982 # Total number of references to valid blocks.
642system.cpu.icache.tags.sampled_refs 1471907 # Sample count of references to valid blocks.
643system.cpu.icache.tags.avg_refs 13.002847 # Average number of references to valid blocks.
644system.cpu.icache.tags.warmup_cycle 50134801500 # Cycle when the warmup percentage was hit.
645system.cpu.icache.tags.occ_blocks::cpu.inst 508.107952 # Average occupied blocks per requestor
646system.cpu.icache.tags.occ_percent::cpu.inst 0.992398 # Average percentage of cache occupancy
647system.cpu.icache.tags.occ_percent::total 0.992398 # Average percentage of cache occupancy
648system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
649system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
650system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
651system.cpu.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id
652system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
653system.cpu.icache.tags.tag_accesses 22083145 # Number of tag accesses
654system.cpu.icache.tags.data_accesses 22083145 # Number of data accesses
655system.cpu.icache.ReadReq_hits::cpu.inst 19138985 # number of ReadReq hits
656system.cpu.icache.ReadReq_hits::total 19138985 # number of ReadReq hits
657system.cpu.icache.demand_hits::cpu.inst 19138985 # number of demand (read+write) hits
658system.cpu.icache.demand_hits::total 19138985 # number of demand (read+write) hits
659system.cpu.icache.overall_hits::cpu.inst 19138985 # number of overall hits
660system.cpu.icache.overall_hits::total 19138985 # number of overall hits
661system.cpu.icache.ReadReq_misses::cpu.inst 1472080 # number of ReadReq misses
662system.cpu.icache.ReadReq_misses::total 1472080 # number of ReadReq misses
663system.cpu.icache.demand_misses::cpu.inst 1472080 # number of demand (read+write) misses
664system.cpu.icache.demand_misses::total 1472080 # number of demand (read+write) misses
665system.cpu.icache.overall_misses::cpu.inst 1472080 # number of overall misses
666system.cpu.icache.overall_misses::total 1472080 # number of overall misses
667system.cpu.icache.ReadReq_miss_latency::cpu.inst 21152422000 # number of ReadReq miss cycles
668system.cpu.icache.ReadReq_miss_latency::total 21152422000 # number of ReadReq miss cycles
669system.cpu.icache.demand_miss_latency::cpu.inst 21152422000 # number of demand (read+write) miss cycles
670system.cpu.icache.demand_miss_latency::total 21152422000 # number of demand (read+write) miss cycles
671system.cpu.icache.overall_miss_latency::cpu.inst 21152422000 # number of overall miss cycles
672system.cpu.icache.overall_miss_latency::total 21152422000 # number of overall miss cycles
673system.cpu.icache.ReadReq_accesses::cpu.inst 20611065 # number of ReadReq accesses(hits+misses)
674system.cpu.icache.ReadReq_accesses::total 20611065 # number of ReadReq accesses(hits+misses)
675system.cpu.icache.demand_accesses::cpu.inst 20611065 # number of demand (read+write) accesses
676system.cpu.icache.demand_accesses::total 20611065 # number of demand (read+write) accesses
677system.cpu.icache.overall_accesses::cpu.inst 20611065 # number of overall (read+write) accesses
678system.cpu.icache.overall_accesses::total 20611065 # number of overall (read+write) accesses
679system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071422 # miss rate for ReadReq accesses
680system.cpu.icache.ReadReq_miss_rate::total 0.071422 # miss rate for ReadReq accesses
681system.cpu.icache.demand_miss_rate::cpu.inst 0.071422 # miss rate for demand accesses
682system.cpu.icache.demand_miss_rate::total 0.071422 # miss rate for demand accesses
683system.cpu.icache.overall_miss_rate::cpu.inst 0.071422 # miss rate for overall accesses
684system.cpu.icache.overall_miss_rate::total 0.071422 # miss rate for overall accesses
685system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14369.070974 # average ReadReq miss latency
686system.cpu.icache.ReadReq_avg_miss_latency::total 14369.070974 # average ReadReq miss latency
687system.cpu.icache.demand_avg_miss_latency::cpu.inst 14369.070974 # average overall miss latency
688system.cpu.icache.demand_avg_miss_latency::total 14369.070974 # average overall miss latency
689system.cpu.icache.overall_avg_miss_latency::cpu.inst 14369.070974 # average overall miss latency
690system.cpu.icache.overall_avg_miss_latency::total 14369.070974 # average overall miss latency
691system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
692system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
693system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
694system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
695system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
696system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
| 632system.cpu.icache.tags.replacements 1471396 # number of replacements
633system.cpu.icache.tags.tagsinuse 508.107952 # Cycle average of tags in use
634system.cpu.icache.tags.total_refs 19138982 # Total number of references to valid blocks.
635system.cpu.icache.tags.sampled_refs 1471907 # Sample count of references to valid blocks.
636system.cpu.icache.tags.avg_refs 13.002847 # Average number of references to valid blocks.
637system.cpu.icache.tags.warmup_cycle 50134801500 # Cycle when the warmup percentage was hit.
638system.cpu.icache.tags.occ_blocks::cpu.inst 508.107952 # Average occupied blocks per requestor
639system.cpu.icache.tags.occ_percent::cpu.inst 0.992398 # Average percentage of cache occupancy
640system.cpu.icache.tags.occ_percent::total 0.992398 # Average percentage of cache occupancy
641system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
642system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
643system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
644system.cpu.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id
645system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
646system.cpu.icache.tags.tag_accesses 22083145 # Number of tag accesses
647system.cpu.icache.tags.data_accesses 22083145 # Number of data accesses
648system.cpu.icache.ReadReq_hits::cpu.inst 19138985 # number of ReadReq hits
649system.cpu.icache.ReadReq_hits::total 19138985 # number of ReadReq hits
650system.cpu.icache.demand_hits::cpu.inst 19138985 # number of demand (read+write) hits
651system.cpu.icache.demand_hits::total 19138985 # number of demand (read+write) hits
652system.cpu.icache.overall_hits::cpu.inst 19138985 # number of overall hits
653system.cpu.icache.overall_hits::total 19138985 # number of overall hits
654system.cpu.icache.ReadReq_misses::cpu.inst 1472080 # number of ReadReq misses
655system.cpu.icache.ReadReq_misses::total 1472080 # number of ReadReq misses
656system.cpu.icache.demand_misses::cpu.inst 1472080 # number of demand (read+write) misses
657system.cpu.icache.demand_misses::total 1472080 # number of demand (read+write) misses
658system.cpu.icache.overall_misses::cpu.inst 1472080 # number of overall misses
659system.cpu.icache.overall_misses::total 1472080 # number of overall misses
660system.cpu.icache.ReadReq_miss_latency::cpu.inst 21152422000 # number of ReadReq miss cycles
661system.cpu.icache.ReadReq_miss_latency::total 21152422000 # number of ReadReq miss cycles
662system.cpu.icache.demand_miss_latency::cpu.inst 21152422000 # number of demand (read+write) miss cycles
663system.cpu.icache.demand_miss_latency::total 21152422000 # number of demand (read+write) miss cycles
664system.cpu.icache.overall_miss_latency::cpu.inst 21152422000 # number of overall miss cycles
665system.cpu.icache.overall_miss_latency::total 21152422000 # number of overall miss cycles
666system.cpu.icache.ReadReq_accesses::cpu.inst 20611065 # number of ReadReq accesses(hits+misses)
667system.cpu.icache.ReadReq_accesses::total 20611065 # number of ReadReq accesses(hits+misses)
668system.cpu.icache.demand_accesses::cpu.inst 20611065 # number of demand (read+write) accesses
669system.cpu.icache.demand_accesses::total 20611065 # number of demand (read+write) accesses
670system.cpu.icache.overall_accesses::cpu.inst 20611065 # number of overall (read+write) accesses
671system.cpu.icache.overall_accesses::total 20611065 # number of overall (read+write) accesses
672system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071422 # miss rate for ReadReq accesses
673system.cpu.icache.ReadReq_miss_rate::total 0.071422 # miss rate for ReadReq accesses
674system.cpu.icache.demand_miss_rate::cpu.inst 0.071422 # miss rate for demand accesses
675system.cpu.icache.demand_miss_rate::total 0.071422 # miss rate for demand accesses
676system.cpu.icache.overall_miss_rate::cpu.inst 0.071422 # miss rate for overall accesses
677system.cpu.icache.overall_miss_rate::total 0.071422 # miss rate for overall accesses
678system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14369.070974 # average ReadReq miss latency
679system.cpu.icache.ReadReq_avg_miss_latency::total 14369.070974 # average ReadReq miss latency
680system.cpu.icache.demand_avg_miss_latency::cpu.inst 14369.070974 # average overall miss latency
681system.cpu.icache.demand_avg_miss_latency::total 14369.070974 # average overall miss latency
682system.cpu.icache.overall_avg_miss_latency::cpu.inst 14369.070974 # average overall miss latency
683system.cpu.icache.overall_avg_miss_latency::total 14369.070974 # average overall miss latency
684system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
685system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
686system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
687system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
688system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
689system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
697system.cpu.icache.fast_writes 0 # number of fast writes performed
698system.cpu.icache.cache_copies 0 # number of cache copies performed
| |
699system.cpu.icache.writebacks::writebacks 1471396 # number of writebacks
700system.cpu.icache.writebacks::total 1471396 # number of writebacks
701system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1472080 # number of ReadReq MSHR misses
702system.cpu.icache.ReadReq_mshr_misses::total 1472080 # number of ReadReq MSHR misses
703system.cpu.icache.demand_mshr_misses::cpu.inst 1472080 # number of demand (read+write) MSHR misses
704system.cpu.icache.demand_mshr_misses::total 1472080 # number of demand (read+write) MSHR misses
705system.cpu.icache.overall_mshr_misses::cpu.inst 1472080 # number of overall MSHR misses
706system.cpu.icache.overall_mshr_misses::total 1472080 # number of overall MSHR misses
707system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19680342000 # number of ReadReq MSHR miss cycles
708system.cpu.icache.ReadReq_mshr_miss_latency::total 19680342000 # number of ReadReq MSHR miss cycles
709system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19680342000 # number of demand (read+write) MSHR miss cycles
710system.cpu.icache.demand_mshr_miss_latency::total 19680342000 # number of demand (read+write) MSHR miss cycles
711system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19680342000 # number of overall MSHR miss cycles
712system.cpu.icache.overall_mshr_miss_latency::total 19680342000 # number of overall MSHR miss cycles
713system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for ReadReq accesses
714system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071422 # mshr miss rate for ReadReq accesses
715system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for demand accesses
716system.cpu.icache.demand_mshr_miss_rate::total 0.071422 # mshr miss rate for demand accesses
717system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for overall accesses
718system.cpu.icache.overall_mshr_miss_rate::total 0.071422 # mshr miss rate for overall accesses
719system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13369.070974 # average ReadReq mshr miss latency
720system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13369.070974 # average ReadReq mshr miss latency
721system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency
722system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency
723system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency
724system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency
| 690system.cpu.icache.writebacks::writebacks 1471396 # number of writebacks
691system.cpu.icache.writebacks::total 1471396 # number of writebacks
692system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1472080 # number of ReadReq MSHR misses
693system.cpu.icache.ReadReq_mshr_misses::total 1472080 # number of ReadReq MSHR misses
694system.cpu.icache.demand_mshr_misses::cpu.inst 1472080 # number of demand (read+write) MSHR misses
695system.cpu.icache.demand_mshr_misses::total 1472080 # number of demand (read+write) MSHR misses
696system.cpu.icache.overall_mshr_misses::cpu.inst 1472080 # number of overall MSHR misses
697system.cpu.icache.overall_mshr_misses::total 1472080 # number of overall MSHR misses
698system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19680342000 # number of ReadReq MSHR miss cycles
699system.cpu.icache.ReadReq_mshr_miss_latency::total 19680342000 # number of ReadReq MSHR miss cycles
700system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19680342000 # number of demand (read+write) MSHR miss cycles
701system.cpu.icache.demand_mshr_miss_latency::total 19680342000 # number of demand (read+write) MSHR miss cycles
702system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19680342000 # number of overall MSHR miss cycles
703system.cpu.icache.overall_mshr_miss_latency::total 19680342000 # number of overall MSHR miss cycles
704system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for ReadReq accesses
705system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071422 # mshr miss rate for ReadReq accesses
706system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for demand accesses
707system.cpu.icache.demand_mshr_miss_rate::total 0.071422 # mshr miss rate for demand accesses
708system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for overall accesses
709system.cpu.icache.overall_mshr_miss_rate::total 0.071422 # mshr miss rate for overall accesses
710system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13369.070974 # average ReadReq mshr miss latency
711system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13369.070974 # average ReadReq mshr miss latency
712system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency
713system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency
714system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency
715system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency
|
725system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
| |
726system.cpu.l2cache.tags.replacements 339491 # number of replacements
727system.cpu.l2cache.tags.tagsinuse 65257.604073 # Cycle average of tags in use
728system.cpu.l2cache.tags.total_refs 5020229 # Total number of references to valid blocks.
729system.cpu.l2cache.tags.sampled_refs 404654 # Sample count of references to valid blocks.
730system.cpu.l2cache.tags.avg_refs 12.406226 # Average number of references to valid blocks.
731system.cpu.l2cache.tags.warmup_cycle 9688326000 # Cycle when the warmup percentage was hit.
732system.cpu.l2cache.tags.occ_blocks::writebacks 54061.905720 # Average occupied blocks per requestor
733system.cpu.l2cache.tags.occ_blocks::cpu.inst 5741.199661 # Average occupied blocks per requestor
734system.cpu.l2cache.tags.occ_blocks::cpu.data 5454.498692 # Average occupied blocks per requestor
735system.cpu.l2cache.tags.occ_percent::writebacks 0.824919 # Average percentage of cache occupancy
736system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087604 # Average percentage of cache occupancy
737system.cpu.l2cache.tags.occ_percent::cpu.data 0.083229 # Average percentage of cache occupancy
738system.cpu.l2cache.tags.occ_percent::total 0.995752 # Average percentage of cache occupancy
739system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
740system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
741system.cpu.l2cache.tags.age_task_id_blocks_1024::1 883 # Occupied blocks per task id
742system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5606 # Occupied blocks per task id
743system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2934 # Occupied blocks per task id
744system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55510 # Occupied blocks per task id
745system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
746system.cpu.l2cache.tags.tag_accesses 46558497 # Number of tag accesses
747system.cpu.l2cache.tags.data_accesses 46558497 # Number of data accesses
748system.cpu.l2cache.WritebackDirty_hits::writebacks 837991 # number of WritebackDirty hits
749system.cpu.l2cache.WritebackDirty_hits::total 837991 # number of WritebackDirty hits
750system.cpu.l2cache.WritebackClean_hits::writebacks 1470820 # number of WritebackClean hits
751system.cpu.l2cache.WritebackClean_hits::total 1470820 # number of WritebackClean hits
752system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits
753system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits
754system.cpu.l2cache.ReadExReq_hits::cpu.data 187526 # number of ReadExReq hits
755system.cpu.l2cache.ReadExReq_hits::total 187526 # number of ReadExReq hits
756system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1455685 # number of ReadCleanReq hits
757system.cpu.l2cache.ReadCleanReq_hits::total 1455685 # number of ReadCleanReq hits
758system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818815 # number of ReadSharedReq hits
759system.cpu.l2cache.ReadSharedReq_hits::total 818815 # number of ReadSharedReq hits
760system.cpu.l2cache.demand_hits::cpu.inst 1455685 # number of demand (read+write) hits
761system.cpu.l2cache.demand_hits::cpu.data 1006341 # number of demand (read+write) hits
762system.cpu.l2cache.demand_hits::total 2462026 # number of demand (read+write) hits
763system.cpu.l2cache.overall_hits::cpu.inst 1455685 # number of overall hits
764system.cpu.l2cache.overall_hits::cpu.data 1006341 # number of overall hits
765system.cpu.l2cache.overall_hits::total 2462026 # number of overall hits
766system.cpu.l2cache.UpgradeReq_misses::cpu.data 15 # number of UpgradeReq misses
767system.cpu.l2cache.UpgradeReq_misses::total 15 # number of UpgradeReq misses
768system.cpu.l2cache.ReadExReq_misses::cpu.data 116580 # number of ReadExReq misses
769system.cpu.l2cache.ReadExReq_misses::total 116580 # number of ReadExReq misses
770system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16339 # number of ReadCleanReq misses
771system.cpu.l2cache.ReadCleanReq_misses::total 16339 # number of ReadCleanReq misses
772system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272190 # number of ReadSharedReq misses
773system.cpu.l2cache.ReadSharedReq_misses::total 272190 # number of ReadSharedReq misses
774system.cpu.l2cache.demand_misses::cpu.inst 16339 # number of demand (read+write) misses
775system.cpu.l2cache.demand_misses::cpu.data 388770 # number of demand (read+write) misses
776system.cpu.l2cache.demand_misses::total 405109 # number of demand (read+write) misses
777system.cpu.l2cache.overall_misses::cpu.inst 16339 # number of overall misses
778system.cpu.l2cache.overall_misses::cpu.data 388770 # number of overall misses
779system.cpu.l2cache.overall_misses::total 405109 # number of overall misses
780system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 396000 # number of UpgradeReq miss cycles
781system.cpu.l2cache.UpgradeReq_miss_latency::total 396000 # number of UpgradeReq miss cycles
782system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14843351000 # number of ReadExReq miss cycles
783system.cpu.l2cache.ReadExReq_miss_latency::total 14843351000 # number of ReadExReq miss cycles
784system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2147420500 # number of ReadCleanReq miss cycles
785system.cpu.l2cache.ReadCleanReq_miss_latency::total 2147420500 # number of ReadCleanReq miss cycles
786system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33672693000 # number of ReadSharedReq miss cycles
787system.cpu.l2cache.ReadSharedReq_miss_latency::total 33672693000 # number of ReadSharedReq miss cycles
788system.cpu.l2cache.demand_miss_latency::cpu.inst 2147420500 # number of demand (read+write) miss cycles
789system.cpu.l2cache.demand_miss_latency::cpu.data 48516044000 # number of demand (read+write) miss cycles
790system.cpu.l2cache.demand_miss_latency::total 50663464500 # number of demand (read+write) miss cycles
791system.cpu.l2cache.overall_miss_latency::cpu.inst 2147420500 # number of overall miss cycles
792system.cpu.l2cache.overall_miss_latency::cpu.data 48516044000 # number of overall miss cycles
793system.cpu.l2cache.overall_miss_latency::total 50663464500 # number of overall miss cycles
794system.cpu.l2cache.WritebackDirty_accesses::writebacks 837991 # number of WritebackDirty accesses(hits+misses)
795system.cpu.l2cache.WritebackDirty_accesses::total 837991 # number of WritebackDirty accesses(hits+misses)
796system.cpu.l2cache.WritebackClean_accesses::writebacks 1470820 # number of WritebackClean accesses(hits+misses)
797system.cpu.l2cache.WritebackClean_accesses::total 1470820 # number of WritebackClean accesses(hits+misses)
798system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses)
799system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses)
800system.cpu.l2cache.ReadExReq_accesses::cpu.data 304106 # number of ReadExReq accesses(hits+misses)
801system.cpu.l2cache.ReadExReq_accesses::total 304106 # number of ReadExReq accesses(hits+misses)
802system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1472024 # number of ReadCleanReq accesses(hits+misses)
803system.cpu.l2cache.ReadCleanReq_accesses::total 1472024 # number of ReadCleanReq accesses(hits+misses)
804system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091005 # number of ReadSharedReq accesses(hits+misses)
805system.cpu.l2cache.ReadSharedReq_accesses::total 1091005 # number of ReadSharedReq accesses(hits+misses)
806system.cpu.l2cache.demand_accesses::cpu.inst 1472024 # number of demand (read+write) accesses
807system.cpu.l2cache.demand_accesses::cpu.data 1395111 # number of demand (read+write) accesses
808system.cpu.l2cache.demand_accesses::total 2867135 # number of demand (read+write) accesses
809system.cpu.l2cache.overall_accesses::cpu.inst 1472024 # number of overall (read+write) accesses
810system.cpu.l2cache.overall_accesses::cpu.data 1395111 # number of overall (read+write) accesses
811system.cpu.l2cache.overall_accesses::total 2867135 # number of overall (read+write) accesses
812system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
813system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
814system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383353 # miss rate for ReadExReq accesses
815system.cpu.l2cache.ReadExReq_miss_rate::total 0.383353 # miss rate for ReadExReq accesses
816system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011100 # miss rate for ReadCleanReq accesses
817system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011100 # miss rate for ReadCleanReq accesses
818system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249486 # miss rate for ReadSharedReq accesses
819system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249486 # miss rate for ReadSharedReq accesses
820system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011100 # miss rate for demand accesses
821system.cpu.l2cache.demand_miss_rate::cpu.data 0.278666 # miss rate for demand accesses
822system.cpu.l2cache.demand_miss_rate::total 0.141294 # miss rate for demand accesses
823system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011100 # miss rate for overall accesses
824system.cpu.l2cache.overall_miss_rate::cpu.data 0.278666 # miss rate for overall accesses
825system.cpu.l2cache.overall_miss_rate::total 0.141294 # miss rate for overall accesses
826system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 26400 # average UpgradeReq miss latency
827system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 26400 # average UpgradeReq miss latency
828system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127323.305884 # average ReadExReq miss latency
829system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127323.305884 # average ReadExReq miss latency
830system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131429.126630 # average ReadCleanReq miss latency
831system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131429.126630 # average ReadCleanReq miss latency
832system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123710.250193 # average ReadSharedReq miss latency
833system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123710.250193 # average ReadSharedReq miss latency
834system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131429.126630 # average overall miss latency
835system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124793.692929 # average overall miss latency
836system.cpu.l2cache.demand_avg_miss_latency::total 125061.315597 # average overall miss latency
837system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131429.126630 # average overall miss latency
838system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124793.692929 # average overall miss latency
839system.cpu.l2cache.overall_avg_miss_latency::total 125061.315597 # average overall miss latency
840system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
841system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
842system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
843system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
844system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
845system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
| 716system.cpu.l2cache.tags.replacements 339491 # number of replacements
717system.cpu.l2cache.tags.tagsinuse 65257.604073 # Cycle average of tags in use
718system.cpu.l2cache.tags.total_refs 5020229 # Total number of references to valid blocks.
719system.cpu.l2cache.tags.sampled_refs 404654 # Sample count of references to valid blocks.
720system.cpu.l2cache.tags.avg_refs 12.406226 # Average number of references to valid blocks.
721system.cpu.l2cache.tags.warmup_cycle 9688326000 # Cycle when the warmup percentage was hit.
722system.cpu.l2cache.tags.occ_blocks::writebacks 54061.905720 # Average occupied blocks per requestor
723system.cpu.l2cache.tags.occ_blocks::cpu.inst 5741.199661 # Average occupied blocks per requestor
724system.cpu.l2cache.tags.occ_blocks::cpu.data 5454.498692 # Average occupied blocks per requestor
725system.cpu.l2cache.tags.occ_percent::writebacks 0.824919 # Average percentage of cache occupancy
726system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087604 # Average percentage of cache occupancy
727system.cpu.l2cache.tags.occ_percent::cpu.data 0.083229 # Average percentage of cache occupancy
728system.cpu.l2cache.tags.occ_percent::total 0.995752 # Average percentage of cache occupancy
729system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
730system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
731system.cpu.l2cache.tags.age_task_id_blocks_1024::1 883 # Occupied blocks per task id
732system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5606 # Occupied blocks per task id
733system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2934 # Occupied blocks per task id
734system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55510 # Occupied blocks per task id
735system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
736system.cpu.l2cache.tags.tag_accesses 46558497 # Number of tag accesses
737system.cpu.l2cache.tags.data_accesses 46558497 # Number of data accesses
738system.cpu.l2cache.WritebackDirty_hits::writebacks 837991 # number of WritebackDirty hits
739system.cpu.l2cache.WritebackDirty_hits::total 837991 # number of WritebackDirty hits
740system.cpu.l2cache.WritebackClean_hits::writebacks 1470820 # number of WritebackClean hits
741system.cpu.l2cache.WritebackClean_hits::total 1470820 # number of WritebackClean hits
742system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits
743system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits
744system.cpu.l2cache.ReadExReq_hits::cpu.data 187526 # number of ReadExReq hits
745system.cpu.l2cache.ReadExReq_hits::total 187526 # number of ReadExReq hits
746system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1455685 # number of ReadCleanReq hits
747system.cpu.l2cache.ReadCleanReq_hits::total 1455685 # number of ReadCleanReq hits
748system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818815 # number of ReadSharedReq hits
749system.cpu.l2cache.ReadSharedReq_hits::total 818815 # number of ReadSharedReq hits
750system.cpu.l2cache.demand_hits::cpu.inst 1455685 # number of demand (read+write) hits
751system.cpu.l2cache.demand_hits::cpu.data 1006341 # number of demand (read+write) hits
752system.cpu.l2cache.demand_hits::total 2462026 # number of demand (read+write) hits
753system.cpu.l2cache.overall_hits::cpu.inst 1455685 # number of overall hits
754system.cpu.l2cache.overall_hits::cpu.data 1006341 # number of overall hits
755system.cpu.l2cache.overall_hits::total 2462026 # number of overall hits
756system.cpu.l2cache.UpgradeReq_misses::cpu.data 15 # number of UpgradeReq misses
757system.cpu.l2cache.UpgradeReq_misses::total 15 # number of UpgradeReq misses
758system.cpu.l2cache.ReadExReq_misses::cpu.data 116580 # number of ReadExReq misses
759system.cpu.l2cache.ReadExReq_misses::total 116580 # number of ReadExReq misses
760system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16339 # number of ReadCleanReq misses
761system.cpu.l2cache.ReadCleanReq_misses::total 16339 # number of ReadCleanReq misses
762system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272190 # number of ReadSharedReq misses
763system.cpu.l2cache.ReadSharedReq_misses::total 272190 # number of ReadSharedReq misses
764system.cpu.l2cache.demand_misses::cpu.inst 16339 # number of demand (read+write) misses
765system.cpu.l2cache.demand_misses::cpu.data 388770 # number of demand (read+write) misses
766system.cpu.l2cache.demand_misses::total 405109 # number of demand (read+write) misses
767system.cpu.l2cache.overall_misses::cpu.inst 16339 # number of overall misses
768system.cpu.l2cache.overall_misses::cpu.data 388770 # number of overall misses
769system.cpu.l2cache.overall_misses::total 405109 # number of overall misses
770system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 396000 # number of UpgradeReq miss cycles
771system.cpu.l2cache.UpgradeReq_miss_latency::total 396000 # number of UpgradeReq miss cycles
772system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14843351000 # number of ReadExReq miss cycles
773system.cpu.l2cache.ReadExReq_miss_latency::total 14843351000 # number of ReadExReq miss cycles
774system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2147420500 # number of ReadCleanReq miss cycles
775system.cpu.l2cache.ReadCleanReq_miss_latency::total 2147420500 # number of ReadCleanReq miss cycles
776system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33672693000 # number of ReadSharedReq miss cycles
777system.cpu.l2cache.ReadSharedReq_miss_latency::total 33672693000 # number of ReadSharedReq miss cycles
778system.cpu.l2cache.demand_miss_latency::cpu.inst 2147420500 # number of demand (read+write) miss cycles
779system.cpu.l2cache.demand_miss_latency::cpu.data 48516044000 # number of demand (read+write) miss cycles
780system.cpu.l2cache.demand_miss_latency::total 50663464500 # number of demand (read+write) miss cycles
781system.cpu.l2cache.overall_miss_latency::cpu.inst 2147420500 # number of overall miss cycles
782system.cpu.l2cache.overall_miss_latency::cpu.data 48516044000 # number of overall miss cycles
783system.cpu.l2cache.overall_miss_latency::total 50663464500 # number of overall miss cycles
784system.cpu.l2cache.WritebackDirty_accesses::writebacks 837991 # number of WritebackDirty accesses(hits+misses)
785system.cpu.l2cache.WritebackDirty_accesses::total 837991 # number of WritebackDirty accesses(hits+misses)
786system.cpu.l2cache.WritebackClean_accesses::writebacks 1470820 # number of WritebackClean accesses(hits+misses)
787system.cpu.l2cache.WritebackClean_accesses::total 1470820 # number of WritebackClean accesses(hits+misses)
788system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses)
789system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses)
790system.cpu.l2cache.ReadExReq_accesses::cpu.data 304106 # number of ReadExReq accesses(hits+misses)
791system.cpu.l2cache.ReadExReq_accesses::total 304106 # number of ReadExReq accesses(hits+misses)
792system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1472024 # number of ReadCleanReq accesses(hits+misses)
793system.cpu.l2cache.ReadCleanReq_accesses::total 1472024 # number of ReadCleanReq accesses(hits+misses)
794system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091005 # number of ReadSharedReq accesses(hits+misses)
795system.cpu.l2cache.ReadSharedReq_accesses::total 1091005 # number of ReadSharedReq accesses(hits+misses)
796system.cpu.l2cache.demand_accesses::cpu.inst 1472024 # number of demand (read+write) accesses
797system.cpu.l2cache.demand_accesses::cpu.data 1395111 # number of demand (read+write) accesses
798system.cpu.l2cache.demand_accesses::total 2867135 # number of demand (read+write) accesses
799system.cpu.l2cache.overall_accesses::cpu.inst 1472024 # number of overall (read+write) accesses
800system.cpu.l2cache.overall_accesses::cpu.data 1395111 # number of overall (read+write) accesses
801system.cpu.l2cache.overall_accesses::total 2867135 # number of overall (read+write) accesses
802system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
803system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
804system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383353 # miss rate for ReadExReq accesses
805system.cpu.l2cache.ReadExReq_miss_rate::total 0.383353 # miss rate for ReadExReq accesses
806system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011100 # miss rate for ReadCleanReq accesses
807system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011100 # miss rate for ReadCleanReq accesses
808system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249486 # miss rate for ReadSharedReq accesses
809system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249486 # miss rate for ReadSharedReq accesses
810system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011100 # miss rate for demand accesses
811system.cpu.l2cache.demand_miss_rate::cpu.data 0.278666 # miss rate for demand accesses
812system.cpu.l2cache.demand_miss_rate::total 0.141294 # miss rate for demand accesses
813system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011100 # miss rate for overall accesses
814system.cpu.l2cache.overall_miss_rate::cpu.data 0.278666 # miss rate for overall accesses
815system.cpu.l2cache.overall_miss_rate::total 0.141294 # miss rate for overall accesses
816system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 26400 # average UpgradeReq miss latency
817system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 26400 # average UpgradeReq miss latency
818system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127323.305884 # average ReadExReq miss latency
819system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127323.305884 # average ReadExReq miss latency
820system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131429.126630 # average ReadCleanReq miss latency
821system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131429.126630 # average ReadCleanReq miss latency
822system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123710.250193 # average ReadSharedReq miss latency
823system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123710.250193 # average ReadSharedReq miss latency
824system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131429.126630 # average overall miss latency
825system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124793.692929 # average overall miss latency
826system.cpu.l2cache.demand_avg_miss_latency::total 125061.315597 # average overall miss latency
827system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131429.126630 # average overall miss latency
828system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124793.692929 # average overall miss latency
829system.cpu.l2cache.overall_avg_miss_latency::total 125061.315597 # average overall miss latency
830system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
831system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
832system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
833system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
834system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
835system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
846system.cpu.l2cache.fast_writes 0 # number of fast writes performed
847system.cpu.l2cache.cache_copies 0 # number of cache copies performed
| |
848system.cpu.l2cache.writebacks::writebacks 76584 # number of writebacks
849system.cpu.l2cache.writebacks::total 76584 # number of writebacks
850system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 15 # number of UpgradeReq MSHR misses
851system.cpu.l2cache.UpgradeReq_mshr_misses::total 15 # number of UpgradeReq MSHR misses
852system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116580 # number of ReadExReq MSHR misses
853system.cpu.l2cache.ReadExReq_mshr_misses::total 116580 # number of ReadExReq MSHR misses
854system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16339 # number of ReadCleanReq MSHR misses
855system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16339 # number of ReadCleanReq MSHR misses
856system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272190 # number of ReadSharedReq MSHR misses
857system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272190 # number of ReadSharedReq MSHR misses
858system.cpu.l2cache.demand_mshr_misses::cpu.inst 16339 # number of demand (read+write) MSHR misses
859system.cpu.l2cache.demand_mshr_misses::cpu.data 388770 # number of demand (read+write) MSHR misses
860system.cpu.l2cache.demand_mshr_misses::total 405109 # number of demand (read+write) MSHR misses
861system.cpu.l2cache.overall_mshr_misses::cpu.inst 16339 # number of overall MSHR misses
862system.cpu.l2cache.overall_mshr_misses::cpu.data 388770 # number of overall MSHR misses
863system.cpu.l2cache.overall_mshr_misses::total 405109 # number of overall MSHR misses
864system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
865system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
866system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable
867system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable
868system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses
869system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses
870system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1037000 # number of UpgradeReq MSHR miss cycles
871system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1037000 # number of UpgradeReq MSHR miss cycles
872system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13677551000 # number of ReadExReq MSHR miss cycles
873system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13677551000 # number of ReadExReq MSHR miss cycles
874system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1984030500 # number of ReadCleanReq MSHR miss cycles
875system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1984030500 # number of ReadCleanReq MSHR miss cycles
876system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30953906500 # number of ReadSharedReq MSHR miss cycles
877system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30953906500 # number of ReadSharedReq MSHR miss cycles
878system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1984030500 # number of demand (read+write) MSHR miss cycles
879system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631457500 # number of demand (read+write) MSHR miss cycles
880system.cpu.l2cache.demand_mshr_miss_latency::total 46615488000 # number of demand (read+write) MSHR miss cycles
881system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1984030500 # number of overall MSHR miss cycles
882system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631457500 # number of overall MSHR miss cycles
883system.cpu.l2cache.overall_mshr_miss_latency::total 46615488000 # number of overall MSHR miss cycles
884system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1441963500 # number of ReadReq MSHR uncacheable cycles
885system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1441963500 # number of ReadReq MSHR uncacheable cycles
| 836system.cpu.l2cache.writebacks::writebacks 76584 # number of writebacks
837system.cpu.l2cache.writebacks::total 76584 # number of writebacks
838system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 15 # number of UpgradeReq MSHR misses
839system.cpu.l2cache.UpgradeReq_mshr_misses::total 15 # number of UpgradeReq MSHR misses
840system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116580 # number of ReadExReq MSHR misses
841system.cpu.l2cache.ReadExReq_mshr_misses::total 116580 # number of ReadExReq MSHR misses
842system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16339 # number of ReadCleanReq MSHR misses
843system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16339 # number of ReadCleanReq MSHR misses
844system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272190 # number of ReadSharedReq MSHR misses
845system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272190 # number of ReadSharedReq MSHR misses
846system.cpu.l2cache.demand_mshr_misses::cpu.inst 16339 # number of demand (read+write) MSHR misses
847system.cpu.l2cache.demand_mshr_misses::cpu.data 388770 # number of demand (read+write) MSHR misses
848system.cpu.l2cache.demand_mshr_misses::total 405109 # number of demand (read+write) MSHR misses
849system.cpu.l2cache.overall_mshr_misses::cpu.inst 16339 # number of overall MSHR misses
850system.cpu.l2cache.overall_mshr_misses::cpu.data 388770 # number of overall MSHR misses
851system.cpu.l2cache.overall_mshr_misses::total 405109 # number of overall MSHR misses
852system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
853system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
854system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable
855system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable
856system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses
857system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses
858system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1037000 # number of UpgradeReq MSHR miss cycles
859system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1037000 # number of UpgradeReq MSHR miss cycles
860system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13677551000 # number of ReadExReq MSHR miss cycles
861system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13677551000 # number of ReadExReq MSHR miss cycles
862system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1984030500 # number of ReadCleanReq MSHR miss cycles
863system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1984030500 # number of ReadCleanReq MSHR miss cycles
864system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30953906500 # number of ReadSharedReq MSHR miss cycles
865system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30953906500 # number of ReadSharedReq MSHR miss cycles
866system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1984030500 # number of demand (read+write) MSHR miss cycles
867system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631457500 # number of demand (read+write) MSHR miss cycles
868system.cpu.l2cache.demand_mshr_miss_latency::total 46615488000 # number of demand (read+write) MSHR miss cycles
869system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1984030500 # number of overall MSHR miss cycles
870system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631457500 # number of overall MSHR miss cycles
871system.cpu.l2cache.overall_mshr_miss_latency::total 46615488000 # number of overall MSHR miss cycles
872system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1441963500 # number of ReadReq MSHR uncacheable cycles
873system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1441963500 # number of ReadReq MSHR uncacheable cycles
|
886system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051300500 # number of WriteReq MSHR uncacheable cycles
887system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051300500 # number of WriteReq MSHR uncacheable cycles
888system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3493264000 # number of overall MSHR uncacheable cycles
889system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3493264000 # number of overall MSHR uncacheable cycles
| 874system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1441963500 # number of overall MSHR uncacheable cycles
875system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1441963500 # number of overall MSHR uncacheable cycles
|
890system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses
891system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses
892system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383353 # mshr miss rate for ReadExReq accesses
893system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383353 # mshr miss rate for ReadExReq accesses
894system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for ReadCleanReq accesses
895system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011100 # mshr miss rate for ReadCleanReq accesses
896system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249486 # mshr miss rate for ReadSharedReq accesses
897system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249486 # mshr miss rate for ReadSharedReq accesses
898system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for demand accesses
899system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278666 # mshr miss rate for demand accesses
900system.cpu.l2cache.demand_mshr_miss_rate::total 0.141294 # mshr miss rate for demand accesses
901system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for overall accesses
902system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278666 # mshr miss rate for overall accesses
903system.cpu.l2cache.overall_mshr_miss_rate::total 0.141294 # mshr miss rate for overall accesses
904system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69133.333333 # average UpgradeReq mshr miss latency
905system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69133.333333 # average UpgradeReq mshr miss latency
906system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117323.305884 # average ReadExReq mshr miss latency
907system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117323.305884 # average ReadExReq mshr miss latency
908system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121429.126630 # average ReadCleanReq mshr miss latency
909system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121429.126630 # average ReadCleanReq mshr miss latency
910system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113721.688894 # average ReadSharedReq mshr miss latency
911system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113721.688894 # average ReadSharedReq mshr miss latency
912system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency
913system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency
914system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency
915system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency
916system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency
917system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency
918system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208075.541126 # average ReadReq mshr uncacheable latency
919system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208075.541126 # average ReadReq mshr uncacheable latency
| 876system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses
877system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses
878system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383353 # mshr miss rate for ReadExReq accesses
879system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383353 # mshr miss rate for ReadExReq accesses
880system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for ReadCleanReq accesses
881system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011100 # mshr miss rate for ReadCleanReq accesses
882system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249486 # mshr miss rate for ReadSharedReq accesses
883system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249486 # mshr miss rate for ReadSharedReq accesses
884system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for demand accesses
885system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278666 # mshr miss rate for demand accesses
886system.cpu.l2cache.demand_mshr_miss_rate::total 0.141294 # mshr miss rate for demand accesses
887system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for overall accesses
888system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278666 # mshr miss rate for overall accesses
889system.cpu.l2cache.overall_mshr_miss_rate::total 0.141294 # mshr miss rate for overall accesses
890system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69133.333333 # average UpgradeReq mshr miss latency
891system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69133.333333 # average UpgradeReq mshr miss latency
892system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117323.305884 # average ReadExReq mshr miss latency
893system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117323.305884 # average ReadExReq mshr miss latency
894system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121429.126630 # average ReadCleanReq mshr miss latency
895system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121429.126630 # average ReadCleanReq mshr miss latency
896system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113721.688894 # average ReadSharedReq mshr miss latency
897system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113721.688894 # average ReadSharedReq mshr miss latency
898system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency
899system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency
900system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency
901system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency
902system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency
903system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency
904system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208075.541126 # average ReadReq mshr uncacheable latency
905system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208075.541126 # average ReadReq mshr uncacheable latency
|
920system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213166.424192 # average WriteReq mshr uncacheable latency
921system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213166.424192 # average WriteReq mshr uncacheable latency
922system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211035.099378 # average overall mshr uncacheable latency
923system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211035.099378 # average overall mshr uncacheable latency
924system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 906system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87111.913248 # average overall mshr uncacheable latency
907system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87111.913248 # average overall mshr uncacheable latency
|
925system.cpu.toL2Bus.snoop_filter.tot_requests 5733180 # Total number of requests made to the snoop filter.
926system.cpu.toL2Bus.snoop_filter.hit_single_requests 2866165 # Number of requests hitting in the snoop filter with a single holder of the requested data.
927system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
928system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter.
929system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
930system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
931system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
932system.cpu.toL2Bus.trans_dist::ReadResp 2570147 # Transaction distribution
933system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution
934system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution
935system.cpu.toL2Bus.trans_dist::WritebackDirty 956097 # Transaction distribution
936system.cpu.toL2Bus.trans_dist::WritebackClean 1471396 # Transaction distribution
937system.cpu.toL2Bus.trans_dist::CleanEvict 819662 # Transaction distribution
938system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution
939system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution
940system.cpu.toL2Bus.trans_dist::ReadExReq 304106 # Transaction distribution
941system.cpu.toL2Bus.trans_dist::ReadExResp 304106 # Transaction distribution
942system.cpu.toL2Bus.trans_dist::ReadCleanReq 1472080 # Transaction distribution
943system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091178 # Transaction distribution
944system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution
945system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
946system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4415500 # Packet count per connected master and slave (bytes)
947system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4218097 # Packet count per connected master and slave (bytes)
948system.cpu.toL2Bus.pkt_count::total 8633597 # Packet count per connected master and slave (bytes)
949system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 188378880 # Cumulative packet size per connected master and slave (bytes)
950system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142971324 # Cumulative packet size per connected master and slave (bytes)
951system.cpu.toL2Bus.pkt_size::total 331350204 # Cumulative packet size per connected master and slave (bytes)
952system.cpu.toL2Bus.snoops 423123 # Total snoops (count)
953system.cpu.toL2Bus.snoop_fanout::samples 3306675 # Request fanout histogram
954system.cpu.toL2Bus.snoop_fanout::mean 0.001025 # Request fanout histogram
955system.cpu.toL2Bus.snoop_fanout::stdev 0.031993 # Request fanout histogram
956system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
957system.cpu.toL2Bus.snoop_fanout::0 3303287 99.90% 99.90% # Request fanout histogram
958system.cpu.toL2Bus.snoop_fanout::1 3388 0.10% 100.00% # Request fanout histogram
959system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
960system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
961system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
962system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
963system.cpu.toL2Bus.snoop_fanout::total 3306675 # Request fanout histogram
964system.cpu.toL2Bus.reqLayer0.occupancy 5189065000 # Layer occupancy (ticks)
965system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
966system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks)
967system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
968system.cpu.toL2Bus.respLayer0.occupancy 2208337564 # Layer occupancy (ticks)
969system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
970system.cpu.toL2Bus.respLayer1.occupancy 2104397493 # Layer occupancy (ticks)
971system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
972system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
973system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
974system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
975system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
976system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
977system.disk0.dma_write_txs 395 # Number of DMA write transactions.
978system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
979system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
980system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
981system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
982system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
983system.disk2.dma_write_txs 1 # Number of DMA write transactions.
984system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
985system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
986system.iobus.trans_dist::WriteReq 51175 # Transaction distribution
987system.iobus.trans_dist::WriteResp 51175 # Transaction distribution
988system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes)
989system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
990system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
991system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
992system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
993system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
994system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
995system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
996system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
997system.iobus.pkt_count_system.bridge.master::total 33106 # Packet count per connected master and slave (bytes)
998system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
999system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
1000system.iobus.pkt_count::total 116556 # Packet count per connected master and slave (bytes)
1001system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20408 # Cumulative packet size per connected master and slave (bytes)
1002system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
1003system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1004system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1005system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1006system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
1007system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
1008system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1009system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1010system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes)
1011system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
1012system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
1013system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes)
1014system.iobus.reqLayer0.occupancy 5407500 # Layer occupancy (ticks)
1015system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1016system.iobus.reqLayer1.occupancy 805000 # Layer occupancy (ticks)
1017system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1018system.iobus.reqLayer2.occupancy 10000 # Layer occupancy (ticks)
1019system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1020system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks)
1021system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1022system.iobus.reqLayer22.occupancy 188500 # Layer occupancy (ticks)
1023system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1024system.iobus.reqLayer23.occupancy 14677500 # Layer occupancy (ticks)
1025system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1026system.iobus.reqLayer24.occupancy 2309500 # Layer occupancy (ticks)
1027system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1028system.iobus.reqLayer25.occupancy 6005500 # Layer occupancy (ticks)
1029system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1030system.iobus.reqLayer26.occupancy 93000 # Layer occupancy (ticks)
1031system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1032system.iobus.reqLayer27.occupancy 215722666 # Layer occupancy (ticks)
1033system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1034system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks)
1035system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1036system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
1037system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1038system.iocache.tags.replacements 41685 # number of replacements
1039system.iocache.tags.tagsinuse 1.298739 # Cycle average of tags in use
1040system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1041system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1042system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1043system.iocache.tags.warmup_cycle 1748617417000 # Cycle when the warmup percentage was hit.
1044system.iocache.tags.occ_blocks::tsunami.ide 1.298739 # Average occupied blocks per requestor
1045system.iocache.tags.occ_percent::tsunami.ide 0.081171 # Average percentage of cache occupancy
1046system.iocache.tags.occ_percent::total 0.081171 # Average percentage of cache occupancy
1047system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1048system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1049system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1050system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1051system.iocache.tags.data_accesses 375525 # Number of data accesses
1052system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1053system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1054system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1055system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
| 908system.cpu.toL2Bus.snoop_filter.tot_requests 5733180 # Total number of requests made to the snoop filter.
909system.cpu.toL2Bus.snoop_filter.hit_single_requests 2866165 # Number of requests hitting in the snoop filter with a single holder of the requested data.
910system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
911system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter.
912system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
913system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
914system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
915system.cpu.toL2Bus.trans_dist::ReadResp 2570147 # Transaction distribution
916system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution
917system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution
918system.cpu.toL2Bus.trans_dist::WritebackDirty 956097 # Transaction distribution
919system.cpu.toL2Bus.trans_dist::WritebackClean 1471396 # Transaction distribution
920system.cpu.toL2Bus.trans_dist::CleanEvict 819662 # Transaction distribution
921system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution
922system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution
923system.cpu.toL2Bus.trans_dist::ReadExReq 304106 # Transaction distribution
924system.cpu.toL2Bus.trans_dist::ReadExResp 304106 # Transaction distribution
925system.cpu.toL2Bus.trans_dist::ReadCleanReq 1472080 # Transaction distribution
926system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091178 # Transaction distribution
927system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution
928system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
929system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4415500 # Packet count per connected master and slave (bytes)
930system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4218097 # Packet count per connected master and slave (bytes)
931system.cpu.toL2Bus.pkt_count::total 8633597 # Packet count per connected master and slave (bytes)
932system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 188378880 # Cumulative packet size per connected master and slave (bytes)
933system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142971324 # Cumulative packet size per connected master and slave (bytes)
934system.cpu.toL2Bus.pkt_size::total 331350204 # Cumulative packet size per connected master and slave (bytes)
935system.cpu.toL2Bus.snoops 423123 # Total snoops (count)
936system.cpu.toL2Bus.snoop_fanout::samples 3306675 # Request fanout histogram
937system.cpu.toL2Bus.snoop_fanout::mean 0.001025 # Request fanout histogram
938system.cpu.toL2Bus.snoop_fanout::stdev 0.031993 # Request fanout histogram
939system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
940system.cpu.toL2Bus.snoop_fanout::0 3303287 99.90% 99.90% # Request fanout histogram
941system.cpu.toL2Bus.snoop_fanout::1 3388 0.10% 100.00% # Request fanout histogram
942system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
943system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
944system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
945system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
946system.cpu.toL2Bus.snoop_fanout::total 3306675 # Request fanout histogram
947system.cpu.toL2Bus.reqLayer0.occupancy 5189065000 # Layer occupancy (ticks)
948system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
949system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks)
950system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
951system.cpu.toL2Bus.respLayer0.occupancy 2208337564 # Layer occupancy (ticks)
952system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
953system.cpu.toL2Bus.respLayer1.occupancy 2104397493 # Layer occupancy (ticks)
954system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
955system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
956system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
957system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
958system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
959system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
960system.disk0.dma_write_txs 395 # Number of DMA write transactions.
961system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
962system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
963system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
964system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
965system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
966system.disk2.dma_write_txs 1 # Number of DMA write transactions.
967system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
968system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
969system.iobus.trans_dist::WriteReq 51175 # Transaction distribution
970system.iobus.trans_dist::WriteResp 51175 # Transaction distribution
971system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes)
972system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
973system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
974system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
975system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
976system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
977system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
978system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
979system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
980system.iobus.pkt_count_system.bridge.master::total 33106 # Packet count per connected master and slave (bytes)
981system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
982system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
983system.iobus.pkt_count::total 116556 # Packet count per connected master and slave (bytes)
984system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20408 # Cumulative packet size per connected master and slave (bytes)
985system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
986system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
987system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
988system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
989system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
990system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
991system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
992system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
993system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes)
994system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
995system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
996system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes)
997system.iobus.reqLayer0.occupancy 5407500 # Layer occupancy (ticks)
998system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
999system.iobus.reqLayer1.occupancy 805000 # Layer occupancy (ticks)
1000system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1001system.iobus.reqLayer2.occupancy 10000 # Layer occupancy (ticks)
1002system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1003system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks)
1004system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1005system.iobus.reqLayer22.occupancy 188500 # Layer occupancy (ticks)
1006system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1007system.iobus.reqLayer23.occupancy 14677500 # Layer occupancy (ticks)
1008system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1009system.iobus.reqLayer24.occupancy 2309500 # Layer occupancy (ticks)
1010system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1011system.iobus.reqLayer25.occupancy 6005500 # Layer occupancy (ticks)
1012system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1013system.iobus.reqLayer26.occupancy 93000 # Layer occupancy (ticks)
1014system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1015system.iobus.reqLayer27.occupancy 215722666 # Layer occupancy (ticks)
1016system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1017system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks)
1018system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1019system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
1020system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1021system.iocache.tags.replacements 41685 # number of replacements
1022system.iocache.tags.tagsinuse 1.298739 # Cycle average of tags in use
1023system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1024system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1025system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1026system.iocache.tags.warmup_cycle 1748617417000 # Cycle when the warmup percentage was hit.
1027system.iocache.tags.occ_blocks::tsunami.ide 1.298739 # Average occupied blocks per requestor
1028system.iocache.tags.occ_percent::tsunami.ide 0.081171 # Average percentage of cache occupancy
1029system.iocache.tags.occ_percent::total 0.081171 # Average percentage of cache occupancy
1030system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1031system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1032system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1033system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1034system.iocache.tags.data_accesses 375525 # Number of data accesses
1035system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1036system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1037system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1038system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
1056system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
1057system.iocache.demand_misses::total 173 # number of demand (read+write) misses
1058system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
1059system.iocache.overall_misses::total 173 # number of overall misses
| 1039system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
1040system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
1041system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
1042system.iocache.overall_misses::total 41725 # number of overall misses
|
1060system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles
1061system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles
1062system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245324283 # number of WriteLineReq miss cycles
1063system.iocache.WriteLineReq_miss_latency::total 5245324283 # number of WriteLineReq miss cycles
| 1043system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles
1044system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles
1045system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245324283 # number of WriteLineReq miss cycles
1046system.iocache.WriteLineReq_miss_latency::total 5245324283 # number of WriteLineReq miss cycles
|
1064system.iocache.demand_miss_latency::tsunami.ide 21917383 # number of demand (read+write) miss cycles
1065system.iocache.demand_miss_latency::total 21917383 # number of demand (read+write) miss cycles
1066system.iocache.overall_miss_latency::tsunami.ide 21917383 # number of overall miss cycles
1067system.iocache.overall_miss_latency::total 21917383 # number of overall miss cycles
| 1047system.iocache.demand_miss_latency::tsunami.ide 5267241666 # number of demand (read+write) miss cycles
1048system.iocache.demand_miss_latency::total 5267241666 # number of demand (read+write) miss cycles
1049system.iocache.overall_miss_latency::tsunami.ide 5267241666 # number of overall miss cycles
1050system.iocache.overall_miss_latency::total 5267241666 # number of overall miss cycles
|
1068system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
1069system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
1070system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1071system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
| 1051system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
1052system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
1053system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1054system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
1072system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
1073system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
1074system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
1075system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
| 1055system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
1056system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
1057system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
1058system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
1076system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1077system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1078system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1079system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1080system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1081system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1082system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1083system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1084system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency
1085system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency
1086system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126235.182013 # average WriteLineReq miss latency
1087system.iocache.WriteLineReq_avg_miss_latency::total 126235.182013 # average WriteLineReq miss latency
| 1059system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1060system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1061system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1062system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1063system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1064system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1065system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1066system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1067system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency
1068system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency
1069system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126235.182013 # average WriteLineReq miss latency
1070system.iocache.WriteLineReq_avg_miss_latency::total 126235.182013 # average WriteLineReq miss latency
|
1088system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency
1089system.iocache.demand_avg_miss_latency::total 126690.075145 # average overall miss latency
1090system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency
1091system.iocache.overall_avg_miss_latency::total 126690.075145 # average overall miss latency
| 1071system.iocache.demand_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency
1072system.iocache.demand_avg_miss_latency::total 126237.068089 # average overall miss latency
1073system.iocache.overall_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency
1074system.iocache.overall_avg_miss_latency::total 126237.068089 # average overall miss latency
|
1092system.iocache.blocked_cycles::no_mshrs 83 # number of cycles access was blocked
1093system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1094system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked
1095system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1096system.iocache.avg_blocked_cycles::no_mshrs 13.833333 # average number of cycles each access was blocked
1097system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
| 1075system.iocache.blocked_cycles::no_mshrs 83 # number of cycles access was blocked
1076system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1077system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked
1078system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1079system.iocache.avg_blocked_cycles::no_mshrs 13.833333 # average number of cycles each access was blocked
1080system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
1098system.iocache.fast_writes 0 # number of fast writes performed
1099system.iocache.cache_copies 0 # number of cache copies performed
| |
1100system.iocache.writebacks::writebacks 41512 # number of writebacks
1101system.iocache.writebacks::total 41512 # number of writebacks
1102system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
1103system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
1104system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1105system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
| 1081system.iocache.writebacks::writebacks 41512 # number of writebacks
1082system.iocache.writebacks::total 41512 # number of writebacks
1083system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
1084system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
1085system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1086system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
1106system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
1107system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
1108system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
1109system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
| 1087system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
1088system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
1089system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
1090system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
1110system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles
1111system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles
1112system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165924983 # number of WriteLineReq MSHR miss cycles
1113system.iocache.WriteLineReq_mshr_miss_latency::total 3165924983 # number of WriteLineReq MSHR miss cycles
| 1091system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles
1092system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles
1093system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165924983 # number of WriteLineReq MSHR miss cycles
1094system.iocache.WriteLineReq_mshr_miss_latency::total 3165924983 # number of WriteLineReq MSHR miss cycles
|
1114system.iocache.demand_mshr_miss_latency::tsunami.ide 13267383 # number of demand (read+write) MSHR miss cycles
1115system.iocache.demand_mshr_miss_latency::total 13267383 # number of demand (read+write) MSHR miss cycles
1116system.iocache.overall_mshr_miss_latency::tsunami.ide 13267383 # number of overall MSHR miss cycles
1117system.iocache.overall_mshr_miss_latency::total 13267383 # number of overall MSHR miss cycles
| 1095system.iocache.demand_mshr_miss_latency::tsunami.ide 3179192366 # number of demand (read+write) MSHR miss cycles
1096system.iocache.demand_mshr_miss_latency::total 3179192366 # number of demand (read+write) MSHR miss cycles
1097system.iocache.overall_mshr_miss_latency::tsunami.ide 3179192366 # number of overall MSHR miss cycles
1098system.iocache.overall_mshr_miss_latency::total 3179192366 # number of overall MSHR miss cycles
|
1118system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1119system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1120system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1121system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1122system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1123system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1124system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1125system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1126system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency
1127system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency
1128system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645 # average WriteLineReq mshr miss latency
1129system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645 # average WriteLineReq mshr miss latency
| 1099system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1100system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1101system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1102system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1103system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1104system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1105system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1106system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1107system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency
1108system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency
1109system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645 # average WriteLineReq mshr miss latency
1110system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645 # average WriteLineReq mshr miss latency
|
1130system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency
1131system.iocache.demand_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency
1132system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency
1133system.iocache.overall_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency
1134system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
| 1111system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency
1112system.iocache.demand_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency
1113system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency
1114system.iocache.overall_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency
|
1135system.membus.trans_dist::ReadReq 6930 # Transaction distribution
1136system.membus.trans_dist::ReadResp 295608 # Transaction distribution
1137system.membus.trans_dist::WriteReq 9623 # Transaction distribution
1138system.membus.trans_dist::WriteResp 9623 # Transaction distribution
1139system.membus.trans_dist::WritebackDirty 118096 # Transaction distribution
1140system.membus.trans_dist::CleanEvict 262242 # Transaction distribution
1141system.membus.trans_dist::UpgradeReq 167 # Transaction distribution
1142system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
1143system.membus.trans_dist::ReadExReq 116428 # Transaction distribution
1144system.membus.trans_dist::ReadExResp 116428 # Transaction distribution
1145system.membus.trans_dist::ReadSharedReq 288702 # Transaction distribution
1146system.membus.trans_dist::BadAddressError 24 # Transaction distribution
1147system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
1148system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes)
1149system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148413 # Packet count per connected master and slave (bytes)
1150system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes)
1151system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181567 # Packet count per connected master and slave (bytes)
1152system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes)
1153system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes)
1154system.membus.pkt_count::total 1264992 # Packet count per connected master and slave (bytes)
1155system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes)
1156system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30799616 # Cumulative packet size per connected master and slave (bytes)
1157system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30843964 # Cumulative packet size per connected master and slave (bytes)
1158system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
1159system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
1160system.membus.pkt_size::total 33501692 # Cumulative packet size per connected master and slave (bytes)
1161system.membus.snoops 433 # Total snoops (count)
1162system.membus.snoop_fanout::samples 843750 # Request fanout histogram
1163system.membus.snoop_fanout::mean 1 # Request fanout histogram
1164system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1165system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1166system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1167system.membus.snoop_fanout::1 843750 100.00% 100.00% # Request fanout histogram
1168system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1169system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1170system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1171system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1172system.membus.snoop_fanout::total 843750 # Request fanout histogram
1173system.membus.reqLayer0.occupancy 29507500 # Layer occupancy (ticks)
1174system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1175system.membus.reqLayer1.occupancy 1318874217 # Layer occupancy (ticks)
1176system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1177system.membus.reqLayer2.occupancy 29500 # Layer occupancy (ticks)
1178system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1179system.membus.respLayer1.occupancy 2159448000 # Layer occupancy (ticks)
1180system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1181system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks)
1182system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1183system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1184system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1185system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1186system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1187system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1188system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1189system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1190system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1191system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1192system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1193system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1194system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1195system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1196system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1197system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1198system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1199system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1200system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1201system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1202system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1203system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1204system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1205system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1206system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1207system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1208system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1209system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1210system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1211system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1212system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1213system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
1214
1215---------- End Simulation Statistics ----------
| 1115system.membus.trans_dist::ReadReq 6930 # Transaction distribution
1116system.membus.trans_dist::ReadResp 295608 # Transaction distribution
1117system.membus.trans_dist::WriteReq 9623 # Transaction distribution
1118system.membus.trans_dist::WriteResp 9623 # Transaction distribution
1119system.membus.trans_dist::WritebackDirty 118096 # Transaction distribution
1120system.membus.trans_dist::CleanEvict 262242 # Transaction distribution
1121system.membus.trans_dist::UpgradeReq 167 # Transaction distribution
1122system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
1123system.membus.trans_dist::ReadExReq 116428 # Transaction distribution
1124system.membus.trans_dist::ReadExResp 116428 # Transaction distribution
1125system.membus.trans_dist::ReadSharedReq 288702 # Transaction distribution
1126system.membus.trans_dist::BadAddressError 24 # Transaction distribution
1127system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
1128system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes)
1129system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148413 # Packet count per connected master and slave (bytes)
1130system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes)
1131system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181567 # Packet count per connected master and slave (bytes)
1132system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes)
1133system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes)
1134system.membus.pkt_count::total 1264992 # Packet count per connected master and slave (bytes)
1135system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes)
1136system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30799616 # Cumulative packet size per connected master and slave (bytes)
1137system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30843964 # Cumulative packet size per connected master and slave (bytes)
1138system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
1139system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
1140system.membus.pkt_size::total 33501692 # Cumulative packet size per connected master and slave (bytes)
1141system.membus.snoops 433 # Total snoops (count)
1142system.membus.snoop_fanout::samples 843750 # Request fanout histogram
1143system.membus.snoop_fanout::mean 1 # Request fanout histogram
1144system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1145system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1146system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1147system.membus.snoop_fanout::1 843750 100.00% 100.00% # Request fanout histogram
1148system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1149system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1150system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1151system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1152system.membus.snoop_fanout::total 843750 # Request fanout histogram
1153system.membus.reqLayer0.occupancy 29507500 # Layer occupancy (ticks)
1154system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1155system.membus.reqLayer1.occupancy 1318874217 # Layer occupancy (ticks)
1156system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1157system.membus.reqLayer2.occupancy 29500 # Layer occupancy (ticks)
1158system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1159system.membus.respLayer1.occupancy 2159448000 # Layer occupancy (ticks)
1160system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1161system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks)
1162system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1163system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1164system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1165system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1166system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1167system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1168system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1169system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1170system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1171system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1172system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1173system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1174system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1175system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1176system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1177system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1178system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1179system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1180system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1181system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1182system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1183system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1184system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1185system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1186system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1187system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1188system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1189system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1190system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1191system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1192system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1193system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
1194
1195---------- End Simulation Statistics ----------
|