1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.883224 # Number of seconds simulated
4sim_ticks 1883223940000 # Number of ticks simulated
5final_tick 1883223940000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 180615 # Simulator instruction rate (inst/s)
8host_op_rate 180615 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 6060637883 # Simulator tick rate (ticks/s)
10host_mem_usage 316396 # Number of bytes of host memory used
11host_seconds 310.73 # Real time elapsed on the host
12sim_insts 56122642 # Number of instructions simulated
13sim_ops 56122642 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 25930944 # Number of bytes read from this memory
17system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
18system.physmem.bytes_read::total 25931904 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 4902720 # Number of bytes written to this memory
22system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7562048 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 405171 # Number of read requests responded to by this memory
25system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 405186 # Number of read requests responded to by this memory
27system.physmem.num_writes::writebacks 76605 # Number of write requests responded to by this memory
28system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 118157 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 13769443 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::total 13769952 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::cpu.inst 558905 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::total 558905 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_write::writebacks 2603365 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_write::tsunami.ide 1412115 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 4015480 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 2603365 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 13769443 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::total 17785432 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.readReqs 405186 # Number of read requests accepted
43system.physmem.writeReqs 118157 # Number of write requests accepted
44system.physmem.readBursts 405186 # Number of DRAM read bursts, including those serviced by the write queue
45system.physmem.writeBursts 118157 # Number of DRAM write bursts, including those merged in the write queue
46system.physmem.bytesReadDRAM 25919424 # Total number of bytes read from DRAM
47system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue
48system.physmem.bytesWritten 7560064 # Total number of bytes written to DRAM
49system.physmem.bytesReadSys 25931904 # Total read bytes from the system interface side
50system.physmem.bytesWrittenSys 7562048 # Total written bytes from the system interface side
51system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue
52system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
53system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write
54system.physmem.perBankRdBursts::0 25480 # Per bank write bursts
55system.physmem.perBankRdBursts::1 25741 # Per bank write bursts
56system.physmem.perBankRdBursts::2 25855 # Per bank write bursts
57system.physmem.perBankRdBursts::3 25788 # Per bank write bursts
58system.physmem.perBankRdBursts::4 25233 # Per bank write bursts
59system.physmem.perBankRdBursts::5 24956 # Per bank write bursts
60system.physmem.perBankRdBursts::6 24811 # Per bank write bursts
61system.physmem.perBankRdBursts::7 24586 # Per bank write bursts
62system.physmem.perBankRdBursts::8 25127 # Per bank write bursts
63system.physmem.perBankRdBursts::9 25280 # Per bank write bursts
64system.physmem.perBankRdBursts::10 25532 # Per bank write bursts
65system.physmem.perBankRdBursts::11 24857 # Per bank write bursts
66system.physmem.perBankRdBursts::12 24547 # Per bank write bursts
67system.physmem.perBankRdBursts::13 25588 # Per bank write bursts
68system.physmem.perBankRdBursts::14 25870 # Per bank write bursts
69system.physmem.perBankRdBursts::15 25740 # Per bank write bursts
70system.physmem.perBankWrBursts::0 7812 # Per bank write bursts
71system.physmem.perBankWrBursts::1 7677 # Per bank write bursts
72system.physmem.perBankWrBursts::2 8067 # Per bank write bursts
73system.physmem.perBankWrBursts::3 7744 # Per bank write bursts
74system.physmem.perBankWrBursts::4 7318 # Per bank write bursts
75system.physmem.perBankWrBursts::5 6954 # Per bank write bursts
76system.physmem.perBankWrBursts::6 6788 # Per bank write bursts
77system.physmem.perBankWrBursts::7 6406 # Per bank write bursts
78system.physmem.perBankWrBursts::8 7235 # Per bank write bursts
79system.physmem.perBankWrBursts::9 6889 # Per bank write bursts
80system.physmem.perBankWrBursts::10 7393 # Per bank write bursts
81system.physmem.perBankWrBursts::11 6865 # Per bank write bursts
82system.physmem.perBankWrBursts::12 7045 # Per bank write bursts
83system.physmem.perBankWrBursts::13 8007 # Per bank write bursts
84system.physmem.perBankWrBursts::14 7989 # Per bank write bursts
85system.physmem.perBankWrBursts::15 7937 # Per bank write bursts
86system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
87system.physmem.numWrRetry 5 # Number of times write queue was full causing retry
88system.physmem.totGap 1883215178500 # Total gap between requests
89system.physmem.readPktSize::0 0 # Read request sizes (log2)
90system.physmem.readPktSize::1 0 # Read request sizes (log2)
91system.physmem.readPktSize::2 0 # Read request sizes (log2)
92system.physmem.readPktSize::3 0 # Read request sizes (log2)
93system.physmem.readPktSize::4 0 # Read request sizes (log2)
94system.physmem.readPktSize::5 0 # Read request sizes (log2)
95system.physmem.readPktSize::6 405186 # Read request sizes (log2)
96system.physmem.writePktSize::0 0 # Write request sizes (log2)
97system.physmem.writePktSize::1 0 # Write request sizes (log2)
98system.physmem.writePktSize::2 0 # Write request sizes (log2)
99system.physmem.writePktSize::3 0 # Write request sizes (log2)
100system.physmem.writePktSize::4 0 # Write request sizes (log2)
101system.physmem.writePktSize::5 0 # Write request sizes (log2)
102system.physmem.writePktSize::6 118157 # Write request sizes (log2)
103system.physmem.rdQLenPdf::0 402670 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::1 2243 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see

--- 28 unchanged lines hidden (view full) ---

142system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::15 1541 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::16 2210 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::17 5693 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::18 5920 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::19 6144 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::20 6907 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::21 7208 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::23 8700 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::24 8681 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::25 8384 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::26 8515 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::27 7009 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::28 6582 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::29 5776 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::30 5533 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::31 5557 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::32 5513 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::33 225 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::37 158 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::39 112 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::40 118 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::41 140 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::43 148 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::44 178 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::45 193 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::46 184 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::48 173 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::51 123 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::54 108 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::55 101 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see
199system.physmem.bytesPerActivate::samples 62955 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::mean 531.800302 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::gmean 324.503879 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::stdev 415.177975 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::0-127 14434 22.93% 22.93% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::128-255 10626 16.88% 39.81% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::256-383 4984 7.92% 47.72% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::384-511 3035 4.82% 52.54% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::512-639 2479 3.94% 56.48% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::640-767 2063 3.28% 59.76% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::768-895 1365 2.17% 61.93% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::896-1023 1615 2.57% 64.49% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::1024-1151 22354 35.51% 100.00% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::total 62955 # Bytes accessed per row activation
213system.physmem.rdPerTurnAround::samples 5310 # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::mean 76.265725 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::stdev 2898.384419 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::0-8191 5307 99.94% 99.94% # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::total 5310 # Reads before turning the bus around for writes
221system.physmem.wrPerTurnAround::samples 5310 # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::mean 22.245951 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::gmean 18.963647 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::stdev 20.434666 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::16-19 4660 87.76% 87.76% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::20-23 16 0.30% 88.06% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::24-27 15 0.28% 88.34% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::28-31 227 4.27% 92.62% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::32-35 38 0.72% 93.33% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::36-39 5 0.09% 93.43% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::40-43 8 0.15% 93.58% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::44-47 6 0.11% 93.69% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::48-51 26 0.49% 94.18% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::52-55 4 0.08% 94.26% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::56-59 5 0.09% 94.35% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::64-67 14 0.26% 94.61% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::68-71 2 0.04% 94.65% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::72-75 5 0.09% 94.75% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::80-83 26 0.49% 95.24% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::84-87 9 0.17% 95.40% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::88-91 5 0.09% 95.50% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::92-95 6 0.11% 95.61% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::96-99 182 3.43% 99.04% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::100-103 6 0.11% 99.15% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::108-111 1 0.02% 99.17% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::112-115 2 0.04% 99.21% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::120-123 3 0.06% 99.27% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::128-131 6 0.11% 99.42% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::132-135 5 0.09% 99.51% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::136-139 4 0.08% 99.59% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::140-143 2 0.04% 99.62% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::144-147 7 0.13% 99.76% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::152-155 1 0.02% 99.77% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::160-163 5 0.09% 99.89% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::176-179 2 0.04% 99.92% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::total 5310 # Writes before turning the bus around for reads
261system.physmem.totQLat 2131293750 # Total ticks spent queuing
262system.physmem.totMemAccLat 9724875000 # Total ticks spent from burst creation until serviced by the DRAM
263system.physmem.totBusLat 2024955000 # Total ticks spent in databus transfers
264system.physmem.avgQLat 5262.57 # Average queueing delay per DRAM burst
265system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
266system.physmem.avgMemAccLat 24012.57 # Average memory access latency per DRAM burst
267system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s
268system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s
269system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s
270system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s
271system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
272system.physmem.busUtil 0.14 # Data bus utilization in percentage
273system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
274system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
275system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
276system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing
277system.physmem.readRowHits 364467 # Number of row buffer hits during reads
278system.physmem.writeRowHits 95695 # Number of row buffer hits during writes
279system.physmem.readRowHitRate 89.99 # Row buffer hit rate for reads
280system.physmem.writeRowHitRate 80.99 # Row buffer hit rate for writes
281system.physmem.avgGap 3598433.87 # Average gap between requests
282system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined
283system.physmem.memoryStateTime::IDLE 1774121817500 # Time in different power states
284system.physmem.memoryStateTime::REF 62884900000 # Time in different power states
285system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
286system.physmem.memoryStateTime::ACT 46214912500 # Time in different power states
287system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
288system.membus.throughput 17814330 # Throughput (bytes/s)
289system.membus.trans_dist::ReadReq 295751 # Transaction distribution
290system.membus.trans_dist::ReadResp 295735 # Transaction distribution
291system.membus.trans_dist::WriteReq 9618 # Transaction distribution
292system.membus.trans_dist::WriteResp 9618 # Transaction distribution
293system.membus.trans_dist::Writeback 76605 # Transaction distribution
294system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
295system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
296system.membus.trans_dist::UpgradeReq 157 # Transaction distribution
297system.membus.trans_dist::UpgradeResp 157 # Transaction distribution
298system.membus.trans_dist::ReadExReq 116539 # Transaction distribution
299system.membus.trans_dist::ReadExResp 116539 # Transaction distribution
300system.membus.trans_dist::BadAddressError 16 # Transaction distribution
301system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes)
302system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887261 # Packet count per connected master and slave (bytes)
303system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes)
304system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920389 # Packet count per connected master and slave (bytes)
305system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes)
306system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes)
307system.membus.pkt_count::total 1003681 # Packet count per connected master and slave (bytes)
308system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes)
309system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30833664 # Cumulative packet size per connected master and slave (bytes)
310system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30877972 # Cumulative packet size per connected master and slave (bytes)
311system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
312system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
313system.membus.tot_pkt_size::total 33538260 # Cumulative packet size per connected master and slave (bytes)
314system.membus.data_through_bus 33538260 # Total data (bytes)
315system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
316system.membus.reqLayer0.occupancy 29840000 # Layer occupancy (ticks)
317system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
318system.membus.reqLayer1.occupancy 1547069500 # Layer occupancy (ticks)
319system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
320system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks)
321system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
322system.membus.respLayer1.occupancy 3825068843 # Layer occupancy (ticks)
323system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
324system.membus.respLayer2.occupancy 43112000 # Layer occupancy (ticks)
325system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
326system.iocache.tags.replacements 41685 # number of replacements
327system.iocache.tags.tagsinuse 1.288165 # Cycle average of tags in use
328system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
329system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
330system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
331system.iocache.tags.warmup_cycle 1728026235000 # Cycle when the warmup percentage was hit.
332system.iocache.tags.occ_blocks::tsunami.ide 1.288165 # Average occupied blocks per requestor
333system.iocache.tags.occ_percent::tsunami.ide 0.080510 # Average percentage of cache occupancy
334system.iocache.tags.occ_percent::total 0.080510 # Average percentage of cache occupancy
335system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
336system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
337system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
338system.iocache.tags.tag_accesses 375533 # Number of tag accesses
339system.iocache.tags.data_accesses 375533 # Number of data accesses
340system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
341system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
342system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
343system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
344system.iocache.WriteInvalidateReq_misses::tsunami.ide 1 # number of WriteInvalidateReq misses
345system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses
346system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
347system.iocache.demand_misses::total 173 # number of demand (read+write) misses
348system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
349system.iocache.overall_misses::total 173 # number of overall misses
350system.iocache.ReadReq_miss_latency::tsunami.ide 21132383 # number of ReadReq miss cycles
351system.iocache.ReadReq_miss_latency::total 21132383 # number of ReadReq miss cycles
352system.iocache.demand_miss_latency::tsunami.ide 21132383 # number of demand (read+write) miss cycles
353system.iocache.demand_miss_latency::total 21132383 # number of demand (read+write) miss cycles
354system.iocache.overall_miss_latency::tsunami.ide 21132383 # number of overall miss cycles
355system.iocache.overall_miss_latency::total 21132383 # number of overall miss cycles
356system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
357system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
358system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41553 # number of WriteInvalidateReq accesses(hits+misses)
359system.iocache.WriteInvalidateReq_accesses::total 41553 # number of WriteInvalidateReq accesses(hits+misses)
360system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
361system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
362system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
363system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
364system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
365system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
366system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000024 # miss rate for WriteInvalidateReq accesses
367system.iocache.WriteInvalidateReq_miss_rate::total 0.000024 # miss rate for WriteInvalidateReq accesses
368system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
369system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
370system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
371system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
372system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122152.502890 # average ReadReq miss latency
373system.iocache.ReadReq_avg_miss_latency::total 122152.502890 # average ReadReq miss latency
374system.iocache.demand_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency
375system.iocache.demand_avg_miss_latency::total 122152.502890 # average overall miss latency
376system.iocache.overall_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency
377system.iocache.overall_avg_miss_latency::total 122152.502890 # average overall miss latency
378system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
379system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
380system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
381system.iocache.blocked::no_targets 0 # number of cycles access was blocked
382system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
383system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
384system.iocache.fast_writes 41552 # number of fast writes performed
385system.iocache.cache_copies 0 # number of cache copies performed
386system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
387system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
388system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
389system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
390system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
391system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
392system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
393system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
394system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12135383 # number of ReadReq MSHR miss cycles
395system.iocache.ReadReq_mshr_miss_latency::total 12135383 # number of ReadReq MSHR miss cycles
396system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2514597305 # number of WriteInvalidateReq MSHR miss cycles
397system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2514597305 # number of WriteInvalidateReq MSHR miss cycles
398system.iocache.demand_mshr_miss_latency::tsunami.ide 12135383 # number of demand (read+write) MSHR miss cycles
399system.iocache.demand_mshr_miss_latency::total 12135383 # number of demand (read+write) MSHR miss cycles
400system.iocache.overall_mshr_miss_latency::tsunami.ide 12135383 # number of overall MSHR miss cycles
401system.iocache.overall_mshr_miss_latency::total 12135383 # number of overall MSHR miss cycles
402system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
403system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
404system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999976 # mshr miss rate for WriteInvalidateReq accesses
405system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999976 # mshr miss rate for WriteInvalidateReq accesses
406system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
407system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
408system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
409system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
410system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average ReadReq mshr miss latency
411system.iocache.ReadReq_avg_mshr_miss_latency::total 70146.722543 # average ReadReq mshr miss latency
412system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60516.877768 # average WriteInvalidateReq mshr miss latency
413system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60516.877768 # average WriteInvalidateReq mshr miss latency
414system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency
415system.iocache.demand_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency
416system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency
417system.iocache.overall_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency
418system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
419system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
420system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
421system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
422system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
423system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
424system.disk0.dma_write_txs 395 # Number of DMA write transactions.
425system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
426system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
427system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
428system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
429system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
430system.disk2.dma_write_txs 1 # Number of DMA write transactions.
431system.cpu.branchPred.lookups 14964215 # Number of BP lookups
432system.cpu.branchPred.condPredicted 12981470 # Number of conditional branches predicted
433system.cpu.branchPred.condIncorrect 376025 # Number of conditional branches incorrect
434system.cpu.branchPred.BTBLookups 10003487 # Number of BTB lookups
435system.cpu.branchPred.BTBHits 5188980 # Number of BTB hits
436system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
437system.cpu.branchPred.BTBHitPct 51.871712 # BTB Hit Percentage
438system.cpu.branchPred.usedRAS 807651 # Number of times the RAS was used to get a target.
439system.cpu.branchPred.RASInCorrect 32040 # Number of incorrect RAS predictions.
440system.cpu_clk_domain.clock 500 # Clock period in ticks
441system.cpu.dtb.fetch_hits 0 # ITB hits
442system.cpu.dtb.fetch_misses 0 # ITB misses
443system.cpu.dtb.fetch_acv 0 # ITB acv
444system.cpu.dtb.fetch_accesses 0 # ITB accesses
445system.cpu.dtb.read_hits 9238395 # DTB read hits
446system.cpu.dtb.read_misses 17814 # DTB read misses
447system.cpu.dtb.read_acv 211 # DTB read access violations
448system.cpu.dtb.read_accesses 766068 # DTB read accesses
449system.cpu.dtb.write_hits 6385066 # DTB write hits
450system.cpu.dtb.write_misses 2311 # DTB write misses
451system.cpu.dtb.write_acv 159 # DTB write access violations
452system.cpu.dtb.write_accesses 298441 # DTB write accesses
453system.cpu.dtb.data_hits 15623461 # DTB hits
454system.cpu.dtb.data_misses 20125 # DTB misses
455system.cpu.dtb.data_acv 370 # DTB access violations
456system.cpu.dtb.data_accesses 1064509 # DTB accesses
457system.cpu.itb.fetch_hits 4000795 # ITB hits
458system.cpu.itb.fetch_misses 6874 # ITB misses
459system.cpu.itb.fetch_acv 703 # ITB acv
460system.cpu.itb.fetch_accesses 4007669 # ITB accesses
461system.cpu.itb.read_hits 0 # DTB read hits
462system.cpu.itb.read_misses 0 # DTB read misses
463system.cpu.itb.read_acv 0 # DTB read access violations
464system.cpu.itb.read_accesses 0 # DTB read accesses
465system.cpu.itb.write_hits 0 # DTB write hits
466system.cpu.itb.write_misses 0 # DTB write misses
467system.cpu.itb.write_acv 0 # DTB write access violations
468system.cpu.itb.write_accesses 0 # DTB write accesses
469system.cpu.itb.data_hits 0 # DTB hits
470system.cpu.itb.data_misses 0 # DTB misses
471system.cpu.itb.data_acv 0 # DTB access violations
472system.cpu.itb.data_accesses 0 # DTB accesses
473system.cpu.numCycles 176776474 # number of cpu cycles simulated
474system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
475system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
476system.cpu.committedInsts 56122642 # Number of instructions committed
477system.cpu.committedOps 56122642 # Number of ops (including micro ops) committed
478system.cpu.discardedOps 2532635 # Number of ops (including micro ops) which were discarded before commit
479system.cpu.numFetchSuspends 5494 # Number of times Execute suspended instruction fetching
480system.cpu.quiesceCycles 3591582755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
481system.cpu.cpi 3.149825 # CPI: cycles per instruction
482system.cpu.ipc 0.317478 # IPC: instructions per cycle
483system.cpu.kern.inst.arm 0 # number of arm instructions executed
484system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed
485system.cpu.kern.inst.hwrei 211451 # number of hwrei instructions executed
486system.cpu.kern.ipl_count::0 74783 40.94% 40.94% # number of times we switched to this ipl
487system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
488system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl
489system.cpu.kern.ipl_count::31 105851 57.95% 100.00% # number of times we switched to this ipl
490system.cpu.kern.ipl_count::total 182665 # number of times we switched to this ipl
491system.cpu.kern.ipl_good::0 73416 49.32% 49.32% # number of times we switched to this ipl from a different ipl
492system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
493system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl
494system.cpu.kern.ipl_good::31 73416 49.32% 100.00% # number of times we switched to this ipl from a different ipl
495system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl
496system.cpu.kern.ipl_ticks::0 1832860357500 97.33% 97.33% # number of cycles we spent at this ipl
497system.cpu.kern.ipl_ticks::21 80169000 0.00% 97.33% # number of cycles we spent at this ipl
498system.cpu.kern.ipl_ticks::22 672803000 0.04% 97.37% # number of cycles we spent at this ipl
499system.cpu.kern.ipl_ticks::31 49609630000 2.63% 100.00% # number of cycles we spent at this ipl
500system.cpu.kern.ipl_ticks::total 1883222959500 # number of cycles we spent at this ipl
501system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl
502system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
503system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
504system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl
505system.cpu.kern.ipl_used::total 0.814951 # fraction of swpipl calls that actually changed the ipl
506system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
507system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
508system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
509system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
510system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
511system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
512system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
513system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed

--- 22 unchanged lines hidden (view full) ---

536system.cpu.kern.syscall::total 326 # number of syscalls executed
537system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
538system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
539system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
540system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
541system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
542system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
543system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
544system.cpu.kern.callpal::swpipl 175508 91.23% 93.43% # number of callpals executed
545system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed
546system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
547system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
548system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
549system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
550system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed
551system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
552system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
553system.cpu.kern.callpal::total 192390 # number of callpals executed
554system.cpu.kern.mode_switch::kernel 5869 # number of protection mode switches
555system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
556system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
557system.cpu.kern.mode_good::kernel 1910
558system.cpu.kern.mode_good::user 1741
559system.cpu.kern.mode_good::idle 169
560system.cpu.kern.mode_switch_good::kernel 0.325439 # fraction of useful protection mode switches
561system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
562system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches
563system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches
564system.cpu.kern.mode_ticks::kernel 36245351000 1.92% 1.92% # number of ticks spent at the given mode
565system.cpu.kern.mode_ticks::user 4057630500 0.22% 2.14% # number of ticks spent at the given mode
566system.cpu.kern.mode_ticks::idle 1842919968000 97.86% 100.00% # number of ticks spent at the given mode
567system.cpu.kern.swap_context 4175 # number of times the context was actually changed
568system.cpu.tickCycles 85798616 # Number of cycles that the object actually ticked
569system.cpu.idleCycles 90977858 # Total number of cycles that the object has spent stopped
570system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
571system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
572system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
573system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
574system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
575system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
576system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
577system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

593system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
594system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
595system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
596system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
597system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
598system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
599system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
600system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
601system.iobus.throughput 1436853 # Throughput (bytes/s)
602system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
603system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
604system.iobus.trans_dist::WriteReq 51169 # Transaction distribution
605system.iobus.trans_dist::WriteResp 51170 # Transaction distribution
606system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution
607system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes)
608system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
609system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
610system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
611system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
612system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
613system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
614system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
615system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
616system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
617system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
618system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
619system.iobus.pkt_count_system.bridge.master::total 33096 # Packet count per connected master and slave (bytes)
620system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
621system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
622system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes)
623system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes)
624system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
625system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
626system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
627system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
628system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
629system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
630system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
631system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
632system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
633system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
634system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
635system.iobus.tot_pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes)
636system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
637system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
638system.iobus.tot_pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes)
639system.iobus.data_through_bus 2705916 # Total data (bytes)
640system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks)
641system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
642system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
643system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
644system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
645system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
646system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
647system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)

--- 6 unchanged lines hidden (view full) ---

654system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
655system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
656system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
657system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
658system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
659system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
660system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
661system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
662system.iobus.reqLayer29.occupancy 374409688 # Layer occupancy (ticks)
663system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
664system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
665system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
666system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks)
667system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
668system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks)
669system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
670system.cpu.icache.tags.replacements 1458007 # number of replacements
671system.cpu.icache.tags.tagsinuse 509.627041 # Cycle average of tags in use
672system.cpu.icache.tags.total_refs 18950160 # Total number of references to valid blocks.
673system.cpu.icache.tags.sampled_refs 1458518 # Sample count of references to valid blocks.
674system.cpu.icache.tags.avg_refs 12.992750 # Average number of references to valid blocks.
675system.cpu.icache.tags.warmup_cycle 31562091250 # Cycle when the warmup percentage was hit.
676system.cpu.icache.tags.occ_blocks::cpu.inst 509.627041 # Average occupied blocks per requestor
677system.cpu.icache.tags.occ_percent::cpu.inst 0.995365 # Average percentage of cache occupancy
678system.cpu.icache.tags.occ_percent::total 0.995365 # Average percentage of cache occupancy
679system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
680system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
681system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
682system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id
683system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
684system.cpu.icache.tags.tag_accesses 21867553 # Number of tag accesses
685system.cpu.icache.tags.data_accesses 21867553 # Number of data accesses
686system.cpu.icache.ReadReq_hits::cpu.inst 18950163 # number of ReadReq hits
687system.cpu.icache.ReadReq_hits::total 18950163 # number of ReadReq hits
688system.cpu.icache.demand_hits::cpu.inst 18950163 # number of demand (read+write) hits
689system.cpu.icache.demand_hits::total 18950163 # number of demand (read+write) hits
690system.cpu.icache.overall_hits::cpu.inst 18950163 # number of overall hits
691system.cpu.icache.overall_hits::total 18950163 # number of overall hits
692system.cpu.icache.ReadReq_misses::cpu.inst 1458695 # number of ReadReq misses
693system.cpu.icache.ReadReq_misses::total 1458695 # number of ReadReq misses
694system.cpu.icache.demand_misses::cpu.inst 1458695 # number of demand (read+write) misses
695system.cpu.icache.demand_misses::total 1458695 # number of demand (read+write) misses
696system.cpu.icache.overall_misses::cpu.inst 1458695 # number of overall misses
697system.cpu.icache.overall_misses::total 1458695 # number of overall misses
698system.cpu.icache.ReadReq_miss_latency::cpu.inst 20021954296 # number of ReadReq miss cycles
699system.cpu.icache.ReadReq_miss_latency::total 20021954296 # number of ReadReq miss cycles
700system.cpu.icache.demand_miss_latency::cpu.inst 20021954296 # number of demand (read+write) miss cycles
701system.cpu.icache.demand_miss_latency::total 20021954296 # number of demand (read+write) miss cycles
702system.cpu.icache.overall_miss_latency::cpu.inst 20021954296 # number of overall miss cycles
703system.cpu.icache.overall_miss_latency::total 20021954296 # number of overall miss cycles
704system.cpu.icache.ReadReq_accesses::cpu.inst 20408858 # number of ReadReq accesses(hits+misses)
705system.cpu.icache.ReadReq_accesses::total 20408858 # number of ReadReq accesses(hits+misses)
706system.cpu.icache.demand_accesses::cpu.inst 20408858 # number of demand (read+write) accesses
707system.cpu.icache.demand_accesses::total 20408858 # number of demand (read+write) accesses
708system.cpu.icache.overall_accesses::cpu.inst 20408858 # number of overall (read+write) accesses
709system.cpu.icache.overall_accesses::total 20408858 # number of overall (read+write) accesses
710system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071474 # miss rate for ReadReq accesses
711system.cpu.icache.ReadReq_miss_rate::total 0.071474 # miss rate for ReadReq accesses
712system.cpu.icache.demand_miss_rate::cpu.inst 0.071474 # miss rate for demand accesses
713system.cpu.icache.demand_miss_rate::total 0.071474 # miss rate for demand accesses
714system.cpu.icache.overall_miss_rate::cpu.inst 0.071474 # miss rate for overall accesses
715system.cpu.icache.overall_miss_rate::total 0.071474 # miss rate for overall accesses
716system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.936057 # average ReadReq miss latency
717system.cpu.icache.ReadReq_avg_miss_latency::total 13725.936057 # average ReadReq miss latency
718system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency
719system.cpu.icache.demand_avg_miss_latency::total 13725.936057 # average overall miss latency
720system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency
721system.cpu.icache.overall_avg_miss_latency::total 13725.936057 # average overall miss latency
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723system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
724system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
725system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
726system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
727system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
728system.cpu.icache.fast_writes 0 # number of fast writes performed
729system.cpu.icache.cache_copies 0 # number of cache copies performed
730system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458695 # number of ReadReq MSHR misses
731system.cpu.icache.ReadReq_mshr_misses::total 1458695 # number of ReadReq MSHR misses
732system.cpu.icache.demand_mshr_misses::cpu.inst 1458695 # number of demand (read+write) MSHR misses
733system.cpu.icache.demand_mshr_misses::total 1458695 # number of demand (read+write) MSHR misses
734system.cpu.icache.overall_mshr_misses::cpu.inst 1458695 # number of overall MSHR misses
735system.cpu.icache.overall_mshr_misses::total 1458695 # number of overall MSHR misses
736system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097209704 # number of ReadReq MSHR miss cycles
737system.cpu.icache.ReadReq_mshr_miss_latency::total 17097209704 # number of ReadReq MSHR miss cycles
738system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097209704 # number of demand (read+write) MSHR miss cycles
739system.cpu.icache.demand_mshr_miss_latency::total 17097209704 # number of demand (read+write) MSHR miss cycles
740system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097209704 # number of overall MSHR miss cycles
741system.cpu.icache.overall_mshr_miss_latency::total 17097209704 # number of overall MSHR miss cycles
742system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for ReadReq accesses
743system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071474 # mshr miss rate for ReadReq accesses
744system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for demand accesses
745system.cpu.icache.demand_mshr_miss_rate::total 0.071474 # mshr miss rate for demand accesses
746system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for overall accesses
747system.cpu.icache.overall_mshr_miss_rate::total 0.071474 # mshr miss rate for overall accesses
748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11720.894158 # average ReadReq mshr miss latency
749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11720.894158 # average ReadReq mshr miss latency
750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency
751system.cpu.icache.demand_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency
752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency
753system.cpu.icache.overall_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency
754system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
755system.cpu.toL2Bus.throughput 126942050 # Throughput (bytes/s)
756system.cpu.toL2Bus.trans_dist::ReadReq 2557486 # Transaction distribution
757system.cpu.toL2Bus.trans_dist::ReadResp 2557452 # Transaction distribution
758system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution
759system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution
760system.cpu.toL2Bus.trans_dist::Writeback 838282 # Transaction distribution
761system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41557 # Transaction distribution
762system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution
763system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution
764system.cpu.toL2Bus.trans_dist::ReadExReq 304264 # Transaction distribution
765system.cpu.toL2Bus.trans_dist::ReadExResp 304264 # Transaction distribution
766system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution
767system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917328 # Packet count per connected master and slave (bytes)
768system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663485 # Packet count per connected master and slave (bytes)
769system.cpu.toL2Bus.pkt_count::total 6580813 # Packet count per connected master and slave (bytes)
770system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352512 # Cumulative packet size per connected master and slave (bytes)
771system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143044180 # Cumulative packet size per connected master and slave (bytes)
772system.cpu.toL2Bus.tot_pkt_size::total 236396692 # Cumulative packet size per connected master and slave (bytes)
773system.cpu.toL2Bus.data_through_bus 236386772 # Total data (bytes)
774system.cpu.toL2Bus.snoop_data_through_bus 2673536 # Total snoop data (bytes)
775system.cpu.toL2Bus.reqLayer0.occupancy 2697842997 # Layer occupancy (ticks)
776system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
777system.cpu.toL2Bus.snoopLayer0.occupancy 232500 # Layer occupancy (ticks)
778system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
779system.cpu.toL2Bus.respLayer0.occupancy 2191719796 # Layer occupancy (ticks)
780system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
781system.cpu.toL2Bus.respLayer1.occupancy 2194901157 # Layer occupancy (ticks)
782system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
783system.cpu.l2cache.tags.replacements 339412 # number of replacements
784system.cpu.l2cache.tags.tagsinuse 65326.749870 # Cycle average of tags in use
785system.cpu.l2cache.tags.total_refs 2981869 # Total number of references to valid blocks.
786system.cpu.l2cache.tags.sampled_refs 404575 # Sample count of references to valid blocks.
787system.cpu.l2cache.tags.avg_refs 7.370374 # Average number of references to valid blocks.
788system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit.
789system.cpu.l2cache.tags.occ_blocks::writebacks 54484.622776 # Average occupied blocks per requestor
790system.cpu.l2cache.tags.occ_blocks::cpu.inst 10842.127094 # Average occupied blocks per requestor
791system.cpu.l2cache.tags.occ_percent::writebacks 0.831369 # Average percentage of cache occupancy
792system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165438 # Average percentage of cache occupancy
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795system.cpu.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
796system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1459 # Occupied blocks per task id
797system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5166 # Occupied blocks per task id
798system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2777 # Occupied blocks per task id
799system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id
800system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
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802system.cpu.l2cache.tags.data_accesses 30252211 # Number of data accesses
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804system.cpu.l2cache.ReadReq_hits::total 2261673 # number of ReadReq hits
805system.cpu.l2cache.Writeback_hits::writebacks 838282 # number of Writeback hits
806system.cpu.l2cache.Writeback_hits::total 838282 # number of Writeback hits
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808system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
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836system.cpu.l2cache.ReadReq_accesses::total 2550321 # number of ReadReq accesses(hits+misses)
837system.cpu.l2cache.Writeback_accesses::writebacks 838282 # number of Writeback accesses(hits+misses)
838system.cpu.l2cache.Writeback_accesses::total 838282 # number of Writeback accesses(hits+misses)
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840system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses)
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842system.cpu.l2cache.ReadExReq_accesses::total 304264 # number of ReadExReq accesses(hits+misses)
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846system.cpu.l2cache.overall_accesses::total 2854585 # number of overall (read+write) accesses
847system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113181 # miss rate for ReadReq accesses
848system.cpu.l2cache.ReadReq_miss_rate::total 0.113181 # miss rate for ReadReq accesses
849system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.833333 # miss rate for UpgradeReq accesses
850system.cpu.l2cache.UpgradeReq_miss_rate::total 0.833333 # miss rate for UpgradeReq accesses
851system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383470 # miss rate for ReadExReq accesses
852system.cpu.l2cache.ReadExReq_miss_rate::total 0.383470 # miss rate for ReadExReq accesses
853system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141991 # miss rate for demand accesses
854system.cpu.l2cache.demand_miss_rate::total 0.141991 # miss rate for demand accesses
855system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141991 # miss rate for overall accesses
856system.cpu.l2cache.overall_miss_rate::total 0.141991 # miss rate for overall accesses
857system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65512.016366 # average ReadReq miss latency
858system.cpu.l2cache.ReadReq_avg_miss_latency::total 65512.016366 # average ReadReq miss latency
859system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 5774.750000 # average UpgradeReq miss latency
860system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5774.750000 # average UpgradeReq miss latency
861system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69323.951481 # average ReadExReq miss latency
862system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69323.951481 # average ReadExReq miss latency
863system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66609.314679 # average overall miss latency
864system.cpu.l2cache.demand_avg_miss_latency::total 66609.314679 # average overall miss latency
865system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66609.314679 # average overall miss latency
866system.cpu.l2cache.overall_avg_miss_latency::total 66609.314679 # average overall miss latency
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869system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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871system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
872system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
873system.cpu.l2cache.fast_writes 0 # number of fast writes performed
874system.cpu.l2cache.cache_copies 0 # number of cache copies performed
875system.cpu.l2cache.writebacks::writebacks 76605 # number of writebacks
876system.cpu.l2cache.writebacks::total 76605 # number of writebacks
877system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288648 # number of ReadReq MSHR misses
878system.cpu.l2cache.ReadReq_mshr_misses::total 288648 # number of ReadReq MSHR misses
879system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 20 # number of UpgradeReq MSHR misses
880system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses
881system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116676 # number of ReadExReq MSHR misses
882system.cpu.l2cache.ReadExReq_mshr_misses::total 116676 # number of ReadExReq MSHR misses
883system.cpu.l2cache.demand_mshr_misses::cpu.inst 405324 # number of demand (read+write) MSHR misses
884system.cpu.l2cache.demand_mshr_misses::total 405324 # number of demand (read+write) MSHR misses
885system.cpu.l2cache.overall_mshr_misses::cpu.inst 405324 # number of overall MSHR misses
886system.cpu.l2cache.overall_mshr_misses::total 405324 # number of overall MSHR misses
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888system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15301161000 # number of ReadReq MSHR miss cycles
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890system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 201018 # number of UpgradeReq MSHR miss cycles
891system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6587763637 # number of ReadExReq MSHR miss cycles
892system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6587763637 # number of ReadExReq MSHR miss cycles
893system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21888924637 # number of demand (read+write) MSHR miss cycles
894system.cpu.l2cache.demand_mshr_miss_latency::total 21888924637 # number of demand (read+write) MSHR miss cycles
895system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21888924637 # number of overall MSHR miss cycles
896system.cpu.l2cache.overall_mshr_miss_latency::total 21888924637 # number of overall MSHR miss cycles
897system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333222000 # number of ReadReq MSHR uncacheable cycles
898system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333222000 # number of ReadReq MSHR uncacheable cycles
899system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887374000 # number of WriteReq MSHR uncacheable cycles
900system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887374000 # number of WriteReq MSHR uncacheable cycles
901system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3220596000 # number of overall MSHR uncacheable cycles
902system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3220596000 # number of overall MSHR uncacheable cycles
903system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113181 # mshr miss rate for ReadReq accesses
904system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113181 # mshr miss rate for ReadReq accesses
905system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.833333 # mshr miss rate for UpgradeReq accesses
906system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses
907system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383470 # mshr miss rate for ReadExReq accesses
908system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383470 # mshr miss rate for ReadExReq accesses
909system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141991 # mshr miss rate for demand accesses
910system.cpu.l2cache.demand_mshr_miss_rate::total 0.141991 # mshr miss rate for demand accesses
911system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141991 # mshr miss rate for overall accesses
912system.cpu.l2cache.overall_mshr_miss_rate::total 0.141991 # mshr miss rate for overall accesses
913system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53009.759292 # average ReadReq mshr miss latency
914system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53009.759292 # average ReadReq mshr miss latency
915system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10050.900000 # average UpgradeReq mshr miss latency
916system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10050.900000 # average UpgradeReq mshr miss latency
917system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56462.028498 # average ReadExReq mshr miss latency
918system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56462.028498 # average ReadExReq mshr miss latency
919system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54003.524679 # average overall mshr miss latency
920system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54003.524679 # average overall mshr miss latency
921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54003.524679 # average overall mshr miss latency
922system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54003.524679 # average overall mshr miss latency
923system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
924system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
925system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
926system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
927system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
928system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
929system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
930system.cpu.dcache.tags.replacements 1395422 # number of replacements
931system.cpu.dcache.tags.tagsinuse 511.982303 # Cycle average of tags in use
932system.cpu.dcache.tags.total_refs 13764943 # Total number of references to valid blocks.
933system.cpu.dcache.tags.sampled_refs 1395934 # Sample count of references to valid blocks.
934system.cpu.dcache.tags.avg_refs 9.860741 # Average number of references to valid blocks.
935system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit.
936system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982303 # Average occupied blocks per requestor
937system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy
938system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy
939system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
940system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id
941system.cpu.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
942system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
943system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
944system.cpu.dcache.tags.tag_accesses 63626016 # Number of tag accesses
945system.cpu.dcache.tags.data_accesses 63626016 # Number of data accesses
946system.cpu.dcache.ReadReq_hits::cpu.inst 7806784 # number of ReadReq hits
947system.cpu.dcache.ReadReq_hits::total 7806784 # number of ReadReq hits
948system.cpu.dcache.WriteReq_hits::cpu.inst 5576432 # number of WriteReq hits
949system.cpu.dcache.WriteReq_hits::total 5576432 # number of WriteReq hits
950system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182707 # number of LoadLockedReq hits
951system.cpu.dcache.LoadLockedReq_hits::total 182707 # number of LoadLockedReq hits
952system.cpu.dcache.StoreCondReq_hits::cpu.inst 198983 # number of StoreCondReq hits
953system.cpu.dcache.StoreCondReq_hits::total 198983 # number of StoreCondReq hits
954system.cpu.dcache.demand_hits::cpu.inst 13383216 # number of demand (read+write) hits
955system.cpu.dcache.demand_hits::total 13383216 # number of demand (read+write) hits
956system.cpu.dcache.overall_hits::cpu.inst 13383216 # number of overall hits
957system.cpu.dcache.overall_hits::total 13383216 # number of overall hits
958system.cpu.dcache.ReadReq_misses::cpu.inst 1201616 # number of ReadReq misses
959system.cpu.dcache.ReadReq_misses::total 1201616 # number of ReadReq misses
960system.cpu.dcache.WriteReq_misses::cpu.inst 573699 # number of WriteReq misses
961system.cpu.dcache.WriteReq_misses::total 573699 # number of WriteReq misses
962system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17299 # number of LoadLockedReq misses
963system.cpu.dcache.LoadLockedReq_misses::total 17299 # number of LoadLockedReq misses
964system.cpu.dcache.demand_misses::cpu.inst 1775315 # number of demand (read+write) misses
965system.cpu.dcache.demand_misses::total 1775315 # number of demand (read+write) misses
966system.cpu.dcache.overall_misses::cpu.inst 1775315 # number of overall misses
967system.cpu.dcache.overall_misses::total 1775315 # number of overall misses
968system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31018318500 # number of ReadReq miss cycles
969system.cpu.dcache.ReadReq_miss_latency::total 31018318500 # number of ReadReq miss cycles
970system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20748316044 # number of WriteReq miss cycles
971system.cpu.dcache.WriteReq_miss_latency::total 20748316044 # number of WriteReq miss cycles
972system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231689250 # number of LoadLockedReq miss cycles
973system.cpu.dcache.LoadLockedReq_miss_latency::total 231689250 # number of LoadLockedReq miss cycles
974system.cpu.dcache.demand_miss_latency::cpu.inst 51766634544 # number of demand (read+write) miss cycles
975system.cpu.dcache.demand_miss_latency::total 51766634544 # number of demand (read+write) miss cycles
976system.cpu.dcache.overall_miss_latency::cpu.inst 51766634544 # number of overall miss cycles
977system.cpu.dcache.overall_miss_latency::total 51766634544 # number of overall miss cycles
978system.cpu.dcache.ReadReq_accesses::cpu.inst 9008400 # number of ReadReq accesses(hits+misses)
979system.cpu.dcache.ReadReq_accesses::total 9008400 # number of ReadReq accesses(hits+misses)
980system.cpu.dcache.WriteReq_accesses::cpu.inst 6150131 # number of WriteReq accesses(hits+misses)
981system.cpu.dcache.WriteReq_accesses::total 6150131 # number of WriteReq accesses(hits+misses)
982system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200006 # number of LoadLockedReq accesses(hits+misses)
983system.cpu.dcache.LoadLockedReq_accesses::total 200006 # number of LoadLockedReq accesses(hits+misses)
984system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198983 # number of StoreCondReq accesses(hits+misses)
985system.cpu.dcache.StoreCondReq_accesses::total 198983 # number of StoreCondReq accesses(hits+misses)
986system.cpu.dcache.demand_accesses::cpu.inst 15158531 # number of demand (read+write) accesses
987system.cpu.dcache.demand_accesses::total 15158531 # number of demand (read+write) accesses
988system.cpu.dcache.overall_accesses::cpu.inst 15158531 # number of overall (read+write) accesses
989system.cpu.dcache.overall_accesses::total 15158531 # number of overall (read+write) accesses
990system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133388 # miss rate for ReadReq accesses
991system.cpu.dcache.ReadReq_miss_rate::total 0.133388 # miss rate for ReadReq accesses
992system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093282 # miss rate for WriteReq accesses
993system.cpu.dcache.WriteReq_miss_rate::total 0.093282 # miss rate for WriteReq accesses
994system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086492 # miss rate for LoadLockedReq accesses
995system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086492 # miss rate for LoadLockedReq accesses
996system.cpu.dcache.demand_miss_rate::cpu.inst 0.117117 # miss rate for demand accesses
997system.cpu.dcache.demand_miss_rate::total 0.117117 # miss rate for demand accesses
998system.cpu.dcache.overall_miss_rate::cpu.inst 0.117117 # miss rate for overall accesses
999system.cpu.dcache.overall_miss_rate::total 0.117117 # miss rate for overall accesses
1000system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25813.836117 # average ReadReq miss latency
1001system.cpu.dcache.ReadReq_avg_miss_latency::total 25813.836117 # average ReadReq miss latency
1002system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36165.857085 # average WriteReq miss latency
1003system.cpu.dcache.WriteReq_avg_miss_latency::total 36165.857085 # average WriteReq miss latency
1004system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13393.216371 # average LoadLockedReq miss latency
1005system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13393.216371 # average LoadLockedReq miss latency
1006system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency
1007system.cpu.dcache.demand_avg_miss_latency::total 29159.126433 # average overall miss latency
1008system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency
1009system.cpu.dcache.overall_avg_miss_latency::total 29159.126433 # average overall miss latency
1010system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1011system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1012system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1013system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1014system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1015system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1016system.cpu.dcache.fast_writes 0 # number of fast writes performed
1017system.cpu.dcache.cache_copies 0 # number of cache copies performed
1018system.cpu.dcache.writebacks::writebacks 838282 # number of writebacks
1019system.cpu.dcache.writebacks::total 838282 # number of writebacks
1020system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127187 # number of ReadReq MSHR hits
1021system.cpu.dcache.ReadReq_mshr_hits::total 127187 # number of ReadReq MSHR hits
1022system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269448 # number of WriteReq MSHR hits
1023system.cpu.dcache.WriteReq_mshr_hits::total 269448 # number of WriteReq MSHR hits
1024system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits
1025system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
1026system.cpu.dcache.demand_mshr_hits::cpu.inst 396635 # number of demand (read+write) MSHR hits
1027system.cpu.dcache.demand_mshr_hits::total 396635 # number of demand (read+write) MSHR hits
1028system.cpu.dcache.overall_mshr_hits::cpu.inst 396635 # number of overall MSHR hits
1029system.cpu.dcache.overall_mshr_hits::total 396635 # number of overall MSHR hits
1030system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074429 # number of ReadReq MSHR misses
1031system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses
1032system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304251 # number of WriteReq MSHR misses
1033system.cpu.dcache.WriteReq_mshr_misses::total 304251 # number of WriteReq MSHR misses
1034system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17296 # number of LoadLockedReq MSHR misses
1035system.cpu.dcache.LoadLockedReq_mshr_misses::total 17296 # number of LoadLockedReq MSHR misses
1036system.cpu.dcache.demand_mshr_misses::cpu.inst 1378680 # number of demand (read+write) MSHR misses
1037system.cpu.dcache.demand_mshr_misses::total 1378680 # number of demand (read+write) MSHR misses
1038system.cpu.dcache.overall_mshr_misses::cpu.inst 1378680 # number of overall MSHR misses
1039system.cpu.dcache.overall_mshr_misses::total 1378680 # number of overall MSHR misses
1040system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26906996250 # number of ReadReq MSHR miss cycles
1041system.cpu.dcache.ReadReq_mshr_miss_latency::total 26906996250 # number of ReadReq MSHR miss cycles
1042system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10272860843 # number of WriteReq MSHR miss cycles
1043system.cpu.dcache.WriteReq_mshr_miss_latency::total 10272860843 # number of WriteReq MSHR miss cycles
1044system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196930250 # number of LoadLockedReq MSHR miss cycles
1045system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196930250 # number of LoadLockedReq MSHR miss cycles
1046system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179857093 # number of demand (read+write) MSHR miss cycles
1047system.cpu.dcache.demand_mshr_miss_latency::total 37179857093 # number of demand (read+write) MSHR miss cycles
1048system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179857093 # number of overall MSHR miss cycles
1049system.cpu.dcache.overall_mshr_miss_latency::total 37179857093 # number of overall MSHR miss cycles
1050system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423313500 # number of ReadReq MSHR uncacheable cycles
1051system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423313500 # number of ReadReq MSHR uncacheable cycles
1052system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002790500 # number of WriteReq MSHR uncacheable cycles
1053system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002790500 # number of WriteReq MSHR uncacheable cycles
1054system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426104000 # number of overall MSHR uncacheable cycles
1055system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426104000 # number of overall MSHR uncacheable cycles
1056system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119270 # mshr miss rate for ReadReq accesses
1057system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119270 # mshr miss rate for ReadReq accesses
1058system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049471 # mshr miss rate for WriteReq accesses
1059system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses
1060system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086477 # mshr miss rate for LoadLockedReq accesses
1061system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086477 # mshr miss rate for LoadLockedReq accesses
1062system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for demand accesses
1063system.cpu.dcache.demand_mshr_miss_rate::total 0.090951 # mshr miss rate for demand accesses
1064system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for overall accesses
1065system.cpu.dcache.overall_mshr_miss_rate::total 0.090951 # mshr miss rate for overall accesses
1066system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25043.065898 # average ReadReq mshr miss latency
1067system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.065898 # average ReadReq mshr miss latency
1068system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33764.427538 # average WriteReq mshr miss latency
1069system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33764.427538 # average WriteReq mshr miss latency
1070system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11385.884019 # average LoadLockedReq mshr miss latency
1071system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11385.884019 # average LoadLockedReq mshr miss latency
1072system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency
1073system.cpu.dcache.demand_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency
1074system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency
1075system.cpu.dcache.overall_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency
1076system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1077system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1078system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
1079system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1080system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1081system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1082system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1083
1084---------- End Simulation Statistics ----------