1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.906052 # Number of seconds simulated
4sim_ticks 1906052165500 # Number of ticks simulated
5final_tick 1906052165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 263346 # Simulator instruction rate (inst/s)
8host_op_rate 263346 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 8940174363 # Simulator tick rate (ticks/s)
10host_mem_usage 335264 # Number of bytes of host memory used
11host_seconds 213.20 # Real time elapsed on the host
12sim_insts 56145499 # Number of instructions simulated
13sim_ops 56145499 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 1044672 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24858688 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::total 25904320 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 1044672 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 1044672 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 7563072 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7563072 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 16323 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 388417 # Number of read requests responded to by this memory
26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 404755 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 118173 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 118173 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 548082 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 13041977 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 13590562 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 548082 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 548082 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 3967925 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 3967925 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 3967925 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 548082 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 13041977 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 17558487 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 404755 # Number of read requests accepted
44system.physmem.writeReqs 118173 # Number of write requests accepted
45system.physmem.readBursts 404755 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 118173 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 25897216 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
49system.physmem.bytesWritten 7561728 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 25904320 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 7563072 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 25477 # Per bank write bursts
56system.physmem.perBankRdBursts::1 25704 # Per bank write bursts
57system.physmem.perBankRdBursts::2 25816 # Per bank write bursts
58system.physmem.perBankRdBursts::3 25781 # Per bank write bursts
59system.physmem.perBankRdBursts::4 25083 # Per bank write bursts
60system.physmem.perBankRdBursts::5 25010 # Per bank write bursts
61system.physmem.perBankRdBursts::6 24709 # Per bank write bursts
62system.physmem.perBankRdBursts::7 24576 # Per bank write bursts
63system.physmem.perBankRdBursts::8 25196 # Per bank write bursts
64system.physmem.perBankRdBursts::9 25297 # Per bank write bursts
65system.physmem.perBankRdBursts::10 25389 # Per bank write bursts
66system.physmem.perBankRdBursts::11 25021 # Per bank write bursts
67system.physmem.perBankRdBursts::12 24534 # Per bank write bursts
68system.physmem.perBankRdBursts::13 25530 # Per bank write bursts
69system.physmem.perBankRdBursts::14 25795 # Per bank write bursts
70system.physmem.perBankRdBursts::15 25726 # Per bank write bursts
71system.physmem.perBankWrBursts::0 7822 # Per bank write bursts
72system.physmem.perBankWrBursts::1 7672 # Per bank write bursts
73system.physmem.perBankWrBursts::2 8075 # Per bank write bursts
74system.physmem.perBankWrBursts::3 7745 # Per bank write bursts
75system.physmem.perBankWrBursts::4 7196 # Per bank write bursts
76system.physmem.perBankWrBursts::5 7016 # Per bank write bursts
77system.physmem.perBankWrBursts::6 6702 # Per bank write bursts
78system.physmem.perBankWrBursts::7 6427 # Per bank write bursts
79system.physmem.perBankWrBursts::8 7309 # Per bank write bursts
80system.physmem.perBankWrBursts::9 6908 # Per bank write bursts
81system.physmem.perBankWrBursts::10 7271 # Per bank write bursts
82system.physmem.perBankWrBursts::11 7002 # Per bank write bursts
83system.physmem.perBankWrBursts::12 7086 # Per bank write bursts
84system.physmem.perBankWrBursts::13 7981 # Per bank write bursts
85system.physmem.perBankWrBursts::14 7993 # Per bank write bursts
86system.physmem.perBankWrBursts::15 7947 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
89system.physmem.totGap 1906043365500 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 404755 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 118173 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 402408 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 2161 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see

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143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 1528 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 2966 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 7248 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 5892 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 6862 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 6013 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 5964 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 6411 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 6987 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 6497 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 8431 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 8614 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 7309 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 7697 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 6993 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 7144 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 6015 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 5600 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 258 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 151 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 113 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 186 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 125 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 106 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 120 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 106 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 138 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 189 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 168 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 259 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 147 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 162 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 132 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 126 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 76 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 67 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 121 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 39 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 64457 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 519.089377 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 317.985274 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 407.069012 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 14849 23.04% 23.04% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 11122 17.25% 40.29% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 4951 7.68% 47.97% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 3330 5.17% 53.14% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 2494 3.87% 57.01% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 1955 3.03% 60.04% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 4176 6.48% 66.52% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 1342 2.08% 68.60% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 20238 31.40% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 64457 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 5292 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 76.462207 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::stdev 2902.463532 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::0-8191 5289 99.94% 99.94% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::total 5292 # Reads before turning the bus around for writes
222system.physmem.wrPerTurnAround::samples 5292 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::mean 22.326531 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::gmean 19.072850 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::stdev 20.540172 # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::16-23 4687 88.57% 88.57% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::24-31 34 0.64% 89.21% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::32-39 32 0.60% 89.81% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::40-47 42 0.79% 90.61% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::48-55 211 3.99% 94.60% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::56-63 8 0.15% 94.75% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::64-71 13 0.25% 94.99% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::72-79 25 0.47% 95.46% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::80-87 188 3.55% 99.02% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::88-95 3 0.06% 99.07% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::96-103 3 0.06% 99.13% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::104-111 3 0.06% 99.19% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::128-135 5 0.09% 99.28% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::136-143 1 0.02% 99.30% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::144-151 1 0.02% 99.32% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::152-159 1 0.02% 99.34% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::160-167 1 0.02% 99.36% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::168-175 11 0.21% 99.57% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::176-183 9 0.17% 99.74% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::184-191 3 0.06% 99.79% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::192-199 1 0.02% 99.81% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::200-207 3 0.06% 99.87% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::208-215 5 0.09% 99.96% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::total 5292 # Writes before turning the bus around for reads
251system.physmem.totQLat 2635925000 # Total ticks spent queuing
252system.physmem.totMemAccLat 10223000000 # Total ticks spent from burst creation until serviced by the DRAM
253system.physmem.totBusLat 2023220000 # Total ticks spent in databus transfers
254system.physmem.avgQLat 6514.18 # Average queueing delay per DRAM burst
255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
256system.physmem.avgMemAccLat 25264.18 # Average memory access latency per DRAM burst
257system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s
258system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s
259system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s
260system.physmem.avgWrBWSys 3.97 # Average system write bandwidth in MiByte/s
261system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
262system.physmem.busUtil 0.14 # Data bus utilization in percentage
263system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
264system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
265system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
266system.physmem.avgWrQLen 26.36 # Average write queue length when enqueuing
267system.physmem.readRowHits 362809 # Number of row buffer hits during reads
268system.physmem.writeRowHits 95530 # Number of row buffer hits during writes
269system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads
270system.physmem.writeRowHitRate 80.84 # Row buffer hit rate for writes
271system.physmem.avgGap 3644944.17 # Average gap between requests
272system.physmem.pageHitRate 87.67 # Row buffer hit rate, read and write combined
273system.physmem_0.actEnergy 238124880 # Energy for activate commands per rank (pJ)
274system.physmem_0.preEnergy 129929250 # Energy for precharge commands per rank (pJ)
275system.physmem_0.readEnergy 1576816800 # Energy for read commands per rank (pJ)
276system.physmem_0.writeEnergy 380084400 # Energy for write commands per rank (pJ)
277system.physmem_0.refreshEnergy 124493962320 # Energy for refresh commands per rank (pJ)
278system.physmem_0.actBackEnergy 67910384250 # Energy for active background per rank (pJ)
279system.physmem_0.preBackEnergy 1084060020000 # Energy for precharge background per rank (pJ)
280system.physmem_0.totalEnergy 1278789321900 # Total energy per rank (pJ)
281system.physmem_0.averagePower 670.910378 # Core power per rank (mW)
282system.physmem_0.memoryStateTime::IDLE 1803172860750 # Time in different power states
283system.physmem_0.memoryStateTime::REF 63647220000 # Time in different power states
284system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
285system.physmem_0.memoryStateTime::ACT 39230820500 # Time in different power states
286system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
287system.physmem_1.actEnergy 249170040 # Energy for activate commands per rank (pJ)
288system.physmem_1.preEnergy 135955875 # Energy for precharge commands per rank (pJ)
289system.physmem_1.readEnergy 1579406400 # Energy for read commands per rank (pJ)
290system.physmem_1.writeEnergy 385540560 # Energy for write commands per rank (pJ)
291system.physmem_1.refreshEnergy 124493962320 # Energy for refresh commands per rank (pJ)
292system.physmem_1.actBackEnergy 68468592375 # Energy for active background per rank (pJ)
293system.physmem_1.preBackEnergy 1083570372000 # Energy for precharge background per rank (pJ)
294system.physmem_1.totalEnergy 1278882999570 # Total energy per rank (pJ)
295system.physmem_1.averagePower 670.959521 # Core power per rank (mW)
296system.physmem_1.memoryStateTime::IDLE 1802360809750 # Time in different power states
297system.physmem_1.memoryStateTime::REF 63647220000 # Time in different power states
298system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
299system.physmem_1.memoryStateTime::ACT 40042885250 # Time in different power states
300system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
301system.cpu.branchPred.lookups 15006509 # Number of BP lookups
302system.cpu.branchPred.condPredicted 13016597 # Number of conditional branches predicted
303system.cpu.branchPred.condIncorrect 371031 # Number of conditional branches incorrect
304system.cpu.branchPred.BTBLookups 9764467 # Number of BTB lookups
305system.cpu.branchPred.BTBHits 5201318 # Number of BTB hits
306system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
307system.cpu.branchPred.BTBHitPct 53.267813 # BTB Hit Percentage
308system.cpu.branchPred.usedRAS 807808 # Number of times the RAS was used to get a target.
309system.cpu.branchPred.RASInCorrect 31462 # Number of incorrect RAS predictions.
310system.cpu_clk_domain.clock 500 # Clock period in ticks
311system.cpu.dtb.fetch_hits 0 # ITB hits
312system.cpu.dtb.fetch_misses 0 # ITB misses
313system.cpu.dtb.fetch_acv 0 # ITB acv
314system.cpu.dtb.fetch_accesses 0 # ITB accesses
315system.cpu.dtb.read_hits 9242631 # DTB read hits
316system.cpu.dtb.read_misses 17134 # DTB read misses
317system.cpu.dtb.read_acv 211 # DTB read access violations
318system.cpu.dtb.read_accesses 765515 # DTB read accesses
319system.cpu.dtb.write_hits 6388389 # DTB write hits
320system.cpu.dtb.write_misses 2336 # DTB write misses
321system.cpu.dtb.write_acv 160 # DTB write access violations
322system.cpu.dtb.write_accesses 298460 # DTB write accesses
323system.cpu.dtb.data_hits 15631020 # DTB hits
324system.cpu.dtb.data_misses 19470 # DTB misses
325system.cpu.dtb.data_acv 371 # DTB access violations
326system.cpu.dtb.data_accesses 1063975 # DTB accesses
327system.cpu.itb.fetch_hits 4014011 # ITB hits
328system.cpu.itb.fetch_misses 6826 # ITB misses
329system.cpu.itb.fetch_acv 642 # ITB acv
330system.cpu.itb.fetch_accesses 4020837 # ITB accesses
331system.cpu.itb.read_hits 0 # DTB read hits
332system.cpu.itb.read_misses 0 # DTB read misses
333system.cpu.itb.read_acv 0 # DTB read access violations
334system.cpu.itb.read_accesses 0 # DTB read accesses
335system.cpu.itb.write_hits 0 # DTB write hits
336system.cpu.itb.write_misses 0 # DTB write misses
337system.cpu.itb.write_acv 0 # DTB write access violations
338system.cpu.itb.write_accesses 0 # DTB write accesses
339system.cpu.itb.data_hits 0 # DTB hits
340system.cpu.itb.data_misses 0 # DTB misses
341system.cpu.itb.data_acv 0 # DTB access violations
342system.cpu.itb.data_accesses 0 # DTB accesses
343system.cpu.numCycles 221712638 # number of cpu cycles simulated
344system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
345system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
346system.cpu.committedInsts 56145499 # Number of instructions committed
347system.cpu.committedOps 56145499 # Number of ops (including micro ops) committed
348system.cpu.discardedOps 2504937 # Number of ops (including micro ops) which were discarded before commit
349system.cpu.numFetchSuspends 5531 # Number of times Execute suspended instruction fetching
350system.cpu.quiesceCycles 3590391693 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
351system.cpu.cpi 3.948894 # CPI: cycles per instruction
352system.cpu.ipc 0.253235 # IPC: instructions per cycle
353system.cpu.kern.inst.arm 0 # number of arm instructions executed
354system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed
355system.cpu.kern.inst.hwrei 211539 # number of hwrei instructions executed
356system.cpu.kern.ipl_count::0 74805 40.93% 40.93% # number of times we switched to this ipl
357system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl
358system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl
359system.cpu.kern.ipl_count::31 105907 57.95% 100.00% # number of times we switched to this ipl
360system.cpu.kern.ipl_count::total 182749 # number of times we switched to this ipl
361system.cpu.kern.ipl_good::0 73438 49.32% 49.32% # number of times we switched to this ipl from a different ipl
362system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl
363system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl
364system.cpu.kern.ipl_good::31 73439 49.32% 100.00% # number of times we switched to this ipl from a different ipl
365system.cpu.kern.ipl_good::total 148914 # number of times we switched to this ipl from a different ipl
366system.cpu.kern.ipl_ticks::0 1837274169000 96.39% 96.39% # number of cycles we spent at this ipl
367system.cpu.kern.ipl_ticks::21 83596500 0.00% 96.40% # number of cycles we spent at this ipl
368system.cpu.kern.ipl_ticks::22 707455500 0.04% 96.43% # number of cycles we spent at this ipl
369system.cpu.kern.ipl_ticks::31 67985922500 3.57% 100.00% # number of cycles we spent at this ipl
370system.cpu.kern.ipl_ticks::total 1906051143500 # number of cycles we spent at this ipl
371system.cpu.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl
372system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
373system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
374system.cpu.kern.ipl_used::31 0.693429 # fraction of swpipl calls that actually changed the ipl
375system.cpu.kern.ipl_used::total 0.814855 # fraction of swpipl calls that actually changed the ipl
376system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
377system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
378system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
379system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
380system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
381system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
382system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
383system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed

--- 22 unchanged lines hidden (view full) ---

406system.cpu.kern.syscall::total 326 # number of syscalls executed
407system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
408system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
409system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
410system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
411system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
412system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
413system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
414system.cpu.kern.callpal::swpipl 175582 91.22% 93.43% # number of callpals executed
415system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed
416system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
417system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
418system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
419system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
420system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed
421system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
422system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
423system.cpu.kern.callpal::total 192473 # number of callpals executed
424system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches
425system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
426system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
427system.cpu.kern.mode_good::kernel 1907
428system.cpu.kern.mode_good::user 1738
429system.cpu.kern.mode_good::idle 169
430system.cpu.kern.mode_switch_good::kernel 0.324541 # fraction of useful protection mode switches
431system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
432system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
433system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches
434system.cpu.kern.mode_ticks::kernel 38725166000 2.03% 2.03% # number of ticks spent at the given mode
435system.cpu.kern.mode_ticks::user 4529345500 0.24% 2.27% # number of ticks spent at the given mode
436system.cpu.kern.mode_ticks::idle 1862796622000 97.73% 100.00% # number of ticks spent at the given mode
437system.cpu.kern.swap_context 4175 # number of times the context was actually changed
438system.cpu.tickCycles 84517271 # Number of cycles that the object actually ticked
439system.cpu.idleCycles 137195367 # Total number of cycles that the object has spent stopped
440system.cpu.dcache.tags.replacements 1395430 # number of replacements
441system.cpu.dcache.tags.tagsinuse 511.976766 # Cycle average of tags in use
442system.cpu.dcache.tags.total_refs 13774435 # Total number of references to valid blocks.
443system.cpu.dcache.tags.sampled_refs 1395942 # Sample count of references to valid blocks.
444system.cpu.dcache.tags.avg_refs 9.867484 # Average number of references to valid blocks.
445system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit.
446system.cpu.dcache.tags.occ_blocks::cpu.data 511.976766 # Average occupied blocks per requestor
447system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy
448system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy
449system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
450system.cpu.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id
451system.cpu.dcache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
452system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
453system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
454system.cpu.dcache.tags.tag_accesses 63669791 # Number of tag accesses
455system.cpu.dcache.tags.data_accesses 63669791 # Number of data accesses
456system.cpu.dcache.ReadReq_hits::cpu.data 7815717 # number of ReadReq hits
457system.cpu.dcache.ReadReq_hits::total 7815717 # number of ReadReq hits
458system.cpu.dcache.WriteReq_hits::cpu.data 5576828 # number of WriteReq hits
459system.cpu.dcache.WriteReq_hits::total 5576828 # number of WriteReq hits
460system.cpu.dcache.LoadLockedReq_hits::cpu.data 182828 # number of LoadLockedReq hits
461system.cpu.dcache.LoadLockedReq_hits::total 182828 # number of LoadLockedReq hits
462system.cpu.dcache.StoreCondReq_hits::cpu.data 199029 # number of StoreCondReq hits
463system.cpu.dcache.StoreCondReq_hits::total 199029 # number of StoreCondReq hits
464system.cpu.dcache.demand_hits::cpu.data 13392545 # number of demand (read+write) hits
465system.cpu.dcache.demand_hits::total 13392545 # number of demand (read+write) hits
466system.cpu.dcache.overall_hits::cpu.data 13392545 # number of overall hits
467system.cpu.dcache.overall_hits::total 13392545 # number of overall hits
468system.cpu.dcache.ReadReq_misses::cpu.data 1201618 # number of ReadReq misses
469system.cpu.dcache.ReadReq_misses::total 1201618 # number of ReadReq misses
470system.cpu.dcache.WriteReq_misses::cpu.data 575220 # number of WriteReq misses
471system.cpu.dcache.WriteReq_misses::total 575220 # number of WriteReq misses
472system.cpu.dcache.LoadLockedReq_misses::cpu.data 17222 # number of LoadLockedReq misses
473system.cpu.dcache.LoadLockedReq_misses::total 17222 # number of LoadLockedReq misses
474system.cpu.dcache.demand_misses::cpu.data 1776838 # number of demand (read+write) misses
475system.cpu.dcache.demand_misses::total 1776838 # number of demand (read+write) misses
476system.cpu.dcache.overall_misses::cpu.data 1776838 # number of overall misses
477system.cpu.dcache.overall_misses::total 1776838 # number of overall misses
478system.cpu.dcache.ReadReq_miss_latency::cpu.data 46968047500 # number of ReadReq miss cycles
479system.cpu.dcache.ReadReq_miss_latency::total 46968047500 # number of ReadReq miss cycles
480system.cpu.dcache.WriteReq_miss_latency::cpu.data 33964546500 # number of WriteReq miss cycles
481system.cpu.dcache.WriteReq_miss_latency::total 33964546500 # number of WriteReq miss cycles
482system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234897500 # number of LoadLockedReq miss cycles
483system.cpu.dcache.LoadLockedReq_miss_latency::total 234897500 # number of LoadLockedReq miss cycles
484system.cpu.dcache.demand_miss_latency::cpu.data 80932594000 # number of demand (read+write) miss cycles
485system.cpu.dcache.demand_miss_latency::total 80932594000 # number of demand (read+write) miss cycles
486system.cpu.dcache.overall_miss_latency::cpu.data 80932594000 # number of overall miss cycles
487system.cpu.dcache.overall_miss_latency::total 80932594000 # number of overall miss cycles
488system.cpu.dcache.ReadReq_accesses::cpu.data 9017335 # number of ReadReq accesses(hits+misses)
489system.cpu.dcache.ReadReq_accesses::total 9017335 # number of ReadReq accesses(hits+misses)
490system.cpu.dcache.WriteReq_accesses::cpu.data 6152048 # number of WriteReq accesses(hits+misses)
491system.cpu.dcache.WriteReq_accesses::total 6152048 # number of WriteReq accesses(hits+misses)
492system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200050 # number of LoadLockedReq accesses(hits+misses)
493system.cpu.dcache.LoadLockedReq_accesses::total 200050 # number of LoadLockedReq accesses(hits+misses)
494system.cpu.dcache.StoreCondReq_accesses::cpu.data 199029 # number of StoreCondReq accesses(hits+misses)
495system.cpu.dcache.StoreCondReq_accesses::total 199029 # number of StoreCondReq accesses(hits+misses)
496system.cpu.dcache.demand_accesses::cpu.data 15169383 # number of demand (read+write) accesses
497system.cpu.dcache.demand_accesses::total 15169383 # number of demand (read+write) accesses
498system.cpu.dcache.overall_accesses::cpu.data 15169383 # number of overall (read+write) accesses
499system.cpu.dcache.overall_accesses::total 15169383 # number of overall (read+write) accesses
500system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133256 # miss rate for ReadReq accesses
501system.cpu.dcache.ReadReq_miss_rate::total 0.133256 # miss rate for ReadReq accesses
502system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093501 # miss rate for WriteReq accesses
503system.cpu.dcache.WriteReq_miss_rate::total 0.093501 # miss rate for WriteReq accesses
504system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086088 # miss rate for LoadLockedReq accesses
505system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086088 # miss rate for LoadLockedReq accesses
506system.cpu.dcache.demand_miss_rate::cpu.data 0.117133 # miss rate for demand accesses
507system.cpu.dcache.demand_miss_rate::total 0.117133 # miss rate for demand accesses
508system.cpu.dcache.overall_miss_rate::cpu.data 0.117133 # miss rate for overall accesses
509system.cpu.dcache.overall_miss_rate::total 0.117133 # miss rate for overall accesses
510system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39087.336824 # average ReadReq miss latency
511system.cpu.dcache.ReadReq_avg_miss_latency::total 39087.336824 # average ReadReq miss latency
512system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59046.184938 # average WriteReq miss latency
513system.cpu.dcache.WriteReq_avg_miss_latency::total 59046.184938 # average WriteReq miss latency
514system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13639.385669 # average LoadLockedReq miss latency
515system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13639.385669 # average LoadLockedReq miss latency
516system.cpu.dcache.demand_avg_miss_latency::cpu.data 45548.662287 # average overall miss latency
517system.cpu.dcache.demand_avg_miss_latency::total 45548.662287 # average overall miss latency
518system.cpu.dcache.overall_avg_miss_latency::cpu.data 45548.662287 # average overall miss latency
519system.cpu.dcache.overall_avg_miss_latency::total 45548.662287 # average overall miss latency
520system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
521system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
522system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
523system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
524system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
525system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
526system.cpu.dcache.fast_writes 0 # number of fast writes performed
527system.cpu.dcache.cache_copies 0 # number of cache copies performed
528system.cpu.dcache.writebacks::writebacks 838230 # number of writebacks
529system.cpu.dcache.writebacks::total 838230 # number of writebacks
530system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127262 # number of ReadReq MSHR hits
531system.cpu.dcache.ReadReq_mshr_hits::total 127262 # number of ReadReq MSHR hits
532system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270814 # number of WriteReq MSHR hits
533system.cpu.dcache.WriteReq_mshr_hits::total 270814 # number of WriteReq MSHR hits
534system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
535system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
536system.cpu.dcache.demand_mshr_hits::cpu.data 398076 # number of demand (read+write) MSHR hits
537system.cpu.dcache.demand_mshr_hits::total 398076 # number of demand (read+write) MSHR hits
538system.cpu.dcache.overall_mshr_hits::cpu.data 398076 # number of overall MSHR hits
539system.cpu.dcache.overall_mshr_hits::total 398076 # number of overall MSHR hits
540system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074356 # number of ReadReq MSHR misses
541system.cpu.dcache.ReadReq_mshr_misses::total 1074356 # number of ReadReq MSHR misses
542system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304406 # number of WriteReq MSHR misses
543system.cpu.dcache.WriteReq_mshr_misses::total 304406 # number of WriteReq MSHR misses
544system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses
545system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses
546system.cpu.dcache.demand_mshr_misses::cpu.data 1378762 # number of demand (read+write) MSHR misses
547system.cpu.dcache.demand_mshr_misses::total 1378762 # number of demand (read+write) MSHR misses
548system.cpu.dcache.overall_mshr_misses::cpu.data 1378762 # number of overall MSHR misses
549system.cpu.dcache.overall_mshr_misses::total 1378762 # number of overall MSHR misses
550system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable
551system.cpu.dcache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable
552system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable
553system.cpu.dcache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable
554system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses
555system.cpu.dcache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses
556system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43812536500 # number of ReadReq MSHR miss cycles
557system.cpu.dcache.ReadReq_mshr_miss_latency::total 43812536500 # number of ReadReq MSHR miss cycles
558system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17276327500 # number of WriteReq MSHR miss cycles
559system.cpu.dcache.WriteReq_mshr_miss_latency::total 17276327500 # number of WriteReq MSHR miss cycles
560system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 217413000 # number of LoadLockedReq MSHR miss cycles
561system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217413000 # number of LoadLockedReq MSHR miss cycles
562system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61088864000 # number of demand (read+write) MSHR miss cycles
563system.cpu.dcache.demand_mshr_miss_latency::total 61088864000 # number of demand (read+write) MSHR miss cycles
564system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61088864000 # number of overall MSHR miss cycles
565system.cpu.dcache.overall_mshr_miss_latency::total 61088864000 # number of overall MSHR miss cycles
566system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529368000 # number of ReadReq MSHR uncacheable cycles
567system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529368000 # number of ReadReq MSHR uncacheable cycles
568system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2162483000 # number of WriteReq MSHR uncacheable cycles
569system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2162483000 # number of WriteReq MSHR uncacheable cycles
570system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3691851000 # number of overall MSHR uncacheable cycles
571system.cpu.dcache.overall_mshr_uncacheable_latency::total 3691851000 # number of overall MSHR uncacheable cycles
572system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119143 # mshr miss rate for ReadReq accesses
573system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119143 # mshr miss rate for ReadReq accesses
574system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049480 # mshr miss rate for WriteReq accesses
575system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049480 # mshr miss rate for WriteReq accesses
576system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086073 # mshr miss rate for LoadLockedReq accesses
577system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086073 # mshr miss rate for LoadLockedReq accesses
578system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090891 # mshr miss rate for demand accesses
579system.cpu.dcache.demand_mshr_miss_rate::total 0.090891 # mshr miss rate for demand accesses
580system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090891 # mshr miss rate for overall accesses
581system.cpu.dcache.overall_mshr_miss_rate::total 0.090891 # mshr miss rate for overall accesses
582system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40780.278139 # average ReadReq mshr miss latency
583system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40780.278139 # average ReadReq mshr miss latency
584system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56754.227906 # average WriteReq mshr miss latency
585system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56754.227906 # average WriteReq mshr miss latency
586system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12626.342993 # average LoadLockedReq mshr miss latency
587system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12626.342993 # average LoadLockedReq mshr miss latency
588system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.040664 # average overall mshr miss latency
589system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.040664 # average overall mshr miss latency
590system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.040664 # average overall mshr miss latency
591system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.040664 # average overall mshr miss latency
592system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.715316 # average ReadReq mshr uncacheable latency
593system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.715316 # average ReadReq mshr uncacheable latency
594system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224696.903574 # average WriteReq mshr uncacheable latency
595system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224696.903574 # average WriteReq mshr uncacheable latency
596system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222964.790434 # average overall mshr uncacheable latency
597system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222964.790434 # average overall mshr uncacheable latency
598system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
599system.cpu.icache.tags.replacements 1460482 # number of replacements
600system.cpu.icache.tags.tagsinuse 508.105568 # Cycle average of tags in use
601system.cpu.icache.tags.total_refs 18950550 # Total number of references to valid blocks.
602system.cpu.icache.tags.sampled_refs 1460993 # Sample count of references to valid blocks.
603system.cpu.icache.tags.avg_refs 12.971007 # Average number of references to valid blocks.
604system.cpu.icache.tags.warmup_cycle 50119711500 # Cycle when the warmup percentage was hit.
605system.cpu.icache.tags.occ_blocks::cpu.inst 508.105568 # Average occupied blocks per requestor
606system.cpu.icache.tags.occ_percent::cpu.inst 0.992394 # Average percentage of cache occupancy
607system.cpu.icache.tags.occ_percent::total 0.992394 # Average percentage of cache occupancy
608system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
609system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
610system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
611system.cpu.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id
612system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
613system.cpu.icache.tags.tag_accesses 21872887 # Number of tag accesses
614system.cpu.icache.tags.data_accesses 21872887 # Number of data accesses
615system.cpu.icache.ReadReq_hits::cpu.inst 18950553 # number of ReadReq hits
616system.cpu.icache.ReadReq_hits::total 18950553 # number of ReadReq hits
617system.cpu.icache.demand_hits::cpu.inst 18950553 # number of demand (read+write) hits
618system.cpu.icache.demand_hits::total 18950553 # number of demand (read+write) hits
619system.cpu.icache.overall_hits::cpu.inst 18950553 # number of overall hits
620system.cpu.icache.overall_hits::total 18950553 # number of overall hits
621system.cpu.icache.ReadReq_misses::cpu.inst 1461167 # number of ReadReq misses
622system.cpu.icache.ReadReq_misses::total 1461167 # number of ReadReq misses
623system.cpu.icache.demand_misses::cpu.inst 1461167 # number of demand (read+write) misses
624system.cpu.icache.demand_misses::total 1461167 # number of demand (read+write) misses
625system.cpu.icache.overall_misses::cpu.inst 1461167 # number of overall misses
626system.cpu.icache.overall_misses::total 1461167 # number of overall misses
627system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009920000 # number of ReadReq miss cycles
628system.cpu.icache.ReadReq_miss_latency::total 21009920000 # number of ReadReq miss cycles
629system.cpu.icache.demand_miss_latency::cpu.inst 21009920000 # number of demand (read+write) miss cycles
630system.cpu.icache.demand_miss_latency::total 21009920000 # number of demand (read+write) miss cycles
631system.cpu.icache.overall_miss_latency::cpu.inst 21009920000 # number of overall miss cycles
632system.cpu.icache.overall_miss_latency::total 21009920000 # number of overall miss cycles
633system.cpu.icache.ReadReq_accesses::cpu.inst 20411720 # number of ReadReq accesses(hits+misses)
634system.cpu.icache.ReadReq_accesses::total 20411720 # number of ReadReq accesses(hits+misses)
635system.cpu.icache.demand_accesses::cpu.inst 20411720 # number of demand (read+write) accesses
636system.cpu.icache.demand_accesses::total 20411720 # number of demand (read+write) accesses
637system.cpu.icache.overall_accesses::cpu.inst 20411720 # number of overall (read+write) accesses
638system.cpu.icache.overall_accesses::total 20411720 # number of overall (read+write) accesses
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640system.cpu.icache.ReadReq_miss_rate::total 0.071585 # miss rate for ReadReq accesses
641system.cpu.icache.demand_miss_rate::cpu.inst 0.071585 # miss rate for demand accesses
642system.cpu.icache.demand_miss_rate::total 0.071585 # miss rate for demand accesses
643system.cpu.icache.overall_miss_rate::cpu.inst 0.071585 # miss rate for overall accesses
644system.cpu.icache.overall_miss_rate::total 0.071585 # miss rate for overall accesses
645system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14378.862923 # average ReadReq miss latency
646system.cpu.icache.ReadReq_avg_miss_latency::total 14378.862923 # average ReadReq miss latency
647system.cpu.icache.demand_avg_miss_latency::cpu.inst 14378.862923 # average overall miss latency
648system.cpu.icache.demand_avg_miss_latency::total 14378.862923 # average overall miss latency
649system.cpu.icache.overall_avg_miss_latency::cpu.inst 14378.862923 # average overall miss latency
650system.cpu.icache.overall_avg_miss_latency::total 14378.862923 # average overall miss latency
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652system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
653system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
654system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
655system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
656system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
657system.cpu.icache.fast_writes 0 # number of fast writes performed
658system.cpu.icache.cache_copies 0 # number of cache copies performed
659system.cpu.icache.writebacks::writebacks 1460482 # number of writebacks
660system.cpu.icache.writebacks::total 1460482 # number of writebacks
661system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1461167 # number of ReadReq MSHR misses
662system.cpu.icache.ReadReq_mshr_misses::total 1461167 # number of ReadReq MSHR misses
663system.cpu.icache.demand_mshr_misses::cpu.inst 1461167 # number of demand (read+write) MSHR misses
664system.cpu.icache.demand_mshr_misses::total 1461167 # number of demand (read+write) MSHR misses
665system.cpu.icache.overall_mshr_misses::cpu.inst 1461167 # number of overall MSHR misses
666system.cpu.icache.overall_mshr_misses::total 1461167 # number of overall MSHR misses
667system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548753000 # number of ReadReq MSHR miss cycles
668system.cpu.icache.ReadReq_mshr_miss_latency::total 19548753000 # number of ReadReq MSHR miss cycles
669system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548753000 # number of demand (read+write) MSHR miss cycles
670system.cpu.icache.demand_mshr_miss_latency::total 19548753000 # number of demand (read+write) MSHR miss cycles
671system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548753000 # number of overall MSHR miss cycles
672system.cpu.icache.overall_mshr_miss_latency::total 19548753000 # number of overall MSHR miss cycles
673system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071585 # mshr miss rate for ReadReq accesses
674system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071585 # mshr miss rate for ReadReq accesses
675system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071585 # mshr miss rate for demand accesses
676system.cpu.icache.demand_mshr_miss_rate::total 0.071585 # mshr miss rate for demand accesses
677system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071585 # mshr miss rate for overall accesses
678system.cpu.icache.overall_mshr_miss_rate::total 0.071585 # mshr miss rate for overall accesses
679system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13378.862923 # average ReadReq mshr miss latency
680system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13378.862923 # average ReadReq mshr miss latency
681system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13378.862923 # average overall mshr miss latency
682system.cpu.icache.demand_avg_mshr_miss_latency::total 13378.862923 # average overall mshr miss latency
683system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13378.862923 # average overall mshr miss latency
684system.cpu.icache.overall_avg_mshr_miss_latency::total 13378.862923 # average overall mshr miss latency
685system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
686system.cpu.l2cache.tags.replacements 339567 # number of replacements
687system.cpu.l2cache.tags.tagsinuse 65260.796606 # Cycle average of tags in use
688system.cpu.l2cache.tags.total_refs 4999675 # Total number of references to valid blocks.
689system.cpu.l2cache.tags.sampled_refs 404729 # Sample count of references to valid blocks.
690system.cpu.l2cache.tags.avg_refs 12.353142 # Average number of references to valid blocks.
691system.cpu.l2cache.tags.warmup_cycle 9687465000 # Cycle when the warmup percentage was hit.
692system.cpu.l2cache.tags.occ_blocks::writebacks 54046.207258 # Average occupied blocks per requestor
693system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.432786 # Average occupied blocks per requestor
694system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.156561 # Average occupied blocks per requestor
695system.cpu.l2cache.tags.occ_percent::writebacks 0.824680 # Average percentage of cache occupancy
696system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087348 # Average percentage of cache occupancy
697system.cpu.l2cache.tags.occ_percent::cpu.data 0.083773 # Average percentage of cache occupancy
698system.cpu.l2cache.tags.occ_percent::total 0.995801 # Average percentage of cache occupancy
699system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
700system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
701system.cpu.l2cache.tags.age_task_id_blocks_1024::1 883 # Occupied blocks per task id
702system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5613 # Occupied blocks per task id
703system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2925 # Occupied blocks per task id
704system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55513 # Occupied blocks per task id
705system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
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707system.cpu.l2cache.tags.data_accesses 46397707 # Number of data accesses
708system.cpu.l2cache.WritebackDirty_hits::writebacks 838230 # number of WritebackDirty hits
709system.cpu.l2cache.WritebackDirty_hits::total 838230 # number of WritebackDirty hits
710system.cpu.l2cache.WritebackClean_hits::writebacks 1459876 # number of WritebackClean hits
711system.cpu.l2cache.WritebackClean_hits::total 1459876 # number of WritebackClean hits
712system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
713system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
714system.cpu.l2cache.ReadExReq_hits::cpu.data 187761 # number of ReadExReq hits
715system.cpu.l2cache.ReadExReq_hits::total 187761 # number of ReadExReq hits
716system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1444783 # number of ReadCleanReq hits
717system.cpu.l2cache.ReadCleanReq_hits::total 1444783 # number of ReadCleanReq hits
718system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819335 # number of ReadSharedReq hits
719system.cpu.l2cache.ReadSharedReq_hits::total 819335 # number of ReadSharedReq hits
720system.cpu.l2cache.demand_hits::cpu.inst 1444783 # number of demand (read+write) hits
721system.cpu.l2cache.demand_hits::cpu.data 1007096 # number of demand (read+write) hits
722system.cpu.l2cache.demand_hits::total 2451879 # number of demand (read+write) hits
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724system.cpu.l2cache.overall_hits::cpu.data 1007096 # number of overall hits
725system.cpu.l2cache.overall_hits::total 2451879 # number of overall hits
726system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses
727system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses
728system.cpu.l2cache.ReadExReq_misses::cpu.data 116656 # number of ReadExReq misses
729system.cpu.l2cache.ReadExReq_misses::total 116656 # number of ReadExReq misses
730system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16324 # number of ReadCleanReq misses
731system.cpu.l2cache.ReadCleanReq_misses::total 16324 # number of ReadCleanReq misses
732system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272208 # number of ReadSharedReq misses
733system.cpu.l2cache.ReadSharedReq_misses::total 272208 # number of ReadSharedReq misses
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737system.cpu.l2cache.overall_misses::cpu.inst 16324 # number of overall misses
738system.cpu.l2cache.overall_misses::cpu.data 388864 # number of overall misses
739system.cpu.l2cache.overall_misses::total 405188 # number of overall misses
740system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 397000 # number of UpgradeReq miss cycles
741system.cpu.l2cache.UpgradeReq_miss_latency::total 397000 # number of UpgradeReq miss cycles
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743system.cpu.l2cache.ReadExReq_miss_latency::total 14841518500 # number of ReadExReq miss cycles
744system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2141533000 # number of ReadCleanReq miss cycles
745system.cpu.l2cache.ReadCleanReq_miss_latency::total 2141533000 # number of ReadCleanReq miss cycles
746system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33675448500 # number of ReadSharedReq miss cycles
747system.cpu.l2cache.ReadSharedReq_miss_latency::total 33675448500 # number of ReadSharedReq miss cycles
748system.cpu.l2cache.demand_miss_latency::cpu.inst 2141533000 # number of demand (read+write) miss cycles
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751system.cpu.l2cache.overall_miss_latency::cpu.inst 2141533000 # number of overall miss cycles
752system.cpu.l2cache.overall_miss_latency::cpu.data 48516967000 # number of overall miss cycles
753system.cpu.l2cache.overall_miss_latency::total 50658500000 # number of overall miss cycles
754system.cpu.l2cache.WritebackDirty_accesses::writebacks 838230 # number of WritebackDirty accesses(hits+misses)
755system.cpu.l2cache.WritebackDirty_accesses::total 838230 # number of WritebackDirty accesses(hits+misses)
756system.cpu.l2cache.WritebackClean_accesses::writebacks 1459876 # number of WritebackClean accesses(hits+misses)
757system.cpu.l2cache.WritebackClean_accesses::total 1459876 # number of WritebackClean accesses(hits+misses)
758system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses)
759system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses)
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761system.cpu.l2cache.ReadExReq_accesses::total 304417 # number of ReadExReq accesses(hits+misses)
762system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1461107 # number of ReadCleanReq accesses(hits+misses)
763system.cpu.l2cache.ReadCleanReq_accesses::total 1461107 # number of ReadCleanReq accesses(hits+misses)
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765system.cpu.l2cache.ReadSharedReq_accesses::total 1091543 # number of ReadSharedReq accesses(hits+misses)
766system.cpu.l2cache.demand_accesses::cpu.inst 1461107 # number of demand (read+write) accesses
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771system.cpu.l2cache.overall_accesses::total 2857067 # number of overall (read+write) accesses
772system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.809524 # miss rate for UpgradeReq accesses
773system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses
774system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383211 # miss rate for ReadExReq accesses
775system.cpu.l2cache.ReadExReq_miss_rate::total 0.383211 # miss rate for ReadExReq accesses
776system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011172 # miss rate for ReadCleanReq accesses
777system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011172 # miss rate for ReadCleanReq accesses
778system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249379 # miss rate for ReadSharedReq accesses
779system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249379 # miss rate for ReadSharedReq accesses
780system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011172 # miss rate for demand accesses
781system.cpu.l2cache.demand_miss_rate::cpu.data 0.278564 # miss rate for demand accesses
782system.cpu.l2cache.demand_miss_rate::total 0.141820 # miss rate for demand accesses
783system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011172 # miss rate for overall accesses
784system.cpu.l2cache.overall_miss_rate::cpu.data 0.278564 # miss rate for overall accesses
785system.cpu.l2cache.overall_miss_rate::total 0.141820 # miss rate for overall accesses
786system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23352.941176 # average UpgradeReq miss latency
787system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23352.941176 # average UpgradeReq miss latency
788system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127224.647682 # average ReadExReq miss latency
789system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127224.647682 # average ReadExReq miss latency
790system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131189.230581 # average ReadCleanReq miss latency
791system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131189.230581 # average ReadCleanReq miss latency
792system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123712.192515 # average ReadSharedReq miss latency
793system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123712.192515 # average ReadSharedReq miss latency
794system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131189.230581 # average overall miss latency
795system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124765.900160 # average overall miss latency
796system.cpu.l2cache.demand_avg_miss_latency::total 125024.679902 # average overall miss latency
797system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131189.230581 # average overall miss latency
798system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124765.900160 # average overall miss latency
799system.cpu.l2cache.overall_avg_miss_latency::total 125024.679902 # average overall miss latency
800system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
801system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
802system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
803system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
804system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
805system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
806system.cpu.l2cache.fast_writes 0 # number of fast writes performed
807system.cpu.l2cache.cache_copies 0 # number of cache copies performed
808system.cpu.l2cache.writebacks::writebacks 76661 # number of writebacks
809system.cpu.l2cache.writebacks::total 76661 # number of writebacks
810system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses
811system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses
812system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116656 # number of ReadExReq MSHR misses
813system.cpu.l2cache.ReadExReq_mshr_misses::total 116656 # number of ReadExReq MSHR misses
814system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16324 # number of ReadCleanReq MSHR misses
815system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16324 # number of ReadCleanReq MSHR misses
816system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272208 # number of ReadSharedReq MSHR misses
817system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272208 # number of ReadSharedReq MSHR misses
818system.cpu.l2cache.demand_mshr_misses::cpu.inst 16324 # number of demand (read+write) MSHR misses
819system.cpu.l2cache.demand_mshr_misses::cpu.data 388864 # number of demand (read+write) MSHR misses
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822system.cpu.l2cache.overall_mshr_misses::cpu.data 388864 # number of overall MSHR misses
823system.cpu.l2cache.overall_mshr_misses::total 405188 # number of overall MSHR misses
824system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable
825system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable
826system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable
827system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable
828system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses
829system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses
830system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1175000 # number of UpgradeReq MSHR miss cycles
831system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1175000 # number of UpgradeReq MSHR miss cycles
832system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13674958500 # number of ReadExReq MSHR miss cycles
833system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13674958500 # number of ReadExReq MSHR miss cycles
834system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1978293000 # number of ReadCleanReq MSHR miss cycles
835system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1978293000 # number of ReadCleanReq MSHR miss cycles
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842system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44630533500 # number of overall MSHR miss cycles
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845system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442672500 # number of ReadReq MSHR uncacheable cycles
846system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051806000 # number of WriteReq MSHR uncacheable cycles
847system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051806000 # number of WriteReq MSHR uncacheable cycles
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849system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494478500 # number of overall MSHR uncacheable cycles
850system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses
851system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses
852system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383211 # mshr miss rate for ReadExReq accesses
853system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383211 # mshr miss rate for ReadExReq accesses
854system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for ReadCleanReq accesses
855system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011172 # mshr miss rate for ReadCleanReq accesses
856system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249379 # mshr miss rate for ReadSharedReq accesses
857system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249379 # mshr miss rate for ReadSharedReq accesses
858system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for demand accesses
859system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278564 # mshr miss rate for demand accesses
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861system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for overall accesses
862system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278564 # mshr miss rate for overall accesses
863system.cpu.l2cache.overall_mshr_miss_rate::total 0.141820 # mshr miss rate for overall accesses
864system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69117.647059 # average UpgradeReq mshr miss latency
865system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69117.647059 # average UpgradeReq mshr miss latency
866system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117224.647682 # average ReadExReq mshr miss latency
867system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117224.647682 # average ReadExReq mshr miss latency
868system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121189.230581 # average ReadCleanReq mshr miss latency
869system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121189.230581 # average ReadCleanReq mshr miss latency
870system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113720.298448 # average ReadSharedReq mshr miss latency
871system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113720.298448 # average ReadSharedReq mshr miss latency
872system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121189.230581 # average overall mshr miss latency
873system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114771.574381 # average overall mshr miss latency
874system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115030.125522 # average overall mshr miss latency
875system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121189.230581 # average overall mshr miss latency
876system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114771.574381 # average overall mshr miss latency
877system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115030.125522 # average overall mshr miss latency
878system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.758869 # average ReadReq mshr uncacheable latency
879system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.758869 # average ReadReq mshr uncacheable latency
880system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213196.799667 # average WriteReq mshr uncacheable latency
881system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213196.799667 # average WriteReq mshr uncacheable latency
882system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211044.721585 # average overall mshr uncacheable latency
883system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211044.721585 # average overall mshr uncacheable latency
884system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
885system.cpu.toL2Bus.snoop_filter.tot_requests 5713060 # Total number of requests made to the snoop filter.
886system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856101 # Number of requests hitting in the snoop filter with a single holder of the requested data.
887system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1990 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
888system.cpu.toL2Bus.snoop_filter.tot_snoops 1247 # Total number of snoops made to the snoop filter.
889system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1247 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
890system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
891system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution
892system.cpu.toL2Bus.trans_dist::ReadResp 2559783 # Transaction distribution
893system.cpu.toL2Bus.trans_dist::WriteReq 9624 # Transaction distribution
894system.cpu.toL2Bus.trans_dist::WriteResp 9624 # Transaction distribution
895system.cpu.toL2Bus.trans_dist::WritebackDirty 956411 # Transaction distribution
896system.cpu.toL2Bus.trans_dist::WritebackClean 1460482 # Transaction distribution
897system.cpu.toL2Bus.trans_dist::CleanEvict 820279 # Transaction distribution
898system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution
899system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution
900system.cpu.toL2Bus.trans_dist::ReadExReq 304417 # Transaction distribution
901system.cpu.toL2Bus.trans_dist::ReadExResp 304417 # Transaction distribution
902system.cpu.toL2Bus.trans_dist::ReadCleanReq 1461167 # Transaction distribution
903system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091716 # Transaction distribution
904system.cpu.toL2Bus.trans_dist::BadAddressError 17 # Transaction distribution
905system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
906system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4382756 # Packet count per connected master and slave (bytes)
907system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4220664 # Packet count per connected master and slave (bytes)
908system.cpu.toL2Bus.pkt_count::total 8603420 # Packet count per connected master and slave (bytes)
909system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186981696 # Cumulative packet size per connected master and slave (bytes)
910system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041437 # Cumulative packet size per connected master and slave (bytes)
911system.cpu.toL2Bus.pkt_size::total 330023133 # Cumulative packet size per connected master and slave (bytes)
912system.cpu.toL2Bus.snoops 423201 # Total snoops (count)
913system.cpu.toL2Bus.snoop_fanout::samples 3296691 # Request fanout histogram
914system.cpu.toL2Bus.snoop_fanout::mean 0.001034 # Request fanout histogram
915system.cpu.toL2Bus.snoop_fanout::stdev 0.032145 # Request fanout histogram
916system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
917system.cpu.toL2Bus.snoop_fanout::0 3293281 99.90% 99.90% # Request fanout histogram
918system.cpu.toL2Bus.snoop_fanout::1 3410 0.10% 100.00% # Request fanout histogram
919system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
920system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
921system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
922system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
923system.cpu.toL2Bus.snoop_fanout::total 3296691 # Request fanout histogram
924system.cpu.toL2Bus.reqLayer0.occupancy 5168333000 # Layer occupancy (ticks)
925system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
926system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks)
927system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
928system.cpu.toL2Bus.respLayer0.occupancy 2192017465 # Layer occupancy (ticks)
929system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
930system.cpu.toL2Bus.respLayer1.occupancy 2105681496 # Layer occupancy (ticks)
931system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
932system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
933system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
934system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
935system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
936system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
937system.disk0.dma_write_txs 395 # Number of DMA write transactions.
938system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).

--- 27 unchanged lines hidden (view full) ---

966system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
967system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
968system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes)
969system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
970system.iobus.pkt_size_system.bridge.master::total 44381 # Cumulative packet size per connected master and slave (bytes)
971system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
972system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
973system.iobus.pkt_size::total 2705989 # Cumulative packet size per connected master and slave (bytes)
974system.iobus.reqLayer0.occupancy 5419000 # Layer occupancy (ticks)
975system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
976system.iobus.reqLayer1.occupancy 786000 # Layer occupancy (ticks)
977system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
978system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks)
979system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
980system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks)
981system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
982system.iobus.reqLayer22.occupancy 186000 # Layer occupancy (ticks)
983system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
984system.iobus.reqLayer23.occupancy 14810500 # Layer occupancy (ticks)
985system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
986system.iobus.reqLayer24.occupancy 2308500 # Layer occupancy (ticks)
987system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
988system.iobus.reqLayer25.occupancy 5936500 # Layer occupancy (ticks)
989system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
990system.iobus.reqLayer26.occupancy 98500 # Layer occupancy (ticks)
991system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
992system.iobus.reqLayer27.occupancy 215720167 # Layer occupancy (ticks)
993system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
994system.iobus.respLayer0.occupancy 23492000 # Layer occupancy (ticks)
995system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
996system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
997system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
998system.iocache.tags.replacements 41685 # number of replacements
999system.iocache.tags.tagsinuse 1.290842 # Cycle average of tags in use
1000system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1001system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1002system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1003system.iocache.tags.warmup_cycle 1748612862000 # Cycle when the warmup percentage was hit.
1004system.iocache.tags.occ_blocks::tsunami.ide 1.290842 # Average occupied blocks per requestor
1005system.iocache.tags.occ_percent::tsunami.ide 0.080678 # Average percentage of cache occupancy
1006system.iocache.tags.occ_percent::total 0.080678 # Average percentage of cache occupancy
1007system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1008system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1009system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1010system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1011system.iocache.tags.data_accesses 375525 # Number of data accesses
1012system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1013system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1014system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1015system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1016system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
1017system.iocache.demand_misses::total 173 # number of demand (read+write) misses
1018system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
1019system.iocache.overall_misses::total 173 # number of overall misses
1020system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles
1021system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles
1022system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244742784 # number of WriteLineReq miss cycles
1023system.iocache.WriteLineReq_miss_latency::total 5244742784 # number of WriteLineReq miss cycles
1024system.iocache.demand_miss_latency::tsunami.ide 21917383 # number of demand (read+write) miss cycles
1025system.iocache.demand_miss_latency::total 21917383 # number of demand (read+write) miss cycles
1026system.iocache.overall_miss_latency::tsunami.ide 21917383 # number of overall miss cycles
1027system.iocache.overall_miss_latency::total 21917383 # number of overall miss cycles
1028system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
1029system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
1030system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1031system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1032system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
1033system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
1034system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
1035system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
1036system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1037system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1038system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1039system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1040system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1041system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1042system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1043system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1044system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency
1045system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency
1046system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126221.187524 # average WriteLineReq miss latency
1047system.iocache.WriteLineReq_avg_miss_latency::total 126221.187524 # average WriteLineReq miss latency
1048system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency
1049system.iocache.demand_avg_miss_latency::total 126690.075145 # average overall miss latency
1050system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency
1051system.iocache.overall_avg_miss_latency::total 126690.075145 # average overall miss latency
1052system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked
1053system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1054system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
1055system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1056system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked
1057system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1058system.iocache.fast_writes 0 # number of fast writes performed
1059system.iocache.cache_copies 0 # number of cache copies performed
1060system.iocache.writebacks::writebacks 41512 # number of writebacks
1061system.iocache.writebacks::total 41512 # number of writebacks
1062system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
1063system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
1064system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1065system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1066system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
1067system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
1068system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
1069system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
1070system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles
1071system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles
1072system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165341974 # number of WriteLineReq MSHR miss cycles
1073system.iocache.WriteLineReq_mshr_miss_latency::total 3165341974 # number of WriteLineReq MSHR miss cycles
1074system.iocache.demand_mshr_miss_latency::tsunami.ide 13267383 # number of demand (read+write) MSHR miss cycles
1075system.iocache.demand_mshr_miss_latency::total 13267383 # number of demand (read+write) MSHR miss cycles
1076system.iocache.overall_mshr_miss_latency::tsunami.ide 13267383 # number of overall MSHR miss cycles
1077system.iocache.overall_mshr_miss_latency::total 13267383 # number of overall MSHR miss cycles
1078system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1079system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1080system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1081system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1082system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1083system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1084system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1085system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1086system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency
1087system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency
1088system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.848816 # average WriteLineReq mshr miss latency
1089system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.848816 # average WriteLineReq mshr miss latency
1090system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency
1091system.iocache.demand_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency
1092system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency
1093system.iocache.overall_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency
1094system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1095system.membus.trans_dist::ReadReq 6934 # Transaction distribution
1096system.membus.trans_dist::ReadResp 295622 # Transaction distribution
1097system.membus.trans_dist::WriteReq 9624 # Transaction distribution
1098system.membus.trans_dist::WriteResp 9624 # Transaction distribution
1099system.membus.trans_dist::WritebackDirty 118173 # Transaction distribution
1100system.membus.trans_dist::CleanEvict 262241 # Transaction distribution
1101system.membus.trans_dist::UpgradeReq 175 # Transaction distribution
1102system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
1103system.membus.trans_dist::ReadExReq 116498 # Transaction distribution
1104system.membus.trans_dist::ReadExResp 116498 # Transaction distribution
1105system.membus.trans_dist::ReadSharedReq 288705 # Transaction distribution
1106system.membus.trans_dist::BadAddressError 17 # Transaction distribution
1107system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
1108system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33116 # Packet count per connected master and slave (bytes)
1109system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148657 # Packet count per connected master and slave (bytes)
1110system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 34 # Packet count per connected master and slave (bytes)
1111system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181807 # Packet count per connected master and slave (bytes)
1112system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes)
1113system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes)
1114system.membus.pkt_count::total 1265232 # Packet count per connected master and slave (bytes)
1115system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44381 # Cumulative packet size per connected master and slave (bytes)
1116system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30809664 # Cumulative packet size per connected master and slave (bytes)
1117system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30854045 # Cumulative packet size per connected master and slave (bytes)
1118system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
1119system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
1120system.membus.pkt_size::total 33511773 # Cumulative packet size per connected master and slave (bytes)
1121system.membus.snoops 433 # Total snoops (count)
1122system.membus.snoop_fanout::samples 843910 # Request fanout histogram
1123system.membus.snoop_fanout::mean 1 # Request fanout histogram
1124system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1125system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1126system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1127system.membus.snoop_fanout::1 843910 100.00% 100.00% # Request fanout histogram
1128system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1129system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1130system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1131system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1132system.membus.snoop_fanout::total 843910 # Request fanout histogram
1133system.membus.reqLayer0.occupancy 29565500 # Layer occupancy (ticks)
1134system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1135system.membus.reqLayer1.occupancy 1319337462 # Layer occupancy (ticks)
1136system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1137system.membus.reqLayer2.occupancy 22000 # Layer occupancy (ticks)
1138system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1139system.membus.respLayer1.occupancy 2159897250 # Layer occupancy (ticks)
1140system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1141system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks)
1142system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1143system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1144system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1145system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1146system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1147system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1148system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1149system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR

--- 26 unchanged lines hidden ---