| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20eventq_index=0 21exit_on_work_items=false 22init_param=0 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20eventq_index=0 21exit_on_work_items=false 22init_param=0 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing |
| 28mem_ranges=0:134217727 | 28mem_ranges=0:134217727:0:0:0:0 |
| 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal --- 18 unchanged lines hidden (view full) --- 55clk_domain=system.clk_domain 56default_p_state=UNDEFINED 57delay=50000 58eventq_index=0 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null | 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal --- 18 unchanged lines hidden (view full) --- 55clk_domain=system.clk_domain 56default_p_state=UNDEFINED 57delay=50000 58eventq_index=0 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null |
| 63ranges=8796093022208:18446744073709551615 | 63ranges=8796093022208:18446744073709551615:0:0:0:0 |
| 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain 71clock=1000 --- 93 unchanged lines hidden (view full) --- 165localHistoryTableSize=2048 166localPredictorSize=2048 167numThreads=1 168useIndirect=true 169 170[system.cpu.dcache] 171type=Cache 172children=tags | 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain 71clock=1000 --- 93 unchanged lines hidden (view full) --- 165localHistoryTableSize=2048 166localPredictorSize=2048 167numThreads=1 168useIndirect=true 169 170[system.cpu.dcache] 171type=Cache 172children=tags |
| 173addr_ranges=0:18446744073709551615 | 173addr_ranges=0:18446744073709551615:0:0:0:0 |
| 174assoc=4 175clk_domain=system.cpu_clk_domain 176clusivity=mostly_incl 177default_p_state=UNDEFINED 178demand_mshr_reserve=1 179eventq_index=0 180hit_latency=2 181is_read_only=false --- 417 unchanged lines hidden (view full) --- 599[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] 600type=MinorOpClass 601eventq_index=0 602opClass=InstPrefetch 603 604[system.cpu.icache] 605type=Cache 606children=tags | 174assoc=4 175clk_domain=system.cpu_clk_domain 176clusivity=mostly_incl 177default_p_state=UNDEFINED 178demand_mshr_reserve=1 179eventq_index=0 180hit_latency=2 181is_read_only=false --- 417 unchanged lines hidden (view full) --- 599[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] 600type=MinorOpClass 601eventq_index=0 602opClass=InstPrefetch 603 604[system.cpu.icache] 605type=Cache 606children=tags |
| 607addr_ranges=0:18446744073709551615 | 607addr_ranges=0:18446744073709551615:0:0:0:0 |
| 608assoc=1 609clk_domain=system.cpu_clk_domain 610clusivity=mostly_incl 611default_p_state=UNDEFINED 612demand_mshr_reserve=1 613eventq_index=0 614hit_latency=2 615is_read_only=true --- 43 unchanged lines hidden (view full) --- 659[system.cpu.itb] 660type=AlphaTLB 661eventq_index=0 662size=48 663 664[system.cpu.l2cache] 665type=Cache 666children=tags | 608assoc=1 609clk_domain=system.cpu_clk_domain 610clusivity=mostly_incl 611default_p_state=UNDEFINED 612demand_mshr_reserve=1 613eventq_index=0 614hit_latency=2 615is_read_only=true --- 43 unchanged lines hidden (view full) --- 659[system.cpu.itb] 660type=AlphaTLB 661eventq_index=0 662size=48 663 664[system.cpu.l2cache] 665type=Cache 666children=tags |
| 667addr_ranges=0:18446744073709551615 | 667addr_ranges=0:18446744073709551615:0:0:0:0 |
| 668assoc=8 669clk_domain=system.cpu_clk_domain 670clusivity=mostly_incl 671default_p_state=UNDEFINED 672demand_mshr_reserve=1 673eventq_index=0 674hit_latency=20 675is_read_only=false --- 146 unchanged lines hidden (view full) --- 822use_default_range=false 823width=16 824master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 825slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 826 827[system.iocache] 828type=Cache 829children=tags | 668assoc=8 669clk_domain=system.cpu_clk_domain 670clusivity=mostly_incl 671default_p_state=UNDEFINED 672demand_mshr_reserve=1 673eventq_index=0 674hit_latency=20 675is_read_only=false --- 146 unchanged lines hidden (view full) --- 822use_default_range=false 823width=16 824master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 825slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 826 827[system.iocache] 828type=Cache 829children=tags |
| 830addr_ranges=0:134217727 | 830addr_ranges=0:134217727:0:0:0:0 |
| 831assoc=8 832clk_domain=system.clk_domain 833clusivity=mostly_incl 834default_p_state=UNDEFINED 835demand_mshr_reserve=1 836eventq_index=0 837hit_latency=50 838is_read_only=false --- 28 unchanged lines hidden (view full) --- 867p_state_clk_gate_max=1000000000000 868p_state_clk_gate_min=1000 869power_model=Null 870sequential_access=false 871size=1024 872 873[system.membus] 874type=CoherentXBar | 831assoc=8 832clk_domain=system.clk_domain 833clusivity=mostly_incl 834default_p_state=UNDEFINED 835demand_mshr_reserve=1 836eventq_index=0 837hit_latency=50 838is_read_only=false --- 28 unchanged lines hidden (view full) --- 867p_state_clk_gate_max=1000000000000 868p_state_clk_gate_min=1000 869power_model=Null 870sequential_access=false 871size=1024 872 873[system.membus] 874type=CoherentXBar |
| 875children=badaddr_responder | 875children=badaddr_responder snoop_filter |
| 876clk_domain=system.clk_domain 877default_p_state=UNDEFINED 878eventq_index=0 879forward_latency=4 880frontend_latency=3 881p_state_clk_gate_bins=20 882p_state_clk_gate_max=1000000000000 883p_state_clk_gate_min=1000 884point_of_coherency=true 885power_model=Null 886response_latency=2 | 876clk_domain=system.clk_domain 877default_p_state=UNDEFINED 878eventq_index=0 879forward_latency=4 880frontend_latency=3 881p_state_clk_gate_bins=20 882p_state_clk_gate_max=1000000000000 883p_state_clk_gate_min=1000 884point_of_coherency=true 885power_model=Null 886response_latency=2 |
| 887snoop_filter=Null | 887snoop_filter=system.membus.snoop_filter |
| 888snoop_response_latency=4 889system=system 890use_default_range=false 891width=16 892default=system.membus.badaddr_responder.pio 893master=system.bridge.slave system.physmem.port 894slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 895 --- 15 unchanged lines hidden (view full) --- 911ret_data32=4294967295 912ret_data64=18446744073709551615 913ret_data8=255 914system=system 915update_data=false 916warn_access= 917pio=system.membus.default 918 | 888snoop_response_latency=4 889system=system 890use_default_range=false 891width=16 892default=system.membus.badaddr_responder.pio 893master=system.bridge.slave system.physmem.port 894slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 895 --- 15 unchanged lines hidden (view full) --- 911ret_data32=4294967295 912ret_data64=18446744073709551615 913ret_data8=255 914system=system 915update_data=false 916warn_access= 917pio=system.membus.default 918 |
| 919[system.membus.snoop_filter] 920type=SnoopFilter 921eventq_index=0 922lookup_latency=1 923max_capacity=8388608 924system=system 925 |
|
| 919[system.physmem] 920type=DRAMCtrl | 926[system.physmem] 927type=DRAMCtrl |
| 921IDD0=0.075000 | 928IDD0=0.055000 |
| 922IDD02=0.000000 | 929IDD02=0.000000 |
| 923IDD2N=0.050000 | 930IDD2N=0.032000 |
| 924IDD2N2=0.000000 925IDD2P0=0.000000 926IDD2P02=0.000000 | 931IDD2N2=0.000000 932IDD2P0=0.000000 933IDD2P02=0.000000 |
| 927IDD2P1=0.000000 | 934IDD2P1=0.032000 |
| 928IDD2P12=0.000000 | 935IDD2P12=0.000000 |
| 929IDD3N=0.057000 | 936IDD3N=0.038000 |
| 930IDD3N2=0.000000 931IDD3P0=0.000000 932IDD3P02=0.000000 | 937IDD3N2=0.000000 938IDD3P0=0.000000 939IDD3P02=0.000000 |
| 933IDD3P1=0.000000 | 940IDD3P1=0.038000 |
| 934IDD3P12=0.000000 | 941IDD3P12=0.000000 |
| 935IDD4R=0.187000 | 942IDD4R=0.157000 |
| 936IDD4R2=0.000000 | 943IDD4R2=0.000000 |
| 937IDD4W=0.165000 | 944IDD4W=0.125000 |
| 938IDD4W2=0.000000 | 945IDD4W2=0.000000 |
| 939IDD5=0.220000 | 946IDD5=0.235000 |
| 940IDD52=0.000000 | 947IDD52=0.000000 |
| 941IDD6=0.000000 | 948IDD6=0.020000 |
| 942IDD62=0.000000 943VDD=1.500000 944VDD2=0.000000 945activation_limit=4 946addr_mapping=RoRaBaCoCh 947bank_groups_per_rank=0 948banks_per_rank=8 949burst_length=8 950channels=1 951clk_domain=system.clk_domain 952conf_table_reported=true 953default_p_state=UNDEFINED 954device_bus_width=8 955device_rowbuffer_size=1024 956device_size=536870912 957devices_per_rank=8 958dll=true 959eventq_index=0 960in_addr_map=true | 949IDD62=0.000000 950VDD=1.500000 951VDD2=0.000000 952activation_limit=4 953addr_mapping=RoRaBaCoCh 954bank_groups_per_rank=0 955banks_per_rank=8 956burst_length=8 957channels=1 958clk_domain=system.clk_domain 959conf_table_reported=true 960default_p_state=UNDEFINED 961device_bus_width=8 962device_rowbuffer_size=1024 963device_size=536870912 964devices_per_rank=8 965dll=true 966eventq_index=0 967in_addr_map=true |
| 968kvm_map=true |
|
| 961max_accesses_per_row=16 962mem_sched_policy=frfcfs 963min_writes_per_switch=16 964null=false 965p_state_clk_gate_bins=20 966p_state_clk_gate_max=1000000000000 967p_state_clk_gate_min=1000 968page_policy=open_adaptive 969power_model=Null | 969max_accesses_per_row=16 970mem_sched_policy=frfcfs 971min_writes_per_switch=16 972null=false 973p_state_clk_gate_bins=20 974p_state_clk_gate_max=1000000000000 975p_state_clk_gate_min=1000 976page_policy=open_adaptive 977power_model=Null |
| 970range=0:134217727 | 978range=0:134217727:0:0:0:0 |
| 971ranks_per_channel=2 972read_buffer_size=32 973static_backend_latency=10000 974static_frontend_latency=10000 975tBURST=5000 976tCCD_L=0 977tCK=1250 978tCL=13750 --- 5 unchanged lines hidden (view full) --- 984tRP=13750 985tRRD=6000 986tRRD_L=0 987tRTP=7500 988tRTW=2500 989tWR=15000 990tWTR=7500 991tXAW=30000 | 979ranks_per_channel=2 980read_buffer_size=32 981static_backend_latency=10000 982static_frontend_latency=10000 983tBURST=5000 984tCCD_L=0 985tCK=1250 986tCL=13750 --- 5 unchanged lines hidden (view full) --- 992tRP=13750 993tRRD=6000 994tRRD_L=0 995tRTP=7500 996tRTW=2500 997tWR=15000 998tWTR=7500 999tXAW=30000 |
| 992tXP=0 | 1000tXP=6000 |
| 993tXPDLL=0 | 1001tXPDLL=0 |
| 994tXS=0 | 1002tXS=270000 |
| 995tXSDLL=0 996write_buffer_size=64 997write_high_thresh_perc=85 998write_low_thresh_perc=50 999port=system.membus.master[1] 1000 1001[system.simple_disk] 1002type=SimpleDisk --- 774 unchanged lines hidden --- | 1003tXSDLL=0 1004write_buffer_size=64 1005write_high_thresh_perc=85 1006write_low_thresh_perc=50 1007port=system.membus.master[1] 1008 1009[system.simple_disk] 1010type=SimpleDisk --- 774 unchanged lines hidden --- |