| config.ini (11245:1c5102c0a7a9) | config.ini (11570:4aac82f10951) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain |
| 18console=/work/gem5/dist/binaries/console | 18console=/arm/projectscratch/randd/systems/dist/binaries/console 19default_p_state=UNDEFINED |
| 19eventq_index=0 | 20eventq_index=0 |
| 21exit_on_work_items=false |
|
| 20init_param=0 | 22init_param=0 |
| 21kernel=/work/gem5/dist/binaries/vmlinux | 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux |
| 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 | 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing 28mem_ranges=0:134217727 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 |
| 31pal=/work/gem5/dist/binaries/ts_osfpal 32readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh | 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal 37power_model=Null 38readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh |
| 33symbolfile= 34system_rev=1024 35system_type=34 | 39symbolfile= 40system_rev=1024 41system_type=34 |
| 42thermal_components= 43thermal_model=Null |
|
| 36work_begin_ckpt_count=0 37work_begin_cpu_id_exit=-1 38work_begin_exit_count=0 39work_cpus_ckpt_count=0 40work_end_ckpt_count=0 41work_end_exit_count=0 42work_item_id=-1 43system_port=system.membus.slave[0] 44 45[system.bridge] 46type=Bridge 47clk_domain=system.clk_domain | 44work_begin_ckpt_count=0 45work_begin_cpu_id_exit=-1 46work_begin_exit_count=0 47work_cpus_ckpt_count=0 48work_end_ckpt_count=0 49work_end_exit_count=0 50work_item_id=-1 51system_port=system.membus.slave[0] 52 53[system.bridge] 54type=Bridge 55clk_domain=system.clk_domain |
| 56default_p_state=UNDEFINED |
|
| 48delay=50000 49eventq_index=0 | 57delay=50000 58eventq_index=0 |
| 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null |
|
| 50ranges=8796093022208:18446744073709551615 51req_size=16 52resp_size=16 53master=system.iobus.slave[0] 54slave=system.membus.master[0] 55 56[system.clk_domain] 57type=SrcClockDomain --- 9 unchanged lines hidden (view full) --- 67branchPred=system.cpu.branchPred 68checker=Null 69clk_domain=system.cpu_clk_domain 70cpu_id=0 71decodeCycleInput=true 72decodeInputBufferSize=3 73decodeInputWidth=2 74decodeToExecuteForwardDelay=1 | 63ranges=8796093022208:18446744073709551615 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain --- 9 unchanged lines hidden (view full) --- 80branchPred=system.cpu.branchPred 81checker=Null 82clk_domain=system.cpu_clk_domain 83cpu_id=0 84decodeCycleInput=true 85decodeInputBufferSize=3 86decodeInputWidth=2 87decodeToExecuteForwardDelay=1 |
| 88default_p_state=UNDEFINED |
|
| 75do_checkpoint_insts=true 76do_quiesce=true 77do_statistics_insts=true 78dtb=system.cpu.dtb 79enableIdling=true 80eventq_index=0 81executeAllowEarlyMemoryIssue=true 82executeBranchDelay=1 --- 26 unchanged lines hidden (view full) --- 109interrupts=system.cpu.interrupts 110isa=system.cpu.isa 111itb=system.cpu.itb 112max_insts_all_threads=0 113max_insts_any_thread=0 114max_loads_all_threads=0 115max_loads_any_thread=0 116numThreads=1 | 89do_checkpoint_insts=true 90do_quiesce=true 91do_statistics_insts=true 92dtb=system.cpu.dtb 93enableIdling=true 94eventq_index=0 95executeAllowEarlyMemoryIssue=true 96executeBranchDelay=1 --- 26 unchanged lines hidden (view full) --- 123interrupts=system.cpu.interrupts 124isa=system.cpu.isa 125itb=system.cpu.itb 126max_insts_all_threads=0 127max_insts_any_thread=0 128max_loads_all_threads=0 129max_loads_any_thread=0 130numThreads=1 |
| 131p_state_clk_gate_bins=20 132p_state_clk_gate_max=1000000000000 133p_state_clk_gate_min=1000 134power_model=Null |
|
| 117profile=0 118progress_interval=0 119simpoint_start_insts= 120socket_id=0 121switched_out=false 122system=system | 135profile=0 136progress_interval=0 137simpoint_start_insts= 138socket_id=0 139switched_out=false 140system=system |
| 141threadPolicy=RoundRobin |
|
| 123tracer=system.cpu.tracer 124workload= 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.branchPred] 129type=TournamentBP 130BTBEntries=4096 131BTBTagSize=16 132RASSize=16 133choiceCtrBits=2 134choicePredictorSize=8192 135eventq_index=0 136globalCtrBits=2 137globalPredictorSize=8192 | 142tracer=system.cpu.tracer 143workload= 144dcache_port=system.cpu.dcache.cpu_side 145icache_port=system.cpu.icache.cpu_side 146 147[system.cpu.branchPred] 148type=TournamentBP 149BTBEntries=4096 150BTBTagSize=16 151RASSize=16 152choiceCtrBits=2 153choicePredictorSize=8192 154eventq_index=0 155globalCtrBits=2 156globalPredictorSize=8192 |
| 157indirectHashGHR=true 158indirectHashTargets=true 159indirectPathLength=3 160indirectSets=256 161indirectTagSize=16 162indirectWays=2 |
|
| 138instShiftAmt=2 139localCtrBits=2 140localHistoryTableSize=2048 141localPredictorSize=2048 142numThreads=1 | 163instShiftAmt=2 164localCtrBits=2 165localHistoryTableSize=2048 166localPredictorSize=2048 167numThreads=1 |
| 168useIndirect=true |
|
| 143 144[system.cpu.dcache] 145type=Cache 146children=tags 147addr_ranges=0:18446744073709551615 148assoc=4 149clk_domain=system.cpu_clk_domain 150clusivity=mostly_incl | 169 170[system.cpu.dcache] 171type=Cache 172children=tags 173addr_ranges=0:18446744073709551615 174assoc=4 175clk_domain=system.cpu_clk_domain 176clusivity=mostly_incl |
| 177default_p_state=UNDEFINED |
|
| 151demand_mshr_reserve=1 152eventq_index=0 | 178demand_mshr_reserve=1 179eventq_index=0 |
| 153forward_snoops=true | |
| 154hit_latency=2 155is_read_only=false 156max_miss_count=0 157mshrs=4 | 180hit_latency=2 181is_read_only=false 182max_miss_count=0 183mshrs=4 |
| 184p_state_clk_gate_bins=20 185p_state_clk_gate_max=1000000000000 186p_state_clk_gate_min=1000 187power_model=Null |
|
| 158prefetch_on_access=false 159prefetcher=Null 160response_latency=2 161sequential_access=false 162size=32768 163system=system 164tags=system.cpu.dcache.tags 165tgts_per_mshr=20 166write_buffers=8 167writeback_clean=false 168cpu_side=system.cpu.dcache_port 169mem_side=system.cpu.toL2Bus.slave[1] 170 171[system.cpu.dcache.tags] 172type=LRU 173assoc=4 174block_size=64 175clk_domain=system.cpu_clk_domain | 188prefetch_on_access=false 189prefetcher=Null 190response_latency=2 191sequential_access=false 192size=32768 193system=system 194tags=system.cpu.dcache.tags 195tgts_per_mshr=20 196write_buffers=8 197writeback_clean=false 198cpu_side=system.cpu.dcache_port 199mem_side=system.cpu.toL2Bus.slave[1] 200 201[system.cpu.dcache.tags] 202type=LRU 203assoc=4 204block_size=64 205clk_domain=system.cpu_clk_domain |
| 206default_p_state=UNDEFINED |
|
| 176eventq_index=0 177hit_latency=2 | 207eventq_index=0 208hit_latency=2 |
| 209p_state_clk_gate_bins=20 210p_state_clk_gate_max=1000000000000 211p_state_clk_gate_min=1000 212power_model=Null |
|
| 178sequential_access=false 179size=32768 180 181[system.cpu.dtb] 182type=AlphaTLB 183eventq_index=0 184size=64 185 --- 382 unchanged lines hidden (view full) --- 568 569[system.cpu.icache] 570type=Cache 571children=tags 572addr_ranges=0:18446744073709551615 573assoc=1 574clk_domain=system.cpu_clk_domain 575clusivity=mostly_incl | 213sequential_access=false 214size=32768 215 216[system.cpu.dtb] 217type=AlphaTLB 218eventq_index=0 219size=64 220 --- 382 unchanged lines hidden (view full) --- 603 604[system.cpu.icache] 605type=Cache 606children=tags 607addr_ranges=0:18446744073709551615 608assoc=1 609clk_domain=system.cpu_clk_domain 610clusivity=mostly_incl |
| 611default_p_state=UNDEFINED |
|
| 576demand_mshr_reserve=1 577eventq_index=0 | 612demand_mshr_reserve=1 613eventq_index=0 |
| 578forward_snoops=true | |
| 579hit_latency=2 580is_read_only=true 581max_miss_count=0 582mshrs=4 | 614hit_latency=2 615is_read_only=true 616max_miss_count=0 617mshrs=4 |
| 618p_state_clk_gate_bins=20 619p_state_clk_gate_max=1000000000000 620p_state_clk_gate_min=1000 621power_model=Null |
|
| 583prefetch_on_access=false 584prefetcher=Null 585response_latency=2 586sequential_access=false 587size=32768 588system=system 589tags=system.cpu.icache.tags 590tgts_per_mshr=20 591write_buffers=8 592writeback_clean=true 593cpu_side=system.cpu.icache_port 594mem_side=system.cpu.toL2Bus.slave[0] 595 596[system.cpu.icache.tags] 597type=LRU 598assoc=1 599block_size=64 600clk_domain=system.cpu_clk_domain | 622prefetch_on_access=false 623prefetcher=Null 624response_latency=2 625sequential_access=false 626size=32768 627system=system 628tags=system.cpu.icache.tags 629tgts_per_mshr=20 630write_buffers=8 631writeback_clean=true 632cpu_side=system.cpu.icache_port 633mem_side=system.cpu.toL2Bus.slave[0] 634 635[system.cpu.icache.tags] 636type=LRU 637assoc=1 638block_size=64 639clk_domain=system.cpu_clk_domain |
| 640default_p_state=UNDEFINED |
|
| 601eventq_index=0 602hit_latency=2 | 641eventq_index=0 642hit_latency=2 |
| 643p_state_clk_gate_bins=20 644p_state_clk_gate_max=1000000000000 645p_state_clk_gate_min=1000 646power_model=Null |
|
| 603sequential_access=false 604size=32768 605 606[system.cpu.interrupts] 607type=AlphaInterrupts 608eventq_index=0 609 610[system.cpu.isa] --- 8 unchanged lines hidden (view full) --- 619 620[system.cpu.l2cache] 621type=Cache 622children=tags 623addr_ranges=0:18446744073709551615 624assoc=8 625clk_domain=system.cpu_clk_domain 626clusivity=mostly_incl | 647sequential_access=false 648size=32768 649 650[system.cpu.interrupts] 651type=AlphaInterrupts 652eventq_index=0 653 654[system.cpu.isa] --- 8 unchanged lines hidden (view full) --- 663 664[system.cpu.l2cache] 665type=Cache 666children=tags 667addr_ranges=0:18446744073709551615 668assoc=8 669clk_domain=system.cpu_clk_domain 670clusivity=mostly_incl |
| 671default_p_state=UNDEFINED |
|
| 627demand_mshr_reserve=1 628eventq_index=0 | 672demand_mshr_reserve=1 673eventq_index=0 |
| 629forward_snoops=true | |
| 630hit_latency=20 631is_read_only=false 632max_miss_count=0 633mshrs=20 | 674hit_latency=20 675is_read_only=false 676max_miss_count=0 677mshrs=20 |
| 678p_state_clk_gate_bins=20 679p_state_clk_gate_max=1000000000000 680p_state_clk_gate_min=1000 681power_model=Null |
|
| 634prefetch_on_access=false 635prefetcher=Null 636response_latency=20 637sequential_access=false 638size=4194304 639system=system 640tags=system.cpu.l2cache.tags 641tgts_per_mshr=12 642write_buffers=8 643writeback_clean=false 644cpu_side=system.cpu.toL2Bus.master[0] 645mem_side=system.membus.slave[1] 646 647[system.cpu.l2cache.tags] 648type=LRU 649assoc=8 650block_size=64 651clk_domain=system.cpu_clk_domain | 682prefetch_on_access=false 683prefetcher=Null 684response_latency=20 685sequential_access=false 686size=4194304 687system=system 688tags=system.cpu.l2cache.tags 689tgts_per_mshr=12 690write_buffers=8 691writeback_clean=false 692cpu_side=system.cpu.toL2Bus.master[0] 693mem_side=system.membus.slave[1] 694 695[system.cpu.l2cache.tags] 696type=LRU 697assoc=8 698block_size=64 699clk_domain=system.cpu_clk_domain |
| 700default_p_state=UNDEFINED |
|
| 652eventq_index=0 653hit_latency=20 | 701eventq_index=0 702hit_latency=20 |
| 703p_state_clk_gate_bins=20 704p_state_clk_gate_max=1000000000000 705p_state_clk_gate_min=1000 706power_model=Null |
|
| 654sequential_access=false 655size=4194304 656 657[system.cpu.toL2Bus] 658type=CoherentXBar 659children=snoop_filter 660clk_domain=system.cpu_clk_domain | 707sequential_access=false 708size=4194304 709 710[system.cpu.toL2Bus] 711type=CoherentXBar 712children=snoop_filter 713clk_domain=system.cpu_clk_domain |
| 714default_p_state=UNDEFINED |
|
| 661eventq_index=0 662forward_latency=0 663frontend_latency=1 | 715eventq_index=0 716forward_latency=0 717frontend_latency=1 |
| 718p_state_clk_gate_bins=20 719p_state_clk_gate_max=1000000000000 720p_state_clk_gate_min=1000 721point_of_coherency=false 722power_model=Null |
|
| 664response_latency=1 665snoop_filter=system.cpu.toL2Bus.snoop_filter 666snoop_response_latency=1 667system=system 668use_default_range=false 669width=32 670master=system.cpu.l2cache.cpu_side 671slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 32 unchanged lines hidden (view full) --- 704eventq_index=0 705image_file= 706read_only=false 707table_size=65536 708 709[system.disk0.image.child] 710type=RawDiskImage 711eventq_index=0 | 723response_latency=1 724snoop_filter=system.cpu.toL2Bus.snoop_filter 725snoop_response_latency=1 726system=system 727use_default_range=false 728width=32 729master=system.cpu.l2cache.cpu_side 730slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 32 unchanged lines hidden (view full) --- 763eventq_index=0 764image_file= 765read_only=false 766table_size=65536 767 768[system.disk0.image.child] 769type=RawDiskImage 770eventq_index=0 |
| 712image_file=/work/gem5/dist/disks/linux-latest.img | 771image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img |
| 713read_only=true 714 715[system.disk2] 716type=IdeDisk 717children=image 718delay=1000000 719driveID=master 720eventq_index=0 --- 6 unchanged lines hidden (view full) --- 727eventq_index=0 728image_file= 729read_only=false 730table_size=65536 731 732[system.disk2.image.child] 733type=RawDiskImage 734eventq_index=0 | 772read_only=true 773 774[system.disk2] 775type=IdeDisk 776children=image 777delay=1000000 778driveID=master 779eventq_index=0 --- 6 unchanged lines hidden (view full) --- 786eventq_index=0 787image_file= 788read_only=false 789table_size=65536 790 791[system.disk2.image.child] 792type=RawDiskImage 793eventq_index=0 |
| 735image_file=/work/gem5/dist/disks/linux-bigswap2.img | 794image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img |
| 736read_only=true 737 738[system.dvfs_handler] 739type=DVFSHandler 740domains= 741enable=false 742eventq_index=0 743sys_clk_domain=system.clk_domain 744transition_latency=100000000 745 746[system.intrctrl] 747type=IntrControl 748eventq_index=0 749sys=system 750 751[system.iobus] 752type=NoncoherentXBar 753clk_domain=system.clk_domain | 795read_only=true 796 797[system.dvfs_handler] 798type=DVFSHandler 799domains= 800enable=false 801eventq_index=0 802sys_clk_domain=system.clk_domain 803transition_latency=100000000 804 805[system.intrctrl] 806type=IntrControl 807eventq_index=0 808sys=system 809 810[system.iobus] 811type=NoncoherentXBar 812clk_domain=system.clk_domain |
| 813default_p_state=UNDEFINED |
|
| 754eventq_index=0 755forward_latency=1 756frontend_latency=2 | 814eventq_index=0 815forward_latency=1 816frontend_latency=2 |
| 817p_state_clk_gate_bins=20 818p_state_clk_gate_max=1000000000000 819p_state_clk_gate_min=1000 820power_model=Null |
|
| 757response_latency=2 758use_default_range=false 759width=16 760master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 761slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 762 763[system.iocache] 764type=Cache 765children=tags 766addr_ranges=0:134217727 767assoc=8 768clk_domain=system.clk_domain 769clusivity=mostly_incl | 821response_latency=2 822use_default_range=false 823width=16 824master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 825slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 826 827[system.iocache] 828type=Cache 829children=tags 830addr_ranges=0:134217727 831assoc=8 832clk_domain=system.clk_domain 833clusivity=mostly_incl |
| 834default_p_state=UNDEFINED |
|
| 770demand_mshr_reserve=1 771eventq_index=0 | 835demand_mshr_reserve=1 836eventq_index=0 |
| 772forward_snoops=false | |
| 773hit_latency=50 774is_read_only=false 775max_miss_count=0 776mshrs=20 | 837hit_latency=50 838is_read_only=false 839max_miss_count=0 840mshrs=20 |
| 841p_state_clk_gate_bins=20 842p_state_clk_gate_max=1000000000000 843p_state_clk_gate_min=1000 844power_model=Null |
|
| 777prefetch_on_access=false 778prefetcher=Null 779response_latency=50 780sequential_access=false 781size=1024 782system=system 783tags=system.iocache.tags 784tgts_per_mshr=12 785write_buffers=8 786writeback_clean=false 787cpu_side=system.iobus.master[27] 788mem_side=system.membus.slave[2] 789 790[system.iocache.tags] 791type=LRU 792assoc=8 793block_size=64 794clk_domain=system.clk_domain | 845prefetch_on_access=false 846prefetcher=Null 847response_latency=50 848sequential_access=false 849size=1024 850system=system 851tags=system.iocache.tags 852tgts_per_mshr=12 853write_buffers=8 854writeback_clean=false 855cpu_side=system.iobus.master[27] 856mem_side=system.membus.slave[2] 857 858[system.iocache.tags] 859type=LRU 860assoc=8 861block_size=64 862clk_domain=system.clk_domain |
| 863default_p_state=UNDEFINED |
|
| 795eventq_index=0 796hit_latency=50 | 864eventq_index=0 865hit_latency=50 |
| 866p_state_clk_gate_bins=20 867p_state_clk_gate_max=1000000000000 868p_state_clk_gate_min=1000 869power_model=Null |
|
| 797sequential_access=false 798size=1024 799 800[system.membus] 801type=CoherentXBar 802children=badaddr_responder 803clk_domain=system.clk_domain | 870sequential_access=false 871size=1024 872 873[system.membus] 874type=CoherentXBar 875children=badaddr_responder 876clk_domain=system.clk_domain |
| 877default_p_state=UNDEFINED |
|
| 804eventq_index=0 805forward_latency=4 806frontend_latency=3 | 878eventq_index=0 879forward_latency=4 880frontend_latency=3 |
| 881p_state_clk_gate_bins=20 882p_state_clk_gate_max=1000000000000 883p_state_clk_gate_min=1000 884point_of_coherency=true 885power_model=Null |
|
| 807response_latency=2 808snoop_filter=Null 809snoop_response_latency=4 810system=system 811use_default_range=false 812width=16 813default=system.membus.badaddr_responder.pio 814master=system.bridge.slave system.physmem.port 815slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 816 817[system.membus.badaddr_responder] 818type=IsaFake 819clk_domain=system.clk_domain | 886response_latency=2 887snoop_filter=Null 888snoop_response_latency=4 889system=system 890use_default_range=false 891width=16 892default=system.membus.badaddr_responder.pio 893master=system.bridge.slave system.physmem.port 894slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 895 896[system.membus.badaddr_responder] 897type=IsaFake 898clk_domain=system.clk_domain |
| 899default_p_state=UNDEFINED |
|
| 820eventq_index=0 821fake_mem=false | 900eventq_index=0 901fake_mem=false |
| 902p_state_clk_gate_bins=20 903p_state_clk_gate_max=1000000000000 904p_state_clk_gate_min=1000 |
|
| 822pio_addr=0 823pio_latency=100000 824pio_size=8 | 905pio_addr=0 906pio_latency=100000 907pio_size=8 |
| 908power_model=Null |
|
| 825ret_bad_addr=true 826ret_data16=65535 827ret_data32=4294967295 828ret_data64=18446744073709551615 829ret_data8=255 830system=system 831update_data=false 832warn_access= --- 28 unchanged lines hidden (view full) --- 861activation_limit=4 862addr_mapping=RoRaBaCoCh 863bank_groups_per_rank=0 864banks_per_rank=8 865burst_length=8 866channels=1 867clk_domain=system.clk_domain 868conf_table_reported=true | 909ret_bad_addr=true 910ret_data16=65535 911ret_data32=4294967295 912ret_data64=18446744073709551615 913ret_data8=255 914system=system 915update_data=false 916warn_access= --- 28 unchanged lines hidden (view full) --- 945activation_limit=4 946addr_mapping=RoRaBaCoCh 947bank_groups_per_rank=0 948banks_per_rank=8 949burst_length=8 950channels=1 951clk_domain=system.clk_domain 952conf_table_reported=true |
| 953default_p_state=UNDEFINED |
|
| 869device_bus_width=8 870device_rowbuffer_size=1024 871device_size=536870912 872devices_per_rank=8 873dll=true 874eventq_index=0 875in_addr_map=true 876max_accesses_per_row=16 877mem_sched_policy=frfcfs 878min_writes_per_switch=16 879null=false | 954device_bus_width=8 955device_rowbuffer_size=1024 956device_size=536870912 957devices_per_rank=8 958dll=true 959eventq_index=0 960in_addr_map=true 961max_accesses_per_row=16 962mem_sched_policy=frfcfs 963min_writes_per_switch=16 964null=false |
| 965p_state_clk_gate_bins=20 966p_state_clk_gate_max=1000000000000 967p_state_clk_gate_min=1000 |
|
| 880page_policy=open_adaptive | 968page_policy=open_adaptive |
| 969power_model=Null |
|
| 881range=0:134217727 882ranks_per_channel=2 883read_buffer_size=32 884static_backend_latency=10000 885static_frontend_latency=10000 886tBURST=5000 887tCCD_L=0 888tCK=1250 --- 25 unchanged lines hidden (view full) --- 914children=disk 915disk=system.simple_disk.disk 916eventq_index=0 917system=system 918 919[system.simple_disk.disk] 920type=RawDiskImage 921eventq_index=0 | 970range=0:134217727 971ranks_per_channel=2 972read_buffer_size=32 973static_backend_latency=10000 974static_frontend_latency=10000 975tBURST=5000 976tCCD_L=0 977tCK=1250 --- 25 unchanged lines hidden (view full) --- 1003children=disk 1004disk=system.simple_disk.disk 1005eventq_index=0 1006system=system 1007 1008[system.simple_disk.disk] 1009type=RawDiskImage 1010eventq_index=0 |
| 922image_file=/work/gem5/dist/disks/linux-latest.img | 1011image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img |
| 923read_only=true 924 925[system.terminal] 926type=Terminal 927eventq_index=0 928intr_control=system.intrctrl 929number=0 930output=true --- 5 unchanged lines hidden (view full) --- 936eventq_index=0 937intrctrl=system.intrctrl 938system=system 939 940[system.tsunami.backdoor] 941type=AlphaBackdoor 942clk_domain=system.clk_domain 943cpu=system.cpu | 1012read_only=true 1013 1014[system.terminal] 1015type=Terminal 1016eventq_index=0 1017intr_control=system.intrctrl 1018number=0 1019output=true --- 5 unchanged lines hidden (view full) --- 1025eventq_index=0 1026intrctrl=system.intrctrl 1027system=system 1028 1029[system.tsunami.backdoor] 1030type=AlphaBackdoor 1031clk_domain=system.clk_domain 1032cpu=system.cpu |
| 1033default_p_state=UNDEFINED |
|
| 944disk=system.simple_disk 945eventq_index=0 | 1034disk=system.simple_disk 1035eventq_index=0 |
| 1036p_state_clk_gate_bins=20 1037p_state_clk_gate_max=1000000000000 1038p_state_clk_gate_min=1000 |
|
| 946pio_addr=8804682956800 947pio_latency=100000 948platform=system.tsunami | 1039pio_addr=8804682956800 1040pio_latency=100000 1041platform=system.tsunami |
| 1042power_model=Null |
|
| 949system=system 950terminal=system.terminal 951pio=system.iobus.master[24] 952 953[system.tsunami.cchip] 954type=TsunamiCChip 955clk_domain=system.clk_domain | 1043system=system 1044terminal=system.terminal 1045pio=system.iobus.master[24] 1046 1047[system.tsunami.cchip] 1048type=TsunamiCChip 1049clk_domain=system.clk_domain |
| 1050default_p_state=UNDEFINED |
|
| 956eventq_index=0 | 1051eventq_index=0 |
| 1052p_state_clk_gate_bins=20 1053p_state_clk_gate_max=1000000000000 1054p_state_clk_gate_min=1000 |
|
| 957pio_addr=8803072344064 958pio_latency=100000 | 1055pio_addr=8803072344064 1056pio_latency=100000 |
| 1057power_model=Null |
|
| 959system=system 960tsunami=system.tsunami 961pio=system.iobus.master[0] 962 963[system.tsunami.ethernet] 964type=NSGigE 965BAR0=1 966BAR0LegacyIO=false --- 64 unchanged lines hidden (view full) --- 1031Revision=0 1032Status=656 1033SubClassCode=0 1034SubsystemID=0 1035SubsystemVendorID=0 1036VendorID=4107 1037clk_domain=system.clk_domain 1038config_latency=20000 | 1058system=system 1059tsunami=system.tsunami 1060pio=system.iobus.master[0] 1061 1062[system.tsunami.ethernet] 1063type=NSGigE 1064BAR0=1 1065BAR0LegacyIO=false --- 64 unchanged lines hidden (view full) --- 1130Revision=0 1131Status=656 1132SubClassCode=0 1133SubsystemID=0 1134SubsystemVendorID=0 1135VendorID=4107 1136clk_domain=system.clk_domain 1137config_latency=20000 |
| 1138default_p_state=UNDEFINED |
|
| 1039dma_data_free=false 1040dma_desc_free=false 1041dma_no_allocate=true 1042dma_read_delay=0 1043dma_read_factor=0 1044dma_write_delay=0 1045dma_write_factor=0 1046eventq_index=0 1047hardware_address=00:90:00:00:00:01 1048host=system.tsunami.pchip 1049intr_delay=10000000 | 1139dma_data_free=false 1140dma_desc_free=false 1141dma_no_allocate=true 1142dma_read_delay=0 1143dma_read_factor=0 1144dma_write_delay=0 1145dma_write_factor=0 1146eventq_index=0 1147hardware_address=00:90:00:00:00:01 1148host=system.tsunami.pchip 1149intr_delay=10000000 |
| 1150p_state_clk_gate_bins=20 1151p_state_clk_gate_max=1000000000000 1152p_state_clk_gate_min=1000 |
|
| 1050pci_bus=0 1051pci_dev=1 1052pci_func=0 1053pio_latency=30000 | 1153pci_bus=0 1154pci_dev=1 1155pci_func=0 1156pio_latency=30000 |
| 1157power_model=Null |
|
| 1054rss=false 1055rx_delay=1000000 1056rx_fifo_size=524288 1057rx_filter=true 1058rx_thread=false 1059system=system 1060tx_delay=1000000 1061tx_fifo_size=524288 1062tx_thread=false 1063dma=system.iobus.slave[2] 1064pio=system.iobus.master[26] 1065 1066[system.tsunami.fake_OROM] 1067type=IsaFake 1068clk_domain=system.clk_domain | 1158rss=false 1159rx_delay=1000000 1160rx_fifo_size=524288 1161rx_filter=true 1162rx_thread=false 1163system=system 1164tx_delay=1000000 1165tx_fifo_size=524288 1166tx_thread=false 1167dma=system.iobus.slave[2] 1168pio=system.iobus.master[26] 1169 1170[system.tsunami.fake_OROM] 1171type=IsaFake 1172clk_domain=system.clk_domain |
| 1173default_p_state=UNDEFINED |
|
| 1069eventq_index=0 1070fake_mem=false | 1174eventq_index=0 1175fake_mem=false |
| 1176p_state_clk_gate_bins=20 1177p_state_clk_gate_max=1000000000000 1178p_state_clk_gate_min=1000 |
|
| 1071pio_addr=8796093677568 1072pio_latency=100000 1073pio_size=393216 | 1179pio_addr=8796093677568 1180pio_latency=100000 1181pio_size=393216 |
| 1182power_model=Null |
|
| 1074ret_bad_addr=false 1075ret_data16=65535 1076ret_data32=4294967295 1077ret_data64=18446744073709551615 1078ret_data8=255 1079system=system 1080update_data=false 1081warn_access= 1082pio=system.iobus.master[8] 1083 1084[system.tsunami.fake_ata0] 1085type=IsaFake 1086clk_domain=system.clk_domain | 1183ret_bad_addr=false 1184ret_data16=65535 1185ret_data32=4294967295 1186ret_data64=18446744073709551615 1187ret_data8=255 1188system=system 1189update_data=false 1190warn_access= 1191pio=system.iobus.master[8] 1192 1193[system.tsunami.fake_ata0] 1194type=IsaFake 1195clk_domain=system.clk_domain |
| 1196default_p_state=UNDEFINED |
|
| 1087eventq_index=0 1088fake_mem=false | 1197eventq_index=0 1198fake_mem=false |
| 1199p_state_clk_gate_bins=20 1200p_state_clk_gate_max=1000000000000 1201p_state_clk_gate_min=1000 |
|
| 1089pio_addr=8804615848432 1090pio_latency=100000 1091pio_size=8 | 1202pio_addr=8804615848432 1203pio_latency=100000 1204pio_size=8 |
| 1205power_model=Null |
|
| 1092ret_bad_addr=false 1093ret_data16=65535 1094ret_data32=4294967295 1095ret_data64=18446744073709551615 1096ret_data8=255 1097system=system 1098update_data=false 1099warn_access= 1100pio=system.iobus.master[19] 1101 1102[system.tsunami.fake_ata1] 1103type=IsaFake 1104clk_domain=system.clk_domain | 1206ret_bad_addr=false 1207ret_data16=65535 1208ret_data32=4294967295 1209ret_data64=18446744073709551615 1210ret_data8=255 1211system=system 1212update_data=false 1213warn_access= 1214pio=system.iobus.master[19] 1215 1216[system.tsunami.fake_ata1] 1217type=IsaFake 1218clk_domain=system.clk_domain |
| 1219default_p_state=UNDEFINED |
|
| 1105eventq_index=0 1106fake_mem=false | 1220eventq_index=0 1221fake_mem=false |
| 1222p_state_clk_gate_bins=20 1223p_state_clk_gate_max=1000000000000 1224p_state_clk_gate_min=1000 |
|
| 1107pio_addr=8804615848304 1108pio_latency=100000 1109pio_size=8 | 1225pio_addr=8804615848304 1226pio_latency=100000 1227pio_size=8 |
| 1228power_model=Null |
|
| 1110ret_bad_addr=false 1111ret_data16=65535 1112ret_data32=4294967295 1113ret_data64=18446744073709551615 1114ret_data8=255 1115system=system 1116update_data=false 1117warn_access= 1118pio=system.iobus.master[20] 1119 1120[system.tsunami.fake_pnp_addr] 1121type=IsaFake 1122clk_domain=system.clk_domain | 1229ret_bad_addr=false 1230ret_data16=65535 1231ret_data32=4294967295 1232ret_data64=18446744073709551615 1233ret_data8=255 1234system=system 1235update_data=false 1236warn_access= 1237pio=system.iobus.master[20] 1238 1239[system.tsunami.fake_pnp_addr] 1240type=IsaFake 1241clk_domain=system.clk_domain |
| 1242default_p_state=UNDEFINED |
|
| 1123eventq_index=0 1124fake_mem=false | 1243eventq_index=0 1244fake_mem=false |
| 1245p_state_clk_gate_bins=20 1246p_state_clk_gate_max=1000000000000 1247p_state_clk_gate_min=1000 |
|
| 1125pio_addr=8804615848569 1126pio_latency=100000 1127pio_size=8 | 1248pio_addr=8804615848569 1249pio_latency=100000 1250pio_size=8 |
| 1251power_model=Null |
|
| 1128ret_bad_addr=false 1129ret_data16=65535 1130ret_data32=4294967295 1131ret_data64=18446744073709551615 1132ret_data8=255 1133system=system 1134update_data=false 1135warn_access= 1136pio=system.iobus.master[9] 1137 1138[system.tsunami.fake_pnp_read0] 1139type=IsaFake 1140clk_domain=system.clk_domain | 1252ret_bad_addr=false 1253ret_data16=65535 1254ret_data32=4294967295 1255ret_data64=18446744073709551615 1256ret_data8=255 1257system=system 1258update_data=false 1259warn_access= 1260pio=system.iobus.master[9] 1261 1262[system.tsunami.fake_pnp_read0] 1263type=IsaFake 1264clk_domain=system.clk_domain |
| 1265default_p_state=UNDEFINED |
|
| 1141eventq_index=0 1142fake_mem=false | 1266eventq_index=0 1267fake_mem=false |
| 1268p_state_clk_gate_bins=20 1269p_state_clk_gate_max=1000000000000 1270p_state_clk_gate_min=1000 |
|
| 1143pio_addr=8804615848451 1144pio_latency=100000 1145pio_size=8 | 1271pio_addr=8804615848451 1272pio_latency=100000 1273pio_size=8 |
| 1274power_model=Null |
|
| 1146ret_bad_addr=false 1147ret_data16=65535 1148ret_data32=4294967295 1149ret_data64=18446744073709551615 1150ret_data8=255 1151system=system 1152update_data=false 1153warn_access= 1154pio=system.iobus.master[11] 1155 1156[system.tsunami.fake_pnp_read1] 1157type=IsaFake 1158clk_domain=system.clk_domain | 1275ret_bad_addr=false 1276ret_data16=65535 1277ret_data32=4294967295 1278ret_data64=18446744073709551615 1279ret_data8=255 1280system=system 1281update_data=false 1282warn_access= 1283pio=system.iobus.master[11] 1284 1285[system.tsunami.fake_pnp_read1] 1286type=IsaFake 1287clk_domain=system.clk_domain |
| 1288default_p_state=UNDEFINED |
|
| 1159eventq_index=0 1160fake_mem=false | 1289eventq_index=0 1290fake_mem=false |
| 1291p_state_clk_gate_bins=20 1292p_state_clk_gate_max=1000000000000 1293p_state_clk_gate_min=1000 |
|
| 1161pio_addr=8804615848515 1162pio_latency=100000 1163pio_size=8 | 1294pio_addr=8804615848515 1295pio_latency=100000 1296pio_size=8 |
| 1297power_model=Null |
|
| 1164ret_bad_addr=false 1165ret_data16=65535 1166ret_data32=4294967295 1167ret_data64=18446744073709551615 1168ret_data8=255 1169system=system 1170update_data=false 1171warn_access= 1172pio=system.iobus.master[12] 1173 1174[system.tsunami.fake_pnp_read2] 1175type=IsaFake 1176clk_domain=system.clk_domain | 1298ret_bad_addr=false 1299ret_data16=65535 1300ret_data32=4294967295 1301ret_data64=18446744073709551615 1302ret_data8=255 1303system=system 1304update_data=false 1305warn_access= 1306pio=system.iobus.master[12] 1307 1308[system.tsunami.fake_pnp_read2] 1309type=IsaFake 1310clk_domain=system.clk_domain |
| 1311default_p_state=UNDEFINED |
|
| 1177eventq_index=0 1178fake_mem=false | 1312eventq_index=0 1313fake_mem=false |
| 1314p_state_clk_gate_bins=20 1315p_state_clk_gate_max=1000000000000 1316p_state_clk_gate_min=1000 |
|
| 1179pio_addr=8804615848579 1180pio_latency=100000 1181pio_size=8 | 1317pio_addr=8804615848579 1318pio_latency=100000 1319pio_size=8 |
| 1320power_model=Null |
|
| 1182ret_bad_addr=false 1183ret_data16=65535 1184ret_data32=4294967295 1185ret_data64=18446744073709551615 1186ret_data8=255 1187system=system 1188update_data=false 1189warn_access= 1190pio=system.iobus.master[13] 1191 1192[system.tsunami.fake_pnp_read3] 1193type=IsaFake 1194clk_domain=system.clk_domain | 1321ret_bad_addr=false 1322ret_data16=65535 1323ret_data32=4294967295 1324ret_data64=18446744073709551615 1325ret_data8=255 1326system=system 1327update_data=false 1328warn_access= 1329pio=system.iobus.master[13] 1330 1331[system.tsunami.fake_pnp_read3] 1332type=IsaFake 1333clk_domain=system.clk_domain |
| 1334default_p_state=UNDEFINED |
|
| 1195eventq_index=0 1196fake_mem=false | 1335eventq_index=0 1336fake_mem=false |
| 1337p_state_clk_gate_bins=20 1338p_state_clk_gate_max=1000000000000 1339p_state_clk_gate_min=1000 |
|
| 1197pio_addr=8804615848643 1198pio_latency=100000 1199pio_size=8 | 1340pio_addr=8804615848643 1341pio_latency=100000 1342pio_size=8 |
| 1343power_model=Null |
|
| 1200ret_bad_addr=false 1201ret_data16=65535 1202ret_data32=4294967295 1203ret_data64=18446744073709551615 1204ret_data8=255 1205system=system 1206update_data=false 1207warn_access= 1208pio=system.iobus.master[14] 1209 1210[system.tsunami.fake_pnp_read4] 1211type=IsaFake 1212clk_domain=system.clk_domain | 1344ret_bad_addr=false 1345ret_data16=65535 1346ret_data32=4294967295 1347ret_data64=18446744073709551615 1348ret_data8=255 1349system=system 1350update_data=false 1351warn_access= 1352pio=system.iobus.master[14] 1353 1354[system.tsunami.fake_pnp_read4] 1355type=IsaFake 1356clk_domain=system.clk_domain |
| 1357default_p_state=UNDEFINED |
|
| 1213eventq_index=0 1214fake_mem=false | 1358eventq_index=0 1359fake_mem=false |
| 1360p_state_clk_gate_bins=20 1361p_state_clk_gate_max=1000000000000 1362p_state_clk_gate_min=1000 |
|
| 1215pio_addr=8804615848707 1216pio_latency=100000 1217pio_size=8 | 1363pio_addr=8804615848707 1364pio_latency=100000 1365pio_size=8 |
| 1366power_model=Null |
|
| 1218ret_bad_addr=false 1219ret_data16=65535 1220ret_data32=4294967295 1221ret_data64=18446744073709551615 1222ret_data8=255 1223system=system 1224update_data=false 1225warn_access= 1226pio=system.iobus.master[15] 1227 1228[system.tsunami.fake_pnp_read5] 1229type=IsaFake 1230clk_domain=system.clk_domain | 1367ret_bad_addr=false 1368ret_data16=65535 1369ret_data32=4294967295 1370ret_data64=18446744073709551615 1371ret_data8=255 1372system=system 1373update_data=false 1374warn_access= 1375pio=system.iobus.master[15] 1376 1377[system.tsunami.fake_pnp_read5] 1378type=IsaFake 1379clk_domain=system.clk_domain |
| 1380default_p_state=UNDEFINED |
|
| 1231eventq_index=0 1232fake_mem=false | 1381eventq_index=0 1382fake_mem=false |
| 1383p_state_clk_gate_bins=20 1384p_state_clk_gate_max=1000000000000 1385p_state_clk_gate_min=1000 |
|
| 1233pio_addr=8804615848771 1234pio_latency=100000 1235pio_size=8 | 1386pio_addr=8804615848771 1387pio_latency=100000 1388pio_size=8 |
| 1389power_model=Null |
|
| 1236ret_bad_addr=false 1237ret_data16=65535 1238ret_data32=4294967295 1239ret_data64=18446744073709551615 1240ret_data8=255 1241system=system 1242update_data=false 1243warn_access= 1244pio=system.iobus.master[16] 1245 1246[system.tsunami.fake_pnp_read6] 1247type=IsaFake 1248clk_domain=system.clk_domain | 1390ret_bad_addr=false 1391ret_data16=65535 1392ret_data32=4294967295 1393ret_data64=18446744073709551615 1394ret_data8=255 1395system=system 1396update_data=false 1397warn_access= 1398pio=system.iobus.master[16] 1399 1400[system.tsunami.fake_pnp_read6] 1401type=IsaFake 1402clk_domain=system.clk_domain |
| 1403default_p_state=UNDEFINED |
|
| 1249eventq_index=0 1250fake_mem=false | 1404eventq_index=0 1405fake_mem=false |
| 1406p_state_clk_gate_bins=20 1407p_state_clk_gate_max=1000000000000 1408p_state_clk_gate_min=1000 |
|
| 1251pio_addr=8804615848835 1252pio_latency=100000 1253pio_size=8 | 1409pio_addr=8804615848835 1410pio_latency=100000 1411pio_size=8 |
| 1412power_model=Null |
|
| 1254ret_bad_addr=false 1255ret_data16=65535 1256ret_data32=4294967295 1257ret_data64=18446744073709551615 1258ret_data8=255 1259system=system 1260update_data=false 1261warn_access= 1262pio=system.iobus.master[17] 1263 1264[system.tsunami.fake_pnp_read7] 1265type=IsaFake 1266clk_domain=system.clk_domain | 1413ret_bad_addr=false 1414ret_data16=65535 1415ret_data32=4294967295 1416ret_data64=18446744073709551615 1417ret_data8=255 1418system=system 1419update_data=false 1420warn_access= 1421pio=system.iobus.master[17] 1422 1423[system.tsunami.fake_pnp_read7] 1424type=IsaFake 1425clk_domain=system.clk_domain |
| 1426default_p_state=UNDEFINED |
|
| 1267eventq_index=0 1268fake_mem=false | 1427eventq_index=0 1428fake_mem=false |
| 1429p_state_clk_gate_bins=20 1430p_state_clk_gate_max=1000000000000 1431p_state_clk_gate_min=1000 |
|
| 1269pio_addr=8804615848899 1270pio_latency=100000 1271pio_size=8 | 1432pio_addr=8804615848899 1433pio_latency=100000 1434pio_size=8 |
| 1435power_model=Null |
|
| 1272ret_bad_addr=false 1273ret_data16=65535 1274ret_data32=4294967295 1275ret_data64=18446744073709551615 1276ret_data8=255 1277system=system 1278update_data=false 1279warn_access= 1280pio=system.iobus.master[18] 1281 1282[system.tsunami.fake_pnp_write] 1283type=IsaFake 1284clk_domain=system.clk_domain | 1436ret_bad_addr=false 1437ret_data16=65535 1438ret_data32=4294967295 1439ret_data64=18446744073709551615 1440ret_data8=255 1441system=system 1442update_data=false 1443warn_access= 1444pio=system.iobus.master[18] 1445 1446[system.tsunami.fake_pnp_write] 1447type=IsaFake 1448clk_domain=system.clk_domain |
| 1449default_p_state=UNDEFINED |
|
| 1285eventq_index=0 1286fake_mem=false | 1450eventq_index=0 1451fake_mem=false |
| 1452p_state_clk_gate_bins=20 1453p_state_clk_gate_max=1000000000000 1454p_state_clk_gate_min=1000 |
|
| 1287pio_addr=8804615850617 1288pio_latency=100000 1289pio_size=8 | 1455pio_addr=8804615850617 1456pio_latency=100000 1457pio_size=8 |
| 1458power_model=Null |
|
| 1290ret_bad_addr=false 1291ret_data16=65535 1292ret_data32=4294967295 1293ret_data64=18446744073709551615 1294ret_data8=255 1295system=system 1296update_data=false 1297warn_access= 1298pio=system.iobus.master[10] 1299 1300[system.tsunami.fake_ppc] 1301type=IsaFake 1302clk_domain=system.clk_domain | 1459ret_bad_addr=false 1460ret_data16=65535 1461ret_data32=4294967295 1462ret_data64=18446744073709551615 1463ret_data8=255 1464system=system 1465update_data=false 1466warn_access= 1467pio=system.iobus.master[10] 1468 1469[system.tsunami.fake_ppc] 1470type=IsaFake 1471clk_domain=system.clk_domain |
| 1472default_p_state=UNDEFINED |
|
| 1303eventq_index=0 1304fake_mem=false | 1473eventq_index=0 1474fake_mem=false |
| 1475p_state_clk_gate_bins=20 1476p_state_clk_gate_max=1000000000000 1477p_state_clk_gate_min=1000 |
|
| 1305pio_addr=8804615848891 1306pio_latency=100000 1307pio_size=8 | 1478pio_addr=8804615848891 1479pio_latency=100000 1480pio_size=8 |
| 1481power_model=Null |
|
| 1308ret_bad_addr=false 1309ret_data16=65535 1310ret_data32=4294967295 1311ret_data64=18446744073709551615 1312ret_data8=255 1313system=system 1314update_data=false 1315warn_access= 1316pio=system.iobus.master[7] 1317 1318[system.tsunami.fake_sm_chip] 1319type=IsaFake 1320clk_domain=system.clk_domain | 1482ret_bad_addr=false 1483ret_data16=65535 1484ret_data32=4294967295 1485ret_data64=18446744073709551615 1486ret_data8=255 1487system=system 1488update_data=false 1489warn_access= 1490pio=system.iobus.master[7] 1491 1492[system.tsunami.fake_sm_chip] 1493type=IsaFake 1494clk_domain=system.clk_domain |
| 1495default_p_state=UNDEFINED |
|
| 1321eventq_index=0 1322fake_mem=false | 1496eventq_index=0 1497fake_mem=false |
| 1498p_state_clk_gate_bins=20 1499p_state_clk_gate_max=1000000000000 1500p_state_clk_gate_min=1000 |
|
| 1323pio_addr=8804615848816 1324pio_latency=100000 1325pio_size=8 | 1501pio_addr=8804615848816 1502pio_latency=100000 1503pio_size=8 |
| 1504power_model=Null |
|
| 1326ret_bad_addr=false 1327ret_data16=65535 1328ret_data32=4294967295 1329ret_data64=18446744073709551615 1330ret_data8=255 1331system=system 1332update_data=false 1333warn_access= 1334pio=system.iobus.master[2] 1335 1336[system.tsunami.fake_uart1] 1337type=IsaFake 1338clk_domain=system.clk_domain | 1505ret_bad_addr=false 1506ret_data16=65535 1507ret_data32=4294967295 1508ret_data64=18446744073709551615 1509ret_data8=255 1510system=system 1511update_data=false 1512warn_access= 1513pio=system.iobus.master[2] 1514 1515[system.tsunami.fake_uart1] 1516type=IsaFake 1517clk_domain=system.clk_domain |
| 1518default_p_state=UNDEFINED |
|
| 1339eventq_index=0 1340fake_mem=false | 1519eventq_index=0 1520fake_mem=false |
| 1521p_state_clk_gate_bins=20 1522p_state_clk_gate_max=1000000000000 1523p_state_clk_gate_min=1000 |
|
| 1341pio_addr=8804615848696 1342pio_latency=100000 1343pio_size=8 | 1524pio_addr=8804615848696 1525pio_latency=100000 1526pio_size=8 |
| 1527power_model=Null |
|
| 1344ret_bad_addr=false 1345ret_data16=65535 1346ret_data32=4294967295 1347ret_data64=18446744073709551615 1348ret_data8=255 1349system=system 1350update_data=false 1351warn_access= 1352pio=system.iobus.master[3] 1353 1354[system.tsunami.fake_uart2] 1355type=IsaFake 1356clk_domain=system.clk_domain | 1528ret_bad_addr=false 1529ret_data16=65535 1530ret_data32=4294967295 1531ret_data64=18446744073709551615 1532ret_data8=255 1533system=system 1534update_data=false 1535warn_access= 1536pio=system.iobus.master[3] 1537 1538[system.tsunami.fake_uart2] 1539type=IsaFake 1540clk_domain=system.clk_domain |
| 1541default_p_state=UNDEFINED |
|
| 1357eventq_index=0 1358fake_mem=false | 1542eventq_index=0 1543fake_mem=false |
| 1544p_state_clk_gate_bins=20 1545p_state_clk_gate_max=1000000000000 1546p_state_clk_gate_min=1000 |
|
| 1359pio_addr=8804615848936 1360pio_latency=100000 1361pio_size=8 | 1547pio_addr=8804615848936 1548pio_latency=100000 1549pio_size=8 |
| 1550power_model=Null |
|
| 1362ret_bad_addr=false 1363ret_data16=65535 1364ret_data32=4294967295 1365ret_data64=18446744073709551615 1366ret_data8=255 1367system=system 1368update_data=false 1369warn_access= 1370pio=system.iobus.master[4] 1371 1372[system.tsunami.fake_uart3] 1373type=IsaFake 1374clk_domain=system.clk_domain | 1551ret_bad_addr=false 1552ret_data16=65535 1553ret_data32=4294967295 1554ret_data64=18446744073709551615 1555ret_data8=255 1556system=system 1557update_data=false 1558warn_access= 1559pio=system.iobus.master[4] 1560 1561[system.tsunami.fake_uart3] 1562type=IsaFake 1563clk_domain=system.clk_domain |
| 1564default_p_state=UNDEFINED |
|
| 1375eventq_index=0 1376fake_mem=false | 1565eventq_index=0 1566fake_mem=false |
| 1567p_state_clk_gate_bins=20 1568p_state_clk_gate_max=1000000000000 1569p_state_clk_gate_min=1000 |
|
| 1377pio_addr=8804615848680 1378pio_latency=100000 1379pio_size=8 | 1570pio_addr=8804615848680 1571pio_latency=100000 1572pio_size=8 |
| 1573power_model=Null |
|
| 1380ret_bad_addr=false 1381ret_data16=65535 1382ret_data32=4294967295 1383ret_data64=18446744073709551615 1384ret_data8=255 1385system=system 1386update_data=false 1387warn_access= 1388pio=system.iobus.master[5] 1389 1390[system.tsunami.fake_uart4] 1391type=IsaFake 1392clk_domain=system.clk_domain | 1574ret_bad_addr=false 1575ret_data16=65535 1576ret_data32=4294967295 1577ret_data64=18446744073709551615 1578ret_data8=255 1579system=system 1580update_data=false 1581warn_access= 1582pio=system.iobus.master[5] 1583 1584[system.tsunami.fake_uart4] 1585type=IsaFake 1586clk_domain=system.clk_domain |
| 1587default_p_state=UNDEFINED |
|
| 1393eventq_index=0 1394fake_mem=false | 1588eventq_index=0 1589fake_mem=false |
| 1590p_state_clk_gate_bins=20 1591p_state_clk_gate_max=1000000000000 1592p_state_clk_gate_min=1000 |
|
| 1395pio_addr=8804615848944 1396pio_latency=100000 1397pio_size=8 | 1593pio_addr=8804615848944 1594pio_latency=100000 1595pio_size=8 |
| 1596power_model=Null |
|
| 1398ret_bad_addr=false 1399ret_data16=65535 1400ret_data32=4294967295 1401ret_data64=18446744073709551615 1402ret_data8=255 1403system=system 1404update_data=false 1405warn_access= 1406pio=system.iobus.master[6] 1407 1408[system.tsunami.fb] 1409type=BadDevice 1410clk_domain=system.clk_domain | 1597ret_bad_addr=false 1598ret_data16=65535 1599ret_data32=4294967295 1600ret_data64=18446744073709551615 1601ret_data8=255 1602system=system 1603update_data=false 1604warn_access= 1605pio=system.iobus.master[6] 1606 1607[system.tsunami.fb] 1608type=BadDevice 1609clk_domain=system.clk_domain |
| 1610default_p_state=UNDEFINED |
|
| 1411devicename=FrameBuffer 1412eventq_index=0 | 1611devicename=FrameBuffer 1612eventq_index=0 |
| 1613p_state_clk_gate_bins=20 1614p_state_clk_gate_max=1000000000000 1615p_state_clk_gate_min=1000 |
|
| 1413pio_addr=8804615848912 1414pio_latency=100000 | 1616pio_addr=8804615848912 1617pio_latency=100000 |
| 1618power_model=Null |
|
| 1415system=system 1416pio=system.iobus.master[21] 1417 1418[system.tsunami.ide] 1419type=IdeController 1420BAR0=1 1421BAR0LegacyIO=false 1422BAR0Size=8 --- 64 unchanged lines hidden (view full) --- 1487Status=640 1488SubClassCode=1 1489SubsystemID=0 1490SubsystemVendorID=0 1491VendorID=32902 1492clk_domain=system.clk_domain 1493config_latency=20000 1494ctrl_offset=0 | 1619system=system 1620pio=system.iobus.master[21] 1621 1622[system.tsunami.ide] 1623type=IdeController 1624BAR0=1 1625BAR0LegacyIO=false 1626BAR0Size=8 --- 64 unchanged lines hidden (view full) --- 1691Status=640 1692SubClassCode=1 1693SubsystemID=0 1694SubsystemVendorID=0 1695VendorID=32902 1696clk_domain=system.clk_domain 1697config_latency=20000 1698ctrl_offset=0 |
| 1699default_p_state=UNDEFINED |
|
| 1495disks=system.disk0 system.disk2 1496eventq_index=0 1497host=system.tsunami.pchip 1498io_shift=0 | 1700disks=system.disk0 system.disk2 1701eventq_index=0 1702host=system.tsunami.pchip 1703io_shift=0 |
| 1704p_state_clk_gate_bins=20 1705p_state_clk_gate_max=1000000000000 1706p_state_clk_gate_min=1000 |
|
| 1499pci_bus=0 1500pci_dev=0 1501pci_func=0 1502pio_latency=30000 | 1707pci_bus=0 1708pci_dev=0 1709pci_func=0 1710pio_latency=30000 |
| 1711power_model=Null |
|
| 1503system=system 1504dma=system.iobus.slave[1] 1505pio=system.iobus.master[25] 1506 1507[system.tsunami.io] 1508type=TsunamiIO 1509clk_domain=system.clk_domain | 1712system=system 1713dma=system.iobus.slave[1] 1714pio=system.iobus.master[25] 1715 1716[system.tsunami.io] 1717type=TsunamiIO 1718clk_domain=system.clk_domain |
| 1719default_p_state=UNDEFINED |
|
| 1510eventq_index=0 1511frequency=976562500 | 1720eventq_index=0 1721frequency=976562500 |
| 1722p_state_clk_gate_bins=20 1723p_state_clk_gate_max=1000000000000 1724p_state_clk_gate_min=1000 |
|
| 1512pio_addr=8804615847936 1513pio_latency=100000 | 1725pio_addr=8804615847936 1726pio_latency=100000 |
| 1727power_model=Null |
|
| 1514system=system 1515time=Thu Jan 1 00:00:00 2009 1516tsunami=system.tsunami 1517year_is_bcd=false 1518pio=system.iobus.master[22] 1519 1520[system.tsunami.pchip] 1521type=TsunamiPChip 1522clk_domain=system.clk_domain 1523conf_base=8804649402368 1524conf_device_bits=8 1525conf_size=16777216 | 1728system=system 1729time=Thu Jan 1 00:00:00 2009 1730tsunami=system.tsunami 1731year_is_bcd=false 1732pio=system.iobus.master[22] 1733 1734[system.tsunami.pchip] 1735type=TsunamiPChip 1736clk_domain=system.clk_domain 1737conf_base=8804649402368 1738conf_device_bits=8 1739conf_size=16777216 |
| 1740default_p_state=UNDEFINED |
|
| 1526eventq_index=0 | 1741eventq_index=0 |
| 1742p_state_clk_gate_bins=20 1743p_state_clk_gate_max=1000000000000 1744p_state_clk_gate_min=1000 |
|
| 1527pci_dma_base=0 1528pci_mem_base=8796093022208 1529pci_pio_base=8804615847936 1530pio_addr=8802535473152 1531pio_latency=100000 1532platform=system.tsunami | 1745pci_dma_base=0 1746pci_mem_base=8796093022208 1747pci_pio_base=8804615847936 1748pio_addr=8802535473152 1749pio_latency=100000 1750platform=system.tsunami |
| 1751power_model=Null |
|
| 1533system=system 1534tsunami=system.tsunami 1535pio=system.iobus.master[1] 1536 1537[system.tsunami.uart] 1538type=Uart8250 1539clk_domain=system.clk_domain | 1752system=system 1753tsunami=system.tsunami 1754pio=system.iobus.master[1] 1755 1756[system.tsunami.uart] 1757type=Uart8250 1758clk_domain=system.clk_domain |
| 1759default_p_state=UNDEFINED |
|
| 1540eventq_index=0 | 1760eventq_index=0 |
| 1761p_state_clk_gate_bins=20 1762p_state_clk_gate_max=1000000000000 1763p_state_clk_gate_min=1000 |
|
| 1541pio_addr=8804615848952 1542pio_latency=100000 1543platform=system.tsunami | 1764pio_addr=8804615848952 1765pio_latency=100000 1766platform=system.tsunami |
| 1767power_model=Null |
|
| 1544system=system 1545terminal=system.terminal 1546pio=system.iobus.master[23] 1547 1548[system.voltage_domain] 1549type=VoltageDomain 1550eventq_index=0 1551voltage=1.000000 1552 | 1768system=system 1769terminal=system.terminal 1770pio=system.iobus.master[23] 1771 1772[system.voltage_domain] 1773type=VoltageDomain 1774eventq_index=0 1775voltage=1.000000 1776 |