twosys-tsunami-simple-atomic.py (9728:7daeab1685e9) twosys-tsunami-simple-atomic.py (9790:ccc428657233)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from FSConfig import *
33from Benchmarks import *
34
35test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
36 SysConfig('netperf-stream-client.rcS'))
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 20 unchanged lines hidden (view full) ---

29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from FSConfig import *
33from Benchmarks import *
34
35test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
36 SysConfig('netperf-stream-client.rcS'))
37test_sys.clock = '1GHz'
37test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
38# create the interrupt controller
39test_sys.cpu.createInterruptController()
40test_sys.cpu.connectAllPorts(test_sys.membus)
41test_sys.cpu.clock = '2GHz'
42# In contrast to the other (one-system) Tsunami configurations we do
43# not have an IO cache but instead rely on an IO bridge for accesses
44# from masters on the IO bus to the memory bus
45test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
46test_sys.iobridge.slave = test_sys.iobus.master
47test_sys.iobridge.master = test_sys.membus.slave
48
49drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
50 SysConfig('netperf-server.rcS'))
38test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
39# create the interrupt controller
40test_sys.cpu.createInterruptController()
41test_sys.cpu.connectAllPorts(test_sys.membus)
42test_sys.cpu.clock = '2GHz'
43# In contrast to the other (one-system) Tsunami configurations we do
44# not have an IO cache but instead rely on an IO bridge for accesses
45# from masters on the IO bus to the memory bus
46test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
47test_sys.iobridge.slave = test_sys.iobus.master
48test_sys.iobridge.master = test_sys.membus.slave
49
50drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
51 SysConfig('netperf-server.rcS'))
52drive_sys.clock = '1GHz'
51drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
52# create the interrupt controller
53drive_sys.cpu.createInterruptController()
54drive_sys.cpu.connectAllPorts(drive_sys.membus)
55drive_sys.cpu.clock = '4GHz'
56drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
57drive_sys.iobridge.slave = drive_sys.iobus.master
58drive_sys.iobridge.master = drive_sys.membus.slave
59
60root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
61
62maxtick = 199999999
53drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
54# create the interrupt controller
55drive_sys.cpu.createInterruptController()
56drive_sys.cpu.connectAllPorts(drive_sys.membus)
57drive_sys.cpu.clock = '4GHz'
58drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
59drive_sys.iobridge.slave = drive_sys.iobus.master
60drive_sys.iobridge.master = drive_sys.membus.slave
61
62root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
63
64maxtick = 199999999