twosys-tsunami-simple-atomic.py (9246:ab0f995552fc) twosys-tsunami-simple-atomic.py (9408:10a84dceab25)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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37test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
38# create the interrupt controller
39test_sys.cpu.createInterruptController()
40test_sys.cpu.connectAllPorts(test_sys.membus)
41test_sys.cpu.clock = '2GHz'
42# In contrast to the other (one-system) Tsunami configurations we do
43# not have an IO cache but instead rely on an IO bridge for accesses
44# from masters on the IO bus to the memory bus
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 28 unchanged lines hidden (view full) ---

37test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
38# create the interrupt controller
39test_sys.cpu.createInterruptController()
40test_sys.cpu.connectAllPorts(test_sys.membus)
41test_sys.cpu.clock = '2GHz'
42# In contrast to the other (one-system) Tsunami configurations we do
43# not have an IO cache but instead rely on an IO bridge for accesses
44# from masters on the IO bus to the memory bus
45test_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')])
45test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
46test_sys.iobridge.slave = test_sys.iobus.master
47test_sys.iobridge.master = test_sys.membus.slave
48
49drive_sys = makeLinuxAlphaSystem('atomic',
50 SysConfig('netperf-server.rcS'))
51drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
52# create the interrupt controller
53drive_sys.cpu.createInterruptController()
54drive_sys.cpu.connectAllPorts(drive_sys.membus)
55drive_sys.cpu.clock = '4GHz'
46test_sys.iobridge.slave = test_sys.iobus.master
47test_sys.iobridge.master = test_sys.membus.slave
48
49drive_sys = makeLinuxAlphaSystem('atomic',
50 SysConfig('netperf-server.rcS'))
51drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
52# create the interrupt controller
53drive_sys.cpu.createInterruptController()
54drive_sys.cpu.connectAllPorts(drive_sys.membus)
55drive_sys.cpu.clock = '4GHz'
56drive_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')])
56drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
57drive_sys.iobridge.slave = drive_sys.iobus.master
58drive_sys.iobridge.master = drive_sys.membus.slave
59
60root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
61
62maxtick = 199999999
57drive_sys.iobridge.slave = drive_sys.iobus.master
58drive_sys.iobridge.master = drive_sys.membus.slave
59
60root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
61
62maxtick = 199999999