twosys-tsunami-simple-atomic.py (8839:eeb293859255) twosys-tsunami-simple-atomic.py (8876:44f8e7bb7fdf)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from FSConfig import *
33from Benchmarks import *
34
35test_sys = makeLinuxAlphaSystem('atomic',
36 SysConfig('netperf-stream-client.rcS'))
37test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 21 unchanged lines hidden (view full) ---

30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from FSConfig import *
33from Benchmarks import *
34
35test_sys = makeLinuxAlphaSystem('atomic',
36 SysConfig('netperf-stream-client.rcS'))
37test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
38# create the interrupt controller
39test_sys.cpu.createInterruptController()
38test_sys.cpu.connectAllPorts(test_sys.membus)
39# In contrast to the other (one-system) Tsunami configurations we do
40# not have an IO cache but instead rely on an IO bridge for accesses
41# from masters on the IO bus to the memory bus
42test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
43 ranges = [AddrRange(0, '8GB')])
44test_sys.iobridge.slave = test_sys.iobus.master
45test_sys.iobridge.master = test_sys.membus.slave
46
47drive_sys = makeLinuxAlphaSystem('atomic',
48 SysConfig('netperf-server.rcS'))
49drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
40test_sys.cpu.connectAllPorts(test_sys.membus)
41# In contrast to the other (one-system) Tsunami configurations we do
42# not have an IO cache but instead rely on an IO bridge for accesses
43# from masters on the IO bus to the memory bus
44test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
45 ranges = [AddrRange(0, '8GB')])
46test_sys.iobridge.slave = test_sys.iobus.master
47test_sys.iobridge.master = test_sys.membus.slave
48
49drive_sys = makeLinuxAlphaSystem('atomic',
50 SysConfig('netperf-server.rcS'))
51drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
52# create the interrupt controller
53drive_sys.cpu.createInterruptController()
50drive_sys.cpu.connectAllPorts(drive_sys.membus)
51drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
52 ranges = [AddrRange(0, '8GB')])
53drive_sys.iobridge.slave = drive_sys.iobus.master
54drive_sys.iobridge.master = drive_sys.membus.slave
55
56root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
57
58maxtick = 199999999
54drive_sys.cpu.connectAllPorts(drive_sys.membus)
55drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
56 ranges = [AddrRange(0, '8GB')])
57drive_sys.iobridge.slave = drive_sys.iobus.master
58drive_sys.iobridge.master = drive_sys.membus.slave
59
60root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
61
62maxtick = 199999999