1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 15 unchanged lines hidden (view full) --- 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Lisa Hsu 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/') |
32from common import Benchmarks, FSConfig, SysPaths |
33 34test_sys = makeLinuxAlphaSystem('atomic', 35 SysConfig('netperf-stream-client.rcS')) |
36test_sys.kernel = SysPaths.binary('vmlinux') |
37 38# Dummy voltage domain for all test_sys clock domains 39test_sys.voltage_domain = VoltageDomain() 40 41# Create the system clock domain 42test_sys.clk_domain = SrcClockDomain(clock = '1GHz', 43 voltage_domain = test_sys.voltage_domain) 44 --- 20 unchanged lines hidden (view full) --- 65test_sys.iobridge.slave = test_sys.iobus.master 66test_sys.iobridge.master = test_sys.membus.slave 67 68test_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0]) 69test_sys.physmem.port = test_sys.membus.master 70 71drive_sys = makeLinuxAlphaSystem('atomic', 72 SysConfig('netperf-server.rcS')) |
73drive_sys.kernel = SysPaths.binary('vmlinux') |
74# Dummy voltage domain for all drive_sys clock domains 75drive_sys.voltage_domain = VoltageDomain() 76# Create the system clock domain 77drive_sys.clk_domain = SrcClockDomain(clock = '1GHz', 78 voltage_domain = 79 drive_sys.voltage_domain) 80drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) 81# create the interrupt controller --- 24 unchanged lines hidden --- |