tsunami-simple-timing.py (4876:a18cedc19da5) tsunami-simple-timing.py (4966:427e4677e589)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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48
49class L2(BaseCache):
50 block_size = 64
51 latency = '10ns'
52 mshrs = 92
53 tgts_per_mshr = 16
54 write_buffers = 8
55
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 39 unchanged lines hidden (view full) ---

48
49class L2(BaseCache):
50 block_size = 64
51 latency = '10ns'
52 mshrs = 92
53 tgts_per_mshr = 16
54 write_buffers = 8
55
56# ---------------------
57# I/O Cache
58# ---------------------
59class IOCache(BaseCache):
60 assoc = 8
61 block_size = 64
62 latency = '50ns'
63 mshrs = 20
64 size = '1kB'
65 tgts_per_mshr = 12
66 mem_side_filter_ranges=[AddrRange(0, Addr.max)]
67 cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
68
56#cpu
57cpu = TimingSimpleCPU(cpu_id=0)
58#the system
59system = FSConfig.makeLinuxAlphaSystem('timing')
60
61system.cpu = cpu
62#create the l1/l2 bus
63system.toL2Bus = Bus()
69#cpu
70cpu = TimingSimpleCPU(cpu_id=0)
71#the system
72system = FSConfig.makeLinuxAlphaSystem('timing')
73
74system.cpu = cpu
75#create the l1/l2 bus
76system.toL2Bus = Bus()
77system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
78system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
79system.iocache = IOCache()
80system.iocache.cpu_side = system.iobus.port
81system.iocache.mem_side = system.membus.port
64
82
83
65#connect up the l2 cache
66system.l2c = L2(size='4MB', assoc=8)
67system.l2c.cpu_side = system.toL2Bus.port
68system.l2c.mem_side = system.membus.port
69
70#connect up the cpu and l1s
71cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
72 L1(size = '32kB', assoc = 4))
73# connect cpu level-1 caches to shared level-2 cache
74cpu.connectMemPorts(system.toL2Bus)
75cpu.clock = '2GHz'
76
77root = Root(system=system)
78m5.ticks.setGlobalFrequency('1THz')
79
84#connect up the l2 cache
85system.l2c = L2(size='4MB', assoc=8)
86system.l2c.cpu_side = system.toL2Bus.port
87system.l2c.mem_side = system.membus.port
88
89#connect up the cpu and l1s
90cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
91 L1(size = '32kB', assoc = 4))
92# connect cpu level-1 caches to shared level-2 cache
93cpu.connectMemPorts(system.toL2Bus)
94cpu.clock = '2GHz'
95
96root = Root(system=system)
97m5.ticks.setGlobalFrequency('1THz')
98