1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33from Caches import *
34
35#cpu
36cpu = TimingSimpleCPU(cpu_id=0)
37#the system
38system = FSConfig.makeLinuxAlphaSystem('timing')
39
40system.cpu = cpu
41
42#create the iocache
43system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
44system.iocache.cpu_side = system.iobus.master
45system.iocache.mem_side = system.membus.slave
46
47#connect up the cpu and caches
48cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
49 L1(size = '32kB', assoc = 4),
50 L2(size = '4MB', assoc = 8))
51# create the interrupt controller
52cpu.createInterruptController()
53# connect cpu and caches to the rest of the system
54cpu.connectAllPorts(system.membus)
55# set the cpu clock along with the caches and l1-l2 bus
56cpu.clock = '2GHz'
57
58root = Root(full_system=True, system=system)
59m5.ticks.setGlobalFrequency('1THz')
60