1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31m5.util.addToPath('../configs/common') 32import FSConfig 33 34# -------------------- 35# Base L1 Cache 36# ==================== 37 38class L1(BaseCache): |
39 hit_latency = 2 40 response_latency = 2 |
41 block_size = 64 42 mshrs = 4 43 tgts_per_mshr = 8 44 is_top_level = True 45 46# ---------------------- 47# Base L2 Cache 48# ---------------------- 49 50class L2(BaseCache): 51 block_size = 64 |
52 hit_latency = 20 53 response_latency = 20 |
54 mshrs = 92 55 tgts_per_mshr = 16 56 write_buffers = 8 57 58# --------------------- 59# I/O Cache 60# --------------------- 61class IOCache(BaseCache): 62 assoc = 8 63 block_size = 64 |
64 hit_latency = 50 65 response_latency = 50 |
66 mshrs = 20 67 size = '1kB' 68 tgts_per_mshr = 12 69 addr_ranges = [AddrRange(0, size='8GB')] 70 forward_snoops = False 71 is_top_level = True 72 73#cpu 74cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] 75#the system 76system = FSConfig.makeLinuxAlphaSystem('timing') |
77system.iocache = IOCache(clock = '1GHz') |
78system.iocache.cpu_side = system.iobus.master 79system.iocache.mem_side = system.membus.slave 80 81system.cpu = cpus 82#create the l1/l2 bus |
83system.toL2Bus = CoherentBus(clock = '2GHz') |
84 85#connect up the l2 cache |
86system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) |
87system.l2c.cpu_side = system.toL2Bus.master 88system.l2c.mem_side = system.membus.slave 89 90#connect up the cpu and l1s 91for c in cpus: 92 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 93 L1(size = '32kB', assoc = 4)) 94 # create the interrupt controller 95 c.createInterruptController() 96 # connect cpu level-1 caches to shared level-2 cache 97 c.connectAllPorts(system.toL2Bus, system.membus) 98 c.clock = '2GHz' 99 100root = Root(full_system=True, system=system) 101m5.ticks.setGlobalFrequency('1THz') 102 103 |