1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 69 unchanged lines hidden (view full) --- 78system.cpu = cpus 79#create the l1/l2 bus 80system.toL2Bus = Bus() 81 82#connect up the l2 cache 83system.l2c = L2(size='4MB', assoc=8) 84system.l2c.cpu_side = system.toL2Bus.port 85system.l2c.mem_side = system.membus.port |
86 87#connect up the cpu and l1s 88for c in cpus: 89 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 90 L1(size = '32kB', assoc = 4)) 91 # connect cpu level-1 caches to shared level-2 cache 92 c.connectAllPorts(system.toL2Bus, system.membus) 93 c.clock = '2GHz' 94 95root = Root(full_system=True, system=system) 96m5.ticks.setGlobalFrequency('1THz') 97 98 |