tsunami-simple-atomic.py (8883:c92153af04ac) tsunami-simple-atomic.py (9036:6385cf85bf12)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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72#the system
73system = FSConfig.makeLinuxAlphaSystem('atomic')
74system.iocache = IOCache()
75system.iocache.cpu_side = system.iobus.master
76system.iocache.mem_side = system.membus.slave
77
78system.cpu = cpu
79#create the l1/l2 bus
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 63 unchanged lines hidden (view full) ---

72#the system
73system = FSConfig.makeLinuxAlphaSystem('atomic')
74system.iocache = IOCache()
75system.iocache.cpu_side = system.iobus.master
76system.iocache.mem_side = system.membus.slave
77
78system.cpu = cpu
79#create the l1/l2 bus
80system.toL2Bus = Bus()
80system.toL2Bus = CoherentBus()
81
82#connect up the l2 cache
83system.l2c = L2(size='4MB', assoc=8)
84system.l2c.cpu_side = system.toL2Bus.master
85system.l2c.mem_side = system.membus.slave
86
87#connect up the cpu and l1s
88cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
89 L1(size = '32kB', assoc = 4))
90# create the interrupt controller
91cpu.createInterruptController()
92# connect cpu level-1 caches to shared level-2 cache
93cpu.connectAllPorts(system.toL2Bus, system.membus)
94cpu.clock = '2GHz'
95
96root = Root(full_system=True, system=system)
97m5.ticks.setGlobalFrequency('1THz')
98
81
82#connect up the l2 cache
83system.l2c = L2(size='4MB', assoc=8)
84system.l2c.cpu_side = system.toL2Bus.master
85system.l2c.mem_side = system.membus.slave
86
87#connect up the cpu and l1s
88cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
89 L1(size = '32kB', assoc = 4))
90# create the interrupt controller
91cpu.createInterruptController()
92# connect cpu level-1 caches to shared level-2 cache
93cpu.connectAllPorts(system.toL2Bus, system.membus)
94cpu.clock = '2GHz'
95
96root = Root(full_system=True, system=system)
97m5.ticks.setGlobalFrequency('1THz')
98