| tsunami-simple-atomic.py (8839:eeb293859255) | tsunami-simple-atomic.py (8876:44f8e7bb7fdf) |
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| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 73 unchanged lines hidden (view full) --- 82#connect up the l2 cache 83system.l2c = L2(size='4MB', assoc=8) 84system.l2c.cpu_side = system.toL2Bus.master 85system.l2c.mem_side = system.membus.slave 86 87#connect up the cpu and l1s 88cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 89 L1(size = '32kB', assoc = 4)) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 73 unchanged lines hidden (view full) --- 82#connect up the l2 cache 83system.l2c = L2(size='4MB', assoc=8) 84system.l2c.cpu_side = system.toL2Bus.master 85system.l2c.mem_side = system.membus.slave 86 87#connect up the cpu and l1s 88cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 89 L1(size = '32kB', assoc = 4)) |
| 90# create the interrupt controller 91cpu.createInterruptController() |
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| 90# connect cpu level-1 caches to shared level-2 cache 91cpu.connectAllPorts(system.toL2Bus, system.membus) 92cpu.clock = '2GHz' 93 94root = Root(full_system=True, system=system) 95m5.ticks.setGlobalFrequency('1THz') 96 | 92# connect cpu level-1 caches to shared level-2 cache 93cpu.connectAllPorts(system.toL2Bus, system.membus) 94cpu.clock = '2GHz' 95 96root = Root(full_system=True, system=system) 97m5.ticks.setGlobalFrequency('1THz') 98 |