tsunami-simple-atomic.py (8134:b01a51ff05fa) tsunami-simple-atomic.py (8713:2f1a3e335255)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 57 unchanged lines hidden (view full) ---

66 addr_range=AddrRange(0, size='8GB')
67 forward_snoops = False
68 is_top_level = True
69
70#cpu
71cpu = AtomicSimpleCPU(cpu_id=0)
72#the system
73system = FSConfig.makeLinuxAlphaSystem('atomic')
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 57 unchanged lines hidden (view full) ---

66 addr_range=AddrRange(0, size='8GB')
67 forward_snoops = False
68 is_top_level = True
69
70#cpu
71cpu = AtomicSimpleCPU(cpu_id=0)
72#the system
73system = FSConfig.makeLinuxAlphaSystem('atomic')
74system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
75system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
76system.iocache = IOCache()
77system.iocache.cpu_side = system.iobus.port
78system.iocache.mem_side = system.membus.port
79
80system.cpu = cpu
81#create the l1/l2 bus
82system.toL2Bus = Bus()
83

--- 15 unchanged lines hidden --- 		74system.iocache = IOCache()
75system.iocache.cpu_side = system.iobus.port
76system.iocache.mem_side = system.membus.port
77
78system.cpu = cpu
79#create the l1/l2 bus
80system.toL2Bus = Bus()
81

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