tsunami-simple-atomic.py (4876:a18cedc19da5) tsunami-simple-atomic.py (4966:427e4677e589)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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47
48class L2(BaseCache):
49 block_size = 64
50 latency = '10ns'
51 mshrs = 92
52 tgts_per_mshr = 16
53 write_buffers = 8
54
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 38 unchanged lines hidden (view full) ---

47
48class L2(BaseCache):
49 block_size = 64
50 latency = '10ns'
51 mshrs = 92
52 tgts_per_mshr = 16
53 write_buffers = 8
54
55# ---------------------
56# I/O Cache
57# ---------------------
58class IOCache(BaseCache):
59 assoc = 8
60 block_size = 64
61 latency = '50ns'
62 mshrs = 20
63 size = '1kB'
64 tgts_per_mshr = 12
65 mem_side_filter_ranges=[AddrRange(0, Addr.max)]
66 cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
67
55#cpu
56cpu = AtomicSimpleCPU(cpu_id=0)
57#the system
58system = FSConfig.makeLinuxAlphaSystem('atomic')
68#cpu
69cpu = AtomicSimpleCPU(cpu_id=0)
70#the system
71system = FSConfig.makeLinuxAlphaSystem('atomic')
72system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
73system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
74system.iocache = IOCache()
75system.iocache.cpu_side = system.iobus.port
76system.iocache.mem_side = system.membus.port
59
60system.cpu = cpu
61#create the l1/l2 bus
62system.toL2Bus = Bus()
63
64#connect up the l2 cache
65system.l2c = L2(size='4MB', assoc=8)
66system.l2c.cpu_side = system.toL2Bus.port

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78system.cpu = cpu
79#create the l1/l2 bus
80system.toL2Bus = Bus()
81
82#connect up the l2 cache
83system.l2c = L2(size='4MB', assoc=8)
84system.l2c.cpu_side = system.toL2Bus.port

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