1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31m5.util.addToPath('../configs/common') 32import FSConfig 33 34# -------------------- 35# Base L1 Cache 36# ==================== 37 38class L1(BaseCache): |
39 hit_latency = '1ns' 40 response_latency = '1ns' |
41 block_size = 64 42 mshrs = 4 43 tgts_per_mshr = 8 44 is_top_level = True 45 46# ---------------------- 47# Base L2 Cache 48# ---------------------- 49 50class L2(BaseCache): 51 block_size = 64 |
52 hit_latency = '10ns' 53 response_latency = '10ns' |
54 mshrs = 92 55 tgts_per_mshr = 16 56 write_buffers = 8 57 58# --------------------- 59# I/O Cache 60# --------------------- 61class IOCache(BaseCache): 62 assoc = 8 63 block_size = 64 |
64 hit_latency = '50ns' 65 response_latency = '50ns' |
66 mshrs = 20 67 size = '1kB' 68 tgts_per_mshr = 12 69 addr_ranges = [AddrRange(0, size='8GB')] 70 forward_snoops = False 71 is_top_level = True 72 73#cpu --- 28 unchanged lines hidden --- |