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>
> system.cpu = cpu
>
> #create the iocache
81,92c85,88
< system.cpu = cpu
< #create the l1/l2 bus
< system.toL2Bus = CoherentBus()
<
< #connect up the l2 cache
< system.l2c = L2(size='4MB', assoc=8)
< system.l2c.cpu_side = system.toL2Bus.master
< system.l2c.mem_side = system.membus.slave
<
< #connect up the cpu and l1s
< cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
< L1(size = '32kB', assoc = 4))
---
> #connect up the cpu and caches
> cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
> L1(size = '32kB', assoc = 4),
> L2(size = '4MB', assoc = 8))
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< # connect cpu level-1 caches to shared level-2 cache
< cpu.connectAllPorts(system.toL2Bus, system.membus)
---
> # connect cpu and caches to the rest of the system
> cpu.connectAllPorts(system.membus)
> # set the cpu clock along with the caches and l1-l2 bus