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> # --------------------
> # Base L1 Cache
> # ====================
>
> class L1(BaseCache):
> latency = '1ns'
> block_size = 64
> mshrs = 4
> tgts_per_mshr = 8
> protocol = CoherenceProtocol(protocol='moesi')
>
> # ----------------------
> # Base L2 Cache
> # ----------------------
>
> class L2(BaseCache):
> block_size = 64
> latency = '10ns'
> mshrs = 92
> tgts_per_mshr = 16
> write_buffers = 8
>
> #cpu
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> #the system
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>
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< cpu.connectMemPorts(system.membus)
---
> #create the l1/l2 bus
> system.toL2Bus = Bus()
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> #connect up the l2 cache
> system.l2c = L2(size='4MB', assoc=8)
> system.l2c.cpu_side = system.toL2Bus.port
> system.l2c.mem_side = system.membus.port
>
> #connect up the cpu and l1s
> cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
> L1(size = '32kB', assoc = 4))
> # connect cpu level-1 caches to shared level-2 cache
> cpu.connectMemPorts(system.toL2Bus)
> cpu.clock = '2GHz'
>
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< m5.ticks.setGlobalFrequency('2GHz')
---
> m5.ticks.setGlobalFrequency('1THz')
>