1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33
34# --------------------
35# Base L1 Cache
36# ====================
37
38class L1(BaseCache):
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33
34# --------------------
35# Base L1 Cache
36# ====================
37
38class L1(BaseCache):
|
63 mshrs = 20
64 size = '1kB'
65 tgts_per_mshr = 12
66 addr_ranges = [AddrRange(0, size='8GB')]
67 forward_snoops = False
68 is_top_level = True
69
70#cpu
71cpu = AtomicSimpleCPU(cpu_id=0)
72#the system
73system = FSConfig.makeLinuxAlphaSystem('atomic')
74system.iocache = IOCache()
75system.iocache.cpu_side = system.iobus.master
76system.iocache.mem_side = system.membus.slave
77
78system.cpu = cpu
79#create the l1/l2 bus
80system.toL2Bus = CoherentBus()
81
82#connect up the l2 cache
83system.l2c = L2(size='4MB', assoc=8)
84system.l2c.cpu_side = system.toL2Bus.master
85system.l2c.mem_side = system.membus.slave
86
87#connect up the cpu and l1s
88cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
89 L1(size = '32kB', assoc = 4))
90# create the interrupt controller
91cpu.createInterruptController()
92# connect cpu level-1 caches to shared level-2 cache
93cpu.connectAllPorts(system.toL2Bus, system.membus)
94cpu.clock = '2GHz'
95
96root = Root(full_system=True, system=system)
97m5.ticks.setGlobalFrequency('1THz')
98
| 66 mshrs = 20
67 size = '1kB'
68 tgts_per_mshr = 12
69 addr_ranges = [AddrRange(0, size='8GB')]
70 forward_snoops = False
71 is_top_level = True
72
73#cpu
74cpu = AtomicSimpleCPU(cpu_id=0)
75#the system
76system = FSConfig.makeLinuxAlphaSystem('atomic')
77system.iocache = IOCache()
78system.iocache.cpu_side = system.iobus.master
79system.iocache.mem_side = system.membus.slave
80
81system.cpu = cpu
82#create the l1/l2 bus
83system.toL2Bus = CoherentBus()
84
85#connect up the l2 cache
86system.l2c = L2(size='4MB', assoc=8)
87system.l2c.cpu_side = system.toL2Bus.master
88system.l2c.mem_side = system.membus.slave
89
90#connect up the cpu and l1s
91cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
92 L1(size = '32kB', assoc = 4))
93# create the interrupt controller
94cpu.createInterruptController()
95# connect cpu level-1 caches to shared level-2 cache
96cpu.connectAllPorts(system.toL2Bus, system.membus)
97cpu.clock = '2GHz'
98
99root = Root(full_system=True, system=system)
100m5.ticks.setGlobalFrequency('1THz')
101
|