tsunami-simple-atomic-dual.py (9310:aa7bf10e822a) tsunami-simple-atomic-dual.py (9315:2e00867b5001)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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40system.iocache.cpu_side = system.iobus.master
41system.iocache.mem_side = system.membus.slave
42
43system.cpu = cpus
44#create the l1/l2 bus
45system.toL2Bus = CoherentBus(clock = '2GHz')
46
47#connect up the l2 cache
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 31 unchanged lines hidden (view full) ---

40system.iocache.cpu_side = system.iobus.master
41system.iocache.mem_side = system.membus.slave
42
43system.cpu = cpus
44#create the l1/l2 bus
45system.toL2Bus = CoherentBus(clock = '2GHz')
46
47#connect up the l2 cache
48system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
48system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
49system.l2c.cpu_side = system.toL2Bus.master
50system.l2c.mem_side = system.membus.slave
51
52#connect up the cpu and l1s
53for c in cpus:
49system.l2c.cpu_side = system.toL2Bus.master
50system.l2c.mem_side = system.membus.slave
51
52#connect up the cpu and l1s
53for c in cpus:
54 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
55 L1(size = '32kB', assoc = 4))
54 c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
55 L1Cache(size = '32kB', assoc = 4))
56 # create the interrupt controller
57 c.createInterruptController()
58 # connect cpu level-1 caches to shared level-2 cache
59 c.connectAllPorts(system.toL2Bus, system.membus)
60 c.clock = '2GHz'
61
62root = Root(full_system=True, system=system)
63m5.ticks.setGlobalFrequency('1THz')
56 # create the interrupt controller
57 c.createInterruptController()
58 # connect cpu level-1 caches to shared level-2 cache
59 c.connectAllPorts(system.toL2Bus, system.membus)
60 c.clock = '2GHz'
61
62root = Root(full_system=True, system=system)
63m5.ticks.setGlobalFrequency('1THz')