tsunami-o3.py (9263:066099902102) | tsunami-o3.py (9282:ac627fdc8991) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 63 unchanged lines hidden (view full) --- 72 is_top_level = True 73 74#cpu 75cpu = DerivO3CPU(cpu_id=0) 76#the system 77system = FSConfig.makeLinuxAlphaSystem('timing') 78 79system.cpu = cpu | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 63 unchanged lines hidden (view full) --- 72 is_top_level = True 73 74#cpu 75cpu = DerivO3CPU(cpu_id=0) 76#the system 77system = FSConfig.makeLinuxAlphaSystem('timing') 78 79system.cpu = cpu |
80#create the l1/l2 bus 81system.toL2Bus = CoherentBus() | 80 81#create the iocache |
82system.iocache = IOCache() 83system.iocache.cpu_side = system.iobus.master 84system.iocache.mem_side = system.membus.slave 85 | 82system.iocache = IOCache() 83system.iocache.cpu_side = system.iobus.master 84system.iocache.mem_side = system.membus.slave 85 |
86 87#connect up the l2 cache 88system.l2c = L2(size='4MB', assoc=8) 89system.l2c.cpu_side = system.toL2Bus.master 90system.l2c.mem_side = system.membus.slave 91 92#connect up the cpu and l1s 93cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 94 L1(size = '32kB', assoc = 4)) | 86#connect up the cpu and caches 87cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), 88 L1(size = '32kB', assoc = 4), 89 L2(size = '4MB', assoc = 8)) |
95# create the interrupt controller 96cpu.createInterruptController() | 90# create the interrupt controller 91cpu.createInterruptController() |
97# connect cpu level-1 caches to shared level-2 cache 98cpu.connectAllPorts(system.toL2Bus, system.membus) | 92# connect cpu and caches to the rest of the system 93cpu.connectAllPorts(system.membus) 94# set the cpu clock along with the caches and l1-l2 bus |
99cpu.clock = '2GHz' 100 101root = Root(full_system=True, system=system) 102m5.ticks.setGlobalFrequency('1THz') 103 | 95cpu.clock = '2GHz' 96 97root = Root(full_system=True, system=system) 98m5.ticks.setGlobalFrequency('1THz') 99 |