| tsunami-o3.py (8839:eeb293859255) | tsunami-o3.py (8876:44f8e7bb7fdf) |
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| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 75 unchanged lines hidden (view full) --- 84#connect up the l2 cache 85system.l2c = L2(size='4MB', assoc=8) 86system.l2c.cpu_side = system.toL2Bus.master 87system.l2c.mem_side = system.membus.slave 88 89#connect up the cpu and l1s 90cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 91 L1(size = '32kB', assoc = 4)) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 75 unchanged lines hidden (view full) --- 84#connect up the l2 cache 85system.l2c = L2(size='4MB', assoc=8) 86system.l2c.cpu_side = system.toL2Bus.master 87system.l2c.mem_side = system.membus.slave 88 89#connect up the cpu and l1s 90cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 91 L1(size = '32kB', assoc = 4)) |
| 92# create the interrupt controller 93cpu.createInterruptController() |
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| 92# connect cpu level-1 caches to shared level-2 cache 93cpu.connectAllPorts(system.toL2Bus, system.membus) 94cpu.clock = '2GHz' 95 96root = Root(full_system=True, system=system) 97m5.ticks.setGlobalFrequency('1THz') 98 | 94# connect cpu level-1 caches to shared level-2 cache 95cpu.connectAllPorts(system.toL2Bus, system.membus) 96cpu.clock = '2GHz' 97 98root = Root(full_system=True, system=system) 99m5.ticks.setGlobalFrequency('1THz') 100 |