1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 27 unchanged lines hidden (view full) --- 36# Base L1 Cache 37# ==================== 38 39class L1(BaseCache): 40 latency = '1ns' 41 block_size = 64 42 mshrs = 4 43 tgts_per_mshr = 8 |
44 is_top_level = True |
45 46# ---------------------- 47# Base L2 Cache 48# ---------------------- 49 50class L2(BaseCache): 51 block_size = 64 52 latency = '10ns' --- 8 unchanged lines hidden (view full) --- 61 assoc = 8 62 block_size = 64 63 latency = '50ns' 64 mshrs = 20 65 size = '1kB' 66 tgts_per_mshr = 12 67 addr_range=AddrRange(0, size='8GB') 68 forward_snoops = False |
69 is_top_level = True |
70 71#cpu 72cpu = DerivO3CPU(cpu_id=0) 73#the system 74system = FSConfig.makeLinuxAlphaSystem('timing') 75 76system.cpu = cpu 77#create the l1/l2 bus --- 23 unchanged lines hidden --- |