1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 76 unchanged lines hidden (view full) --- 85system.l2c = L2(size='4MB', assoc=8) 86system.l2c.cpu_side = system.toL2Bus.port 87system.l2c.mem_side = system.membus.port 88 89#connect up the cpu and l1s 90cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 91 L1(size = '32kB', assoc = 4)) 92# connect cpu level-1 caches to shared level-2 cache |
93cpu.connectAllPorts(system.toL2Bus, system.membus) |
94cpu.clock = '2GHz' 95 96root = Root(system=system) 97m5.ticks.setGlobalFrequency('1THz') 98 |