tsunami-o3-dual.py (9288:3d6da8559605) tsunami-o3-dual.py (9310:aa7bf10e822a)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 16 unchanged lines hidden (view full) ---

25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33from Caches import *
33
34
34
35# --------------------
36# Base L1 Cache
37# ====================
38
39class L1(BaseCache):
40 hit_latency = 2
41 response_latency = 2
42 block_size = 64
43 mshrs = 4
44 tgts_per_mshr = 20
45 is_top_level = True
46
47# ----------------------
48# Base L2 Cache
49# ----------------------
50
51class L2(BaseCache):
52 block_size = 64
53 hit_latency = 20
54 response_latency = 20
55 mshrs = 92
56 tgts_per_mshr = 16
57 write_buffers = 8
58
59# ---------------------
60# I/O Cache
61# ---------------------
62class IOCache(BaseCache):
63 assoc = 8
64 block_size = 64
65 hit_latency = 50
66 response_latency = 50
67 mshrs = 20
68 size = '1kB'
69 tgts_per_mshr = 12
70 addr_ranges = [AddrRange(0, size='8GB')]
71 forward_snoops = False
72 is_top_level = True
73
74#cpu
75cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
76#the system
77system = FSConfig.makeLinuxAlphaSystem('timing')
78
79system.cpu = cpus
80#create the l1/l2 bus
81system.toL2Bus = CoherentBus(clock = '2GHz')
35#cpu
36cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
37#the system
38system = FSConfig.makeLinuxAlphaSystem('timing')
39
40system.cpu = cpus
41#create the l1/l2 bus
42system.toL2Bus = CoherentBus(clock = '2GHz')
82system.iocache = IOCache(clock = '1GHz')
43system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
83system.iocache.cpu_side = system.iobus.master
84system.iocache.mem_side = system.membus.slave
85
86
87#connect up the l2 cache
88system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
89system.l2c.cpu_side = system.toL2Bus.master
90system.l2c.mem_side = system.membus.slave

--- 14 unchanged lines hidden --- 		44system.iocache.cpu_side = system.iobus.master
45system.iocache.mem_side = system.membus.slave
46
47
48#connect up the l2 cache
49system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
50system.l2c.cpu_side = system.toL2Bus.master
51system.l2c.mem_side = system.membus.slave

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