tsunami-o3-dual.py (6978:ab05e20dc4a7) tsunami-o3-dual.py (7876:189b9b258779)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 78 unchanged lines hidden (view full) ---

87system.l2c.mem_side = system.membus.port
88system.l2c.num_cpus = 2
89
90#connect up the cpu and l1s
91for c in cpus:
92 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
93 L1(size = '32kB', assoc = 4))
94 # connect cpu level-1 caches to shared level-2 cache
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 78 unchanged lines hidden (view full) ---

87system.l2c.mem_side = system.membus.port
88system.l2c.num_cpus = 2
89
90#connect up the cpu and l1s
91for c in cpus:
92 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
93 L1(size = '32kB', assoc = 4))
94 # connect cpu level-1 caches to shared level-2 cache
95 c.connectMemPorts(system.toL2Bus)
95 c.connectAllPorts(system.toL2Bus, system.membus)
96 c.clock = '2GHz'
97
98root = Root(system=system)
99m5.ticks.setGlobalFrequency('1THz')
100
96 c.clock = '2GHz'
97
98root = Root(system=system)
99m5.ticks.setGlobalFrequency('1THz')
100