| tgen-simple-mem.py (9827:f47274776aa0) | tgen-simple-mem.py (10189:94d6ffac1e9b) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 41 unchanged lines hidden (view full) --- 50# system simulated 51system = System(cpu = cpu, physmem = SimpleMemory(), 52 membus = NoncoherentBus(width = 16), 53 clk_domain = SrcClockDomain(clock = '1GHz', 54 voltage_domain = 55 VoltageDomain())) 56 57# add a communication monitor, and also trace all the packets | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 41 unchanged lines hidden (view full) --- 50# system simulated 51system = System(cpu = cpu, physmem = SimpleMemory(), 52 membus = NoncoherentBus(width = 16), 53 clk_domain = SrcClockDomain(clock = '1GHz', 54 voltage_domain = 55 VoltageDomain())) 56 57# add a communication monitor, and also trace all the packets |
| 58system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz") | 58system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz", 59 trace_enable = True) |
| 59 60# connect the traffic generator to the bus via a communication monitor 61system.cpu.port = system.monitor.slave 62system.monitor.master = system.membus.slave 63 64# connect the system port even if it is not used in this example 65system.system_port = system.membus.slave 66 67# connect memory to the membus 68system.physmem.port = system.membus.master 69 70# ----------------------- 71# run simulation 72# ----------------------- 73 74root = Root(full_system = False, system = system) 75root.system.mem_mode = 'timing' | 60 61# connect the traffic generator to the bus via a communication monitor 62system.cpu.port = system.monitor.slave 63system.monitor.master = system.membus.slave 64 65# connect the system port even if it is not used in this example 66system.system_port = system.membus.slave 67 68# connect memory to the membus 69system.physmem.port = system.membus.master 70 71# ----------------------- 72# run simulation 73# ----------------------- 74 75root = Root(full_system = False, system = system) 76root.system.mem_mode = 'timing' |