| tgen-simple-mem.py (9242:256143419b40) | tgen-simple-mem.py (9398:6a348f61220c) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 32 unchanged lines hidden (view full) --- 41# even if this is only a traffic generator, call it cpu to make sure 42# the scripts are happy 43cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg") 44 45# system simulated 46system = System(cpu = cpu, physmem = SimpleMemory(), 47 membus = NoncoherentBus(clock="1GHz", width = 16)) 48 | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 32 unchanged lines hidden (view full) --- 41# even if this is only a traffic generator, call it cpu to make sure 42# the scripts are happy 43cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg") 44 45# system simulated 46system = System(cpu = cpu, physmem = SimpleMemory(), 47 membus = NoncoherentBus(clock="1GHz", width = 16)) 48 |
| 49# add a communication monitor 50system.monitor = CommMonitor() | 49# add a communication monitor, and also trace all the packets 50system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz") |
| 51 52# connect the traffic generator to the bus via a communication monitor 53system.cpu.port = system.monitor.slave 54system.monitor.master = system.membus.slave 55 56# connect the system port even if it is not used in this example 57system.system_port = system.membus.slave 58 59# connect memory to the membus 60system.physmem.port = system.membus.master 61 62# ----------------------- 63# run simulation 64# ----------------------- 65 66root = Root(full_system = False, system = system) 67root.system.mem_mode = 'timing' | 51 52# connect the traffic generator to the bus via a communication monitor 53system.cpu.port = system.monitor.slave 54system.monitor.master = system.membus.slave 55 56# connect the system port even if it is not used in this example 57system.system_port = system.membus.slave 58 59# connect memory to the membus 60system.physmem.port = system.membus.master 61 62# ----------------------- 63# run simulation 64# ----------------------- 65 66root = Root(full_system = False, system = system) 67root.system.mem_mode = 'timing' |