| tgen-simple-mem.py (10720:67b3e74de9ae) | tgen-simple-mem.py (10995:a114e2712642) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 43 unchanged lines hidden (view full) --- 52 membus = IOXBar(width = 16), 53 clk_domain = SrcClockDomain(clock = '1GHz', 54 voltage_domain = 55 VoltageDomain())) 56 57# add a communication monitor, and also trace all the packets and 58# calculate and verify stack distance 59system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz", | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 43 unchanged lines hidden (view full) --- 52 membus = IOXBar(width = 16), 53 clk_domain = SrcClockDomain(clock = '1GHz', 54 voltage_domain = 55 VoltageDomain())) 56 57# add a communication monitor, and also trace all the packets and 58# calculate and verify stack distance 59system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz", |
| 60 trace_enable = True, 61 stack_dist_calc = StackDistCalc(verify = True)) | 60 trace_enable = True) 61system.monitor.stackdist = StackDistProbe(verify = True) |
| 62 63# connect the traffic generator to the bus via a communication monitor 64system.cpu.port = system.monitor.slave 65system.monitor.master = system.membus.slave 66 67# connect the system port even if it is not used in this example 68system.system_port = system.membus.slave 69 70# connect memory to the membus 71system.physmem.port = system.membus.master 72 73# ----------------------- 74# run simulation 75# ----------------------- 76 77root = Root(full_system = False, system = system) 78root.system.mem_mode = 'timing' | 62 63# connect the traffic generator to the bus via a communication monitor 64system.cpu.port = system.monitor.slave 65system.monitor.master = system.membus.slave 66 67# connect the system port even if it is not used in this example 68system.system_port = system.membus.slave 69 70# connect memory to the membus 71system.physmem.port = system.membus.master 72 73# ----------------------- 74# run simulation 75# ----------------------- 76 77root = Root(full_system = False, system = system) 78root.system.mem_mode = 'timing' |