1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 35 unchanged lines hidden (view full) --- 44require_sim_object("CommMonitor") 45 46# even if this is only a traffic generator, call it cpu to make sure 47# the scripts are happy 48cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg") 49 50# system simulated 51system = System(cpu = cpu, physmem = SimpleMemory(), |
52 membus = NoncoherentBus(width = 16)) |
53 54# add a communication monitor, and also trace all the packets 55system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz") 56 57# connect the traffic generator to the bus via a communication monitor 58system.cpu.port = system.monitor.slave 59system.monitor.master = system.membus.slave 60 --- 12 unchanged lines hidden --- |